INTEGRATED CIRCUITS DATA SHEET P82C150 CAN Serial Linked I/O device (SLIO) with digital and analog port functions Preliminary specification Supersedes data of 1995 Oct 11 File under Integrated Circuits, IC18 1996 Jun 19 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 FUNCTIONAL DIAGRAM 6 PINNING INFORMATION 6.1 6.2 Pinning Pin description 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 I/O functions I/O registers CAN functions Initialization P82C150 operation after RESET or change of bus mode 8 LIMITING VALUES 9 DC CHARACTERISTICS 10 AC CHARACTERISTICS 11 APPLICATION INFORMATION 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Maximum bus length Start up sequence External oscillator mode Using digital I/O port functions Using DPM Using ADC Using analog input port functions CAN-bus system applications 12 PACKAGE OUTLINE 13 SOLDERING 13.1 13.2 13.3 13.4 Introduction Reflow soldering Wave soldering Repairing soldered joints 14 DEFINITIONS 15 LIFE SUPPORT APPLICATIONS 1996 Jun 19 2 P82C150 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 1 FEATURES 2 • Single-chip I/O device with CAN protocol controller P82C150 GENERAL DESCRIPTION The P82C150 is a single-chip 16-bit I/O device including a Controller Area Network (CAN) protocol controller with automatic bit rate detection and calibration. It features 16 configurable I/O port pins with programmable direction, digital and analog modes. • Meets CAN protocol specification version 2.0 A and B (passive) with restricted bit timing • Fully integrated clock oscillator (no crystal required) • 16 configurable digital or analog I/O port pins The P82C150 provides a configurable event capture facility supporting automatic transmission caused by a change on the port input pins. • Each of the port pins individually configurable via CAN-bus: port direction, port mode and event capture facilities for inputs (event driven or polling) The clock oscillator requires no external components, thus, the cost of the CAN link is reduced significantly. • Up to sixteen digital inputs; automatic transmission of a CAN message on a change on inputs individually selectable The P82C150 is a very cost-effective way to increase the I/O capability of a microcontroller based CAN node as well as to reduce the amount and complexity of wiring. Advanced safety is provided by the CAN protocol. • Up to sixteen 3-state outputs • Up to two quasi-analog outputs with 10-bit accuracy • 10-bit analog-to-digital converter with up to six multiplexed analog input channels (for accuracy see Section 11.6) Applications: • Body electronics and instrumentation in automotive applications • Two general purpose comparators • Sensor/actuator interface in automotive and general industrial applications • Bit rate from 20 kbit/s up to 125 kbit/s using internal oscillator • Extension of I/O capabilities of microcontroller based CAN nodes. • Automatic bit rate detection and calibration • Up to sixteen P82C150 nodes for one CAN-bus system • Four identifier bits programmable • SLIO functions controlled by a single intelligent node (‘host’) • Sleep-mode with wake-up via CAN-bus • Differential CAN-bus input comparator and CAN-bus output driver • Supply voltage: 5 V ±4% • Operating temperature: two ranges −40 to +85 °C and −40 to +125 °C. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER P82C150 AFT P82C150 AHT 1996 Jun 19 NAME DESCRIPTION SO28 plastic small outline package; 28 leads; body width 7.5 mm 3 TEMPERATURE RANGE (°C) VERSION SOT136-1 −40 to +85 −40 to +125 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 4 P82C150 BLOCK DIAGRAM handbook, full pagewidth +5 V AVDD +5 V VDD 18 8 22 19 REF RST 23 16 I/O port pins 17 bus mode RXO 21 CAN-bus RX1 P16 OSCILLATOR clock AND CALIBRATOR input comparator 9 to 16 P8 to P15 PORT LOGIC REFERENCE VOLTAGE 1/2 AV DD BIT STREAM PROCESSOR bus mode TRANSMIT/ RECEIVE LOGIC 5, 6, 7 P5 to P7 1, 2, 3 P2 to P4 27, 28 P0/CLK, P1 I/O REGISTERS + TX1 26 ERROR MANAGEMENT LOGIC CAN-bus TX0 25 20 AVSS P82C150 24 XMOD 4 VSS Fig.1 Block diagram. 1996 Jun 19 IDENTIFIER LATCH 4 MHA064 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 5 P82C150 FUNCTIONAL DIAGRAM VDD AVDD handbook, full pagewidth P16 RX0 ADC feedback output CAN-bus inputs RX1 P15 reference voltage output REF P14 P13 TX1 analog-to-digital comparator input multiplexed analogto-digital signal analog input P12 CAN-bus outputs comparator inputs P11 TX0 P10 P82C150 DPM1 output P9 P8 P7 16-bit digital I/O analog inputs, analog switches P6 RST (reset) P5 P4 DPM2 output P3 P2 P1 XMOD identifier programming P0/CLK VSS AVSS Fig.2 Functional diagram. 1996 Jun 19 5 MHA066 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 6 6.1 P82C150 PINNING INFORMATION Pinning handbook, halfpage P2 1 28 P1 P3 2 27 P0/CLK P4 3 26 TX1 SS 4 25 TX0 P5 5 24 XMOD P6 6 23 RST P7 7 V 22 RX1 P82C150 21 RX0 VDD 8 P8 20 AVSS 9 19 REF P9 10 P10 11 18 AV DD P11 12 17 P16 P12 13 16 P15 15 P14 P13 14 MHA065 Fig.3 Pin configuration. 1996 Jun 19 6 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 6.2 P82C150 Pin description Table 1 Pin description for P82C150; SO28; see note 1 SYMBOL PIN DESCRIPTION P2 1 I/O Ports P2 to P3; Identifier programming input. P3 2 P4 3 I/O Port 4; DPM2 output. VSS 4 Ground, digital part (0 V; logic circuits and CAN-bus driver). P5 5 I/O Ports P5 to P6; analog input. P6 6 P7 7 I/O Port 7; analog input or analog-to-digital comparator 1 output. VDD 8 Power supply, digital part (+5 V; logic circuits and CAN-bus driver). P8 9 I/O Port 8; analog input or comparator 3 output. P9 10 I/O Port 9; analog input or comparator 2 output. P10 11 I/O Port 10; comparator 3 inverting input or DPM1 output. P11 12 I/O Port 11; comparator 3 non-inverting input. P12 13 I/O Port 12; comparator 2 inverting input. P13 14 I/O Port 13; comparator 2 non-inverting input. P14 15 I/O Port 14; multiplexed analog signal. P15 16 I/O Port 15; analog-to-digital comparator input. P16 17 Feedback output of analog-to-digital converter. AVDD 18 Power supply, analog part (+5 V; CAN input, oscillator and reference). REF 19 Reference voltage output (1⁄2 × AVDD). AVSS 20 Ground, analog part (0 V; CAN input, oscillator, reference). RX0 21 CAN-bus input. RX1 22 RST 23 External reset input (active-HIGH) for internal oscillator mode; pulled to +5 V for external oscillator mode (see Section 11.3). XMOD 24 Connected to GND for internal oscillator mode; external reset input (active-LOW) for external oscillator mode (see Section 11.3). TX0 25 Open-drain CAN-bus output: dominant = LOW; recessive = floating. TX1 26 Open-drain CAN-bus output: dominant = HIGH; recessive or at bus mode 2 floating. P0/CLK 27 I/O Port P0, Identifier programming input in internal oscillator mode; clock input in external oscillator mode (see Section 11.3). P1 28 I/O Port P1; identifier programming input. Note 1. In this documentation the port pins are referred to by their symbols, not by their pin number. For example P15 means I/O Port 15 at pin 16. 1996 Jun 19 7 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 7 Analog-to-digital converted digital results are obtained by reading the Analog-to-Digital Conversion (ADC) Register. Analog functions of each port pin are individually controlled by the Analog Configuration Register. FUNCTIONAL DESCRIPTION 7.1 I/O functions The P82C150 provides 16 port pins (P15 to P0) which are individually configurable via CAN-bus. Besides the digital I/O functions some of these port pins provide analog I/O functions. 7.1.1 P82C150 Writing the I/O registers is done serially via CAN-bus by Data Frames. The first data byte contains the register address, and the second and third data bytes represent the register contents. If a read only register is addressed, the contents of the second and third data bytes are ignored. DIGITAL INPUT FUNCTIONS Input levels HIGH and LOW on the port pins (P15 to P0) can be read in two ways by the host node: It is recommended to set unused port pins to HIGH (100 kΩ resistor to VDD). • Polling: a Remote Frame is sent to the P82C150 to be answered by a Data Frame containing the Data Input Register contents. • Event capture: in case of edge-triggered mode, the P82C150 sends the same Data Frame caused by the event of a rising and/or falling edge on the corresponding port pins (see Table 3). 7.1.2 handbook, halfpage DIGITAL OUTPUT FUNCTIONS DIx Px The Data Output Register is set via a CAN message. Its content is only output when the corresponding bits of the Output Enable Register are set to logic 1s. 7.1.3 DOx ANALOG INPUT/OUTPUT FUNCTIONS P82C150 • Up to six multiplexed analog input signals for analog-to-digital conversion or general purpose 3-state buffer OEx MHA068 • Up to two quasi-analog output channels (DPM; Distributed Pulse Modulation) • Two input comparators, for example for window comparator applications Fig.4 I/O port pins. • A separate analog-to-digital input comparator with feedback output. 1996 Jun 19 8 13 1996 Jun 19 DI14 DI13 PE14 PE13 NE14 NE13 PE12 DO14 DO13 DO12 NE12 OE14 OE13 OE12 OC3 OC2 9 DP8 DP7 DQ8 DQ7 DQ6 DP6 OC1 DQ5 DP5 0 OE11 DO11 NE11 PE11 DI11 11 DQ4 DP4 M3 OE10 DO10 NE10 PE10 DI10 10 AD9 AD8 AD7 AD6 AD5 AD4 ADDRESS 8: ANALOG-TO-DIGITAL CONVERSION (ADC) DQ9 ADDRESS 7: DPM2 DP9 ADDRESS 6: DPM1 ADC ADDRESS 5: ANALOG CONFIGURATION OE15 ADDRESS 4: OUTPUT ENABLE DO15 ADDRESS 3: DATA OUTPUT NE15 12 DI12 ADDRESS 2: NEGATIVE EDGE PE15 ADDRESS 1: POSITIVE EDGE DI15 ADDRESS 0: DATA INPUT 14 I/O register map AD3 DQ3 DP3 M2 OE9 DO9 NE9 PE9 DI9 9 AD2 DQ2 DP2 M1 OE8 DO8 NE8 PE8 DI8 8 AD1 DQ1 DP1 SW3 OE7 DO7 NE7 PE7 DI7 7 AD0 DQ0 DP0 SW2 OE6 DO6 NE6 PE6 DI6 6 0 0 0 SW1 OE5 DO5 NE5 PE5 DI5 5 0 0 0 0 OE4 DO4 NE4 PE4 DI4 4 0 0 0 0 OE3 DO3 NE3 PE3 DI3 3 0 0 0 0 OE2 DO2 NE2 PE2 DI2 2 0 0 0 0 OE1 DO1 NE1 PE1 DI1 1 0 0 0 0 OE0 DO0 NE0 PE0 DI0 0 (LSB) 7.2 15 (MSB) Table 2 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions P82C150 I/O registers Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 7.2.1 7.2.3 DATA INPUT REGISTER (ADDRESS 0) This read only register contains the states of port pins P15 to P0 which are transmitted on request, or automatically by change of one of the input levels, provided that the respective input is configured to event capture mode (see Table 3). When an edge is detected the port state is loaded into the transmit buffer after the Control Field of the triggered message is sent. Therefore a delay for input settling is provided. If between edge detection and transmission of the data input register another input signal change at the input port occurs, the corresponding data input register bit is overwritten by the current input port value. Additionally the register content is sent automatically after wake-up or bus mode change, once the bit time has been calibrated (part of the ‘sign-on’ message). NEGATIVE EDGE REGISTER (ADDRESS 2) This write only register contains configuration information per port pin for the event capture facility. The corresponding NE-bit (see Table 3) has to be set to logic 1 to enable capturing of the falling edge. The combination of PE and NE functions is possible. 7.2.4 DATA OUTPUT REGISTER (ADDRESS 3) This write only register contains the output data for the port pins. The output drivers are bitwise enabled by OE (see Section 7.2.5). New data for the output port register are processed and written to the output ports directly after the corresponding CAN message to the P82C150 is successfully checked and becomes valid. 7.2.5 7.2.2 P82C150 POSITIVE EDGE REGISTER (ADDRESS 1) OUTPUT ENABLE REGISTER (ADDRESS 4) This write only register controls the output drivers of the port pins. The corresponding Output Enable Register bit has to be set to logic 1 to enable an output driver. If set to logic 0, the corresponding output driver is disabled (floating; see Fig.7). This write only register contains configuration information per port pin for the event capture facility. The corresponding PE-bit (see Table 3) has to be set to logic 1 to enable capturing of the rising edge. Table 3 Programming of the I/O registers to event capture on edge or to digital output X = don’ t care; n = 0 to 15. REGISTER CONTENTS OF PARTICULAR PORT PIN FUNCTION POSITIVE EDGE (BITS PEn) NEGATIVE EDGE (BITS NEn) OUTPUT ENABLE (BITS OEn) X X 1 X X X Rising 1 0 X Falling 0 1 X Rising and Falling 1 1 X Digital output Digital input Polling Event capture on edge 1996 Jun 19 10 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 7.2.6 ANALOG CONFIGURATION REGISTER (ADDRESS 5) 7.2.7 This read/write register contains the bits ADC, OC3 to OC1, M3 to M1 and SW3 to SW1 (see Fig.7). • OC3 to OC1 bits (comparator output data; read only bits). The bits OC3 to OC1 represent the logical output level of the analog comparators at input port pins P10, P11, P12, P13 and P15. The P82C150 sends back the logical output value of these comparators after having received a Data Frame (see Section 7.3.3) addressing the Analog Configuration Register. The comparator outputs can be monitored at the output port pins P8, P9 and P7. 7.2.8 7.2.9 Analog switch selection by SW3, SW2, SW1. SW1 SWITCH STATE 0 0 0 no switch closed (S0); note 1 0 0 1 S1 closed 0 1 0 S2 closed 0 1 1 S3 closed 1 0 0 S4 closed 1 0 1 S5 closed 1 1 0 S6 closed 1 1 1 reserved Note 1. Evidently if P14 is driven, it may not be connected to any other driven pin via the internal analog switches (avoid short-circuit!). 1996 Jun 19 ANALOG-TO- DIGITAL CONVERSION (ADC) REGISTER (ADDRESS 8) This read only register contains the result of the analog-to-digital converted level of that I/O pin which was selected by the SW bits. The conversion is started by ADC-bit set to logic 1 (see Section 7.2.6), or by transmitting a Data Frame addressing the ADC Register. • SW3 to SW1 (analog switch control bits; write only bits). One of the analog switches S1 to S6 can be closed by setting the switch bits to the corresponding value (see Fig.7 and Table 4). SW2 DPM2 REGISTER (ADDRESS 7) This write only register contains data for a quasi-analog output signal on port pin P4. The function of the DPM2 corresponds to the definition of DPM1. • M3 to M1 bits (multiplexer control bits; write only bits). The logical value of the comparators is monitored on port pins P8, P9 and P7 (see Fig.7) by setting M3 to M1 to logic 1, provided that these pins are configured as outputs (OE = 1). Additionally the register content is sent automatically when the corresponding port bits in the Positive Edge Register and/or Negative Edge Register and the corresponding bits in the Output Enable Register are set. SW3 DPM1 REGISTER (ADDRESS 6) This write only register contains data for a quasi-analog output signal on port pin P10, which is generated by Distributed Pulse Modulation (DPM; see Fig.9). The Output Enable bit must be set for this functions (OE10 = 1). The DPM1 output signal is inverted by setting DO10 = 1. The number of output pulses during a DPM period is given by the DPM1 Register value. These pulses have 4 × tCLK length and are distributed over the DPM period. An analog voltage is provided after smoothing the output signal by an external RC combination. • ADC bit (analog-to-digital conversion start bit; write only bit). The P82C150 starts an analog-to-digital conversion cycle at ADC = 1 ended with the transmission of a message containing the result. After that, the ADC bit is reset automatically. Table 4 P82C150 11 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions ok, full pagewidth P16 17 P15 16 P82C150 R2 + ADC REGISTER − C1 R1 1/2 V DD 1/4fCLK 15 P14 OC1 M1 DO7 S0 OE7 P7 7 S1 P6 6 S2 5 S3 9 S4 10 S5 14 S6 P5 P8 P9 P13 SW3 to SW1 P82C150 OE8 M3 DO8 M2 DO9 OE9 + P12 13 OC2 − OE10 =1 P11 P10 12 11 + DPM1 DO10 OC3 − OE4 P4 3 =1 DPM2 DO4 MHA067 Fig.5 Analog configuration of I/O port pins; R1, R2 and C1 are used to implement the analog-to-digital converter. 1996 Jun 19 12 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions P82C150 handbook, full pagewidth H DPM = 0 L H DPM = 1 L 4 t CLK H DPM = 2 L H DPM = 3 L H DPM = 512 L H DPM = 513 L H DPM = 1023 L t DPM = 1024 x 4 t CLK MHA081 Distributed Pulse Modulation (DPM) is a special pulse count modulation. Fig.6 DPM output pulses at DO10(4) = 0; output pulses are inverted at DO10(4) = 1. 1996 Jun 19 13 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 7.3 host node to verify that the addressed register has correctly been written in case of writeable registers, and to read the contents in case of readable registers. CAN functions The P82C150 meets the CAN protocol specification version 2.0 A and B (passive) with restricted bit timing because of the on-chip RC-oscillator and the automatic bit rate detection. 7.3.1 CAN IDENTIFIER Data and Remote Frames to be processed by the P82C150 are of Standard Format with 11 Identifier bits ID.10 to ID.0. Frames with extended Identifier (CAN specification version 2.0 B) are ignored. In a system with P82C150 nodes there must be at least one conventional crystal-driven CAN controller (host node) which is compatible to the CAN specification V1.2 or later to control P82C150 nodes. Host nodes compatible to CAN specification V1.1 can also be used provided that the P82C150 nodes are powered by a high-accuracy power supply or they are in external oscillator mode (refer to Section 11.3). The way of identifier programming is based on two facts: • Each P82C150 operates with only two Identifiers distinguished by the LSB (see Tables 5, 6 and 7). The identifier with the higher priority is used for Data Frame reception. An extra Identifier is used for calibration purposes. Each time a P82C150 node receives a Data Frame, it initiates the transmission of a Data Frame containing four bits status information, the register address (previously received) and the current contents of the addressed register (exception: see Section 7.3.3.1). This enables the Table 5 P82C150 • There can be maximum sixteen P82C150 circuits in one network. Message types and format FRAME TRANSMISSION BY 82C150 RECEPTION AT 82C150 Data Frame yes (DLC = 3; DIR = 1) yes (DLC = 3; DIR = 0; calibration message with DLC = 2 to 8 allowed, see Section 7.3.10) Remote Frame no yes (DLC = 3; DIR = 1) Error Frame yes yes Overload Frame yes (only as a response) yes Note 1. DLC = Data Length Code; DIR = LSB of Identifier (see Section 7.3.1). Table 6 Standard Format Identifier bits ID.10 to ID.0 1 = recessive; 0 = dominant IDENTIFIER ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 ID.4 ID.3 ID.2 ID.1 ID.0 0 1 P3 1 0 P2 P1 P0 1 0 DIR Table 7 RTR Description of the Standard Format Identifier bits BIT ID.8 SYMBOL P3 ID.5 to ID.3 P2 to P0 ID.0 1996 Jun 19 DESCRIPTION Programmable identifier bits read from Port pins P3 to P0 during reset. The input levels on P3 to P0, for example set by resistors to VSS or to VDD, are latched in the Identifier latch with the falling edge of the RST input signal. They represent the variable part of the Identifier, while the remaining bits are fixed (mask-programmed), P3 to P0 can be used as I/O ports after reset. DIR DIR = 1 for transmission of Data Frames to the host. It must be set to a logic 1 in Remote Frames and to a logic 0 in Data Frames received from the host. RTR Remote Transmission Request bit. 14 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 7.3.2 2. ADC Register: On receiving a Data Frame addressing the ADC Register, the P82C150 starts an analog-to-digital conversion cycle. It automatically returns the result of the conversion (ADC Register) by transmitting a respective Data Frame after finishing the analog-to-digital conversion cycle. TRANSMISSION OF DATA FRAMES Data Frames transmitted by the P82C150 contain three data bytes (see Fig.7). The first data byte contains the status information and the register address A3 to A0 (see Tables 8 and 9), the other two data bytes contain the content of the addressed I/O Register. 3. At normal operation, the calibration messages are confirmed by returning a dominant bit in the acknowledge slot. There is no particular confirmation message returned by the P82C150. Only after entering the calibrated state (start-up), a Data Frame (‘sign-on’ message) containing the Data Input Register contents is transmitted indicating to the host node, that the P82C150 is now ready for transmission. After each successful message transmission, the P82C150 delays the transmission of a possibly further pending message for three bit times. The reason is to give other CAN controllers - with a lower identifier priority - the possibility to transmit a message in case of faulty contact at one of the edge-triggered port pins. 7.3.3 RECEPTION OF DATA FRAMES AND REMOTE FRAMES 7.3.3.2 Received Data Frames have the same format as transmitted ones, only the DIR-bit (ID.0) in the Arbitration Field is different. The status bits RSTD, EW, BM1 and BM0 are ignored during reception. Exceptions to the rule 1. Analog Configuration Register: If a P82C150 receives a Data Frame addressing the Analog Configuration Register and the ADC bit is set to logic 1, it will respond with two messages. The first message returns the contents of the Analog Configuration Register. The control instructions are executed (e.g. next analog input channel selected), and an analog-to-digital conversion cycle is started after a set-up time. After finishing the analog-to-digital conversion cycle, the second message is transmitted containing the result (ADC Register). 1996 Jun 19 Remote Frame Received Remote Frames must have the Data Length Code DLC = 3 (Remote Frames with DLC ≠ 3 are ignored). It is answered by a Data Frame containing the contents of the Data Input Register. The P82C150 confirms each reception of a Data Frame by transmitting a Data Frame containing the (new) contents of the addressed I/O Register. 7.3.3.1 P82C150 15 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions Table 8 P82C150 Data Frame Byte 1 STATUS RSTD Table 9 EW REGISTER ADDRESS BM1 BM0 A3 A2 A1 A0 Description of Data Frame Byte 1 bits SYMBOL DESCRIPTION Status RSTD It is logic 1 in the first message (‘sign-on’ message) after the successful detection of the bit rate (bit time calibrated). EW Logic 1, if the error warning limit (32) is reached. In the “sign-on” message EW is always logic 1. The EW status bit is set when the Receive Error Counter or the Transmit Error Counter have exceeded the Error Warning Limit of 32, also temporarily, since the last successful transmission of a message. BM1 Bus mode status bits. BM0 Register address A3 to A0 Register address bits. handbook, full pagewidth ARBITRATION FIELD SOF Identifier ID10 0 0 1 P3 1 0 ID0 P2 P1 P0 1 0 CONTROL FIELD reserved 0 BYTE 1 Data Length Code 0 0 0 DIR RTR 1 P82C150 status 1 RSTD EW register address BM1 BM0 A3 A2 A1 BYTE 2 BYTE 3 I/O Register data(15 to 8) X X X X X A0 X I/O Register data(7 to 0) X X X X X X X X X X MHA071 SOF: Start Of Frame. RTR: Remote Transmission Request. P3 to P0: equals programmed identifier bits. Fig.7 P82C150 Data Frame. 1996 Jun 19 16 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 7.3.4 P82C150 After reset the P82C150 changes directly into bus mode 3 (Sleep Mode). During Sleep Mode, the internal RC oscillator is stopped, and all the output drivers are disabled (I/O Register contents cleared). A P82C150 in Sleep Mode can be woken up via CAN-bus lines (dominant level on RX0 or RX1) or by a reset condition. CAN-BUS MODES The P82C150 can pass through four CAN-bus modes under certain conditions (see Fig.8). In the bus modes 0 to 2 (see Table 10) the P82C150 is operating with different input comparator configurations. Bus mode 3 is the power reduced Sleep Mode. The bus modes support: • Communication on two balanced wires (differential system) columns DIFFERENTIAL MODE Inputs: RX0, RX1 Outputs: TX0, TX1 • Communication on one wire in a two-wire differential system • Sleep Mode with wake-up via either a dominant signal on RX0 or RX1 input '0' Condition 2 Condition 1 • Connection of a second transmission medium (redundancy) SLEEP MODE ONE-WIRE RX1 MODE Inputs: RX0, RX1 Outputs: no Input: RX1 Outputs: TX0, TX1 '3' '1' end of RESET There are two possibilities for condition 1 to switch to the next mode (see Fig.8): • Overflow of the bit counter when 8192 is reached since the last calibration message • Overflow of the Transmit Error Counter (>255; bus-off limit reached). Condition 1 Condition 1 ONE-WIRE RX0 MODE When the bus mode changes, all I/O Registers are cleared and outputs become floating (OE bits cleared). That means the I/O ports return to a fail-safe state whenever the P82C150 looses connection to its host controller. This is a kind of network watchdog function. The status bits are set to the following values after a bus mode change: Input: RX0 Output: TX0 '2' MHA070 Condition 1: bit counter overflow (>8191) or Transmit Error Counter overflow (>255). Condition 2: dominant bit detected on RX0 and RX1. • RSTD = 1 • EW = 0 Fig.8 CAN-bus modes and switch-over conditions. • BMnew = BMold + 1. The programmed Identifier bits remain unchanged. Table 10 Can-bus modes BITS RECEPTION LEVEL TRANSMISSION BUS MODE BM1 BM0 RECESSIVE DOMINANT TX1 TX0 0 = Differential 0 0 RX0 > RX1 RX0 < RX1 enabled enabled 1 = One-wire RX1 0 1 RX1 < REF RX1 > REF enabled enabled 2 = One-wire RX0 1 0 RX0 > REF RX0 < REF disabled enabled 3 = Sleep 1 1 RX0 > REF and RX1 < REF RX0 < REF or RX1 > REF disabled disabled Note 1. Output TX1 is disabled in bus mode 2 to tolerate short-circuit between the CAN-bus wires CAN_H and CAN_L. 1996 Jun 19 17 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 7.3.5 P82C150 that bit timing which is provided by the crystal driven host (calibration message). BIT TIMING The Nominal Bit Time of the P82C150 is subdivided into 10 Time Quanta. The Synchronization Time Segment (SYNC_SEG) and the Propagation Time Segment (PROP_SEG) are each one Time Quantum long. The Phase Buffer Segment 1 (PHASE_SEG1) and the Phase Buffer Segment 2 (PHASE_SEG2) are each four Time Quanta long. The Resynchronization Jump Width (SJW) is four Time Quanta long. The usable bus length at a given bit rate is reduced in comparison to other CAN controllers with programmable bit timing because the Propagation Time Segment is fixed to 1⁄10 length of the Nominal Bit Time. The bit segmentation of the crystal driven host should be programmed like the fixed bit segmentation of the P82C150, e.g. one bit time segment is 1⁄10 length of the Nominal Bit Time (refer also to Table 15 for bit time programming). The sample point is located at the end of the Phase Buffer Segment 1. The Nominal Bit Time is internally adjusted to Table 11 Bit time subdivision 1 BIT TIME BT1 BT2 BT3 BT4 SYNC_SEG PROP_SEG 7.3.6 BT5 BT6 BT8 PHASE_SEG1 BT9 BT10 PHASE_SEG2 The recessive state and the dominant state are not equivalent and may not be mixed-up. CAN-BUS TRANSCEIVER The transceiver of the P82C150 consists of the configurable input comparator and of complementary open-drain driver outputs. The reference voltage REF is an additional output. 7.3.6.1 BT7 The input comparator is configurable depending on the four CAN-bus modes (see Table 10), supporting battery-powered applications (Sleep Mode) and tolerance against bus wiring failures. CAN-bus input comparator (RX0, RX1) 7.3.6.2 The input comparator monitors the transient voltage on RX1 and RX0. CAN-bus output drivers (TX0, TX1) The output driver function is shown in Table 12. The output driver TX1 is disabled in bus mode 2 to tolerate a short-circuit between the CAN-bus lines in a two-wire differential CAN physical layer. The result of the input comparator is logic 1 if the voltage levels of the CAN-bus lines are regarded as recessive, and logic 0 if they are regarded as dominant. Table 12 CAN-bus driver output function DOMINANT CAN OUTPUT RECESSIVE MODES 0 AND 1 MODE 2 RESET STATE, BUS-OFF AND SLEEP MODE (MODE 3) TX0 floating LOW LOW floating TX1 floating HIGH floating floating 1996 Jun 19 18 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 7.3.7 From this time on, the bit time is calibrated and fine-tuned by calibration messages with a special Identifier transmitted by the crystal-controlled host. TRANSMIT AND RECEIVE LOGIC The transmit and receive logic stores the destuffed bit stream which was received or is about to be transmitted. The incoming Identifier is compared with that of the P82C150. The content of the message is transferred to the port logic in case of matching. Only P82C150 nodes being calibrated by calibration messages can transmit messages. The first message is transmitted directly after entering the calibrated state (‘sign-on’ message). Since the P82C150 is not able to transmit as long as the bit time is not calibrated, it cannot wake-up other CAN nodes via the bus line. Hence to keep the network alive, the calibration message must be transmitted regularly by a crystal-controlled (host) node with a maximum repetition period of 8192 bit (bit length measured by the 82C150). It is recommended to select a repetition period between 3800 and maximum 8000 bit times. At transmission, the message about to be sent is put together: the Identifier, the status information, the register address and the content of the addressed register from the port logic. 7.3.8 BIT STREAM PROCESSOR AND ERROR MANAGEMENT LOGIC The Bit Stream Processor (BSP) is a sequencer to control the data stream between the transmit/receive logic (parallel data) and the on-chip CAN transceiver (serial data). Reception/transmission, bit stuffing/destuffing, arbitration and error detection, according to CAN protocol specification version 2.0 A and B (passive), are performed. Further, automatic re-transmission of corrupted messages is handled by means of continuously comparing the output bit stream with the input bit stream. Moreover, the Bit Stream Processor provides control information to calibrate the internal bit time. 7.3.10 CALIBRATION MESSAGE The calibration message has to meet the following requirements • Transmitted by a crystal-controlled node (host node) • Identifier: 000 1010 1010 (1 = recessive; 0 = dominant) • RTR bit: 0 • Allowed control field: DLC = 2 to 8 • The first recessive to dominant transition after the control field must be followed by another recessive to dominant transition in a distance of exactly 32 bit (stuff bits included). The Error Management Logic is responsible for the complete CAN-inherent error management. 7.3.9 P82C150 OSCILLATOR AND CALIBRATION Example of a suitable calibration message (there are others using different data bytes; see Table 13): The P82C150 contains an on-chip RC-oscillator. The bit time is automatically calibrated by messages being received via CAN-bus. During start-up (after wake-up or reset) any message is used to calibrate the bit time until the calibration is sufficient to receive messages correctly. • Data length code: 0010 • 1st data byte: 1010 1010 (AAH) • 2nd data byte: 0000 0100 (04H). Table 13 Example of a suitable calibration message The two important 1/0 transitions are marked by underlines; see note 1. SOF ARBITRATION FIELD CONTROL FIELD DATA BYTE 1 DATA BYTE 2 CRC FIELD 0 000 1010 1010 0 000I010 1010 1010 0000I 0100 000I0 1011 1000 00I0 Note 1. I = stuff bit (recessive); the total length is 67 bit from start-of-frame to end-of-intermission. 1996 Jun 19 19 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 7.4 After rough calibration the P82C150 can receive any valid CAN message correctly and executes respective commands without giving an acknowledge. With another valid CAN message and additionally with one valid calibration message the P82C150 is fully calibrated and sends its ‘sign-on’ message. As long as the P82C150 is fully calibrated the P82C150 acts as an active CAN node. Initialization 7.4.1 IDENTIFIER PROGRAMMING Most of the P82C150 identifier bits are fixed. Four bits are programmable via port pins P3 to P0. All output drivers are disabled at reset, also P3 to P0. Thus the outputs are floating unless the input level is defined by external components to define identifier bits. They are latched at the end of reset, and P3 to P0 can be used as port pins. It is not allowed, according to the CAN protocol specification, that multiple bus nodes transmit the same identifier bit combination. Therefore a P82C150 must have one of the 16 possible identifier bit combinations, one that is not yet occupied. 7.4.2 The P82C150 treats any CAN message (including the calibration message) as a valid message, when these messages are terminated by an error passive frame because of a missing acknowledge. This situation may occur whenever a host node works together with P82C150’s and the host node doesn’t receive an acknowledge as long as the P82C150’s are not fully calibrated. RESET FUNCTION 7.4.3.1 RST = HIGH disables all output drivers P16 to P0, TX0 and TX1. All I/O Registers are automatically cleared and set to logic 0. The bit time is set greater than 50 µs. The sign-on message returns the contents of the Data Input Register, and can be recognized by the host mode by checking the RSTD status bit: • Sign-on message RSTD = 1 • Other Data Frames RSTD = 0 Table 14 Situation after RESET Note that in the sign-on message the EW bit is logic 1. Nevertheless the P82C150 status with the error counters are set to logic 0. IDENTIFIER BITS RSTD = 1 ID.8 equals P3 EW = 1 ID.5 equals P2 BM1 = 0 ID.4 equals P1 BM0 = 0 ID.3 equals P0 7.4.3 BIT TIME CALIBRATION The P82C150 must receive at least three messages to calibrate its bit time after reset or change of bus mode. The first message is used to detect the bit time length (rough calibration) between two consecutive falling edges at the output of the CAN input comparator. Therefore the bit stream should contain a sequence of ‘1010’. 1996 Jun 19 Sign-on message This special Data Frame is transmitted once by the P82C150 after entering the calibrated state. It indicates to the host node that the P82C150 is ready for transmission. If a particular clock period is necessary, e.g. for a dedicated DPM output frequency, this can be achieved by feeding an external clock signal into P0. RST and TEST must be permanently HIGH for this special mode. A reset is then performed as usual (RST = HIGH; TEST = LOW). STATUS BITS P82C150 20 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 7.5 P82C150 P82C150 operation after RESET or change of bus mode Figure 9 illustrates the calibration procedure of the P82C150 after Power-on-reset or after a bus mode change. andbook, full pagewidth end of Power-on-reset bus mode change e.g. due to missing reception of a calibration message within 8192 bit times ID bits from P0-P3 latched I/O registers cleared P82C150 receives 1st message (any message) P82C150 is roughly calibrated and has started bus-off recovery sequence (counting 129 blocks of 11 recessive bits) P82C150 receives 2nd message (any message), acknowledge not required but no active error flag allowed Rough calibration verified P82C150 receives calibration message within 8192 bit times after wake-up or bus mode change P82C150 is fine calibrated and I/O register cleared P82C150 waits until bus-off recovery sequence finished P82C150 is on bus and ready to send after bus-of f sequence finished P82C150 sends 'sign-on' message Communication with host node possible MHA080 Fig.9 SLIO operation flow after reset and bus mode change. 1996 Jun 19 21 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions P82C150 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage on VDD pin −0.5 +6.5 V VI DC input voltage on any pin (RX0, RX1, TX0, TX1 excluded) −0.5 VDD + 0.5 V II RX1 and RX0 input current − ±2 mA IREF reference output current − ±2 mA IO port output current at port enabled (pins P0 to P15) − ±5 mA port output current at analog switch enabled (OE-bits = 0; pins P5 to P9, P13, P14) − 7.5 mA TX0 and TX1 output current − 30 mA POtot total power dissipation (port outputs together) − 200 mW Tamb operating ambient temperature range: −40 +125 °C Tstg storage temperature range −65 +150 °C Ptot total power dissipation − 1 W 1996 Jun 19 22 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions P82C150 9 DC CHARACTERISTICS VDD = 5 V ± 4%; VSS = 0 V; Tamb = −40 to +85 °C and Tamb = −40 to +125 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Supply VDD supply voltage note 1 4.8 5.2 V IDD operating supply current VRST = VDD; all port inputs connected via 1 MΩ to GND − 22 mA IDD(SM) supply current Sleep mode Ports P15, P13 and P11 connected to VDD; Ports P12 and P10 connected to VSS; all other port inputs connected via 1 MΩ to GND 1 mA CAN Input comparators RX0 and RX1 VDIF differential input voltage − mV input voltage hysteresis 0.3AVDD < VI < 0.7AVDD; note 2 ±100 VHYST 8 60 mV II input current 0.45 V < VI < VDD − 0.45 V − ±400 nA − 0.1 V 1.0 V − V CAN output driver TX0 and TX1; port pins P0 to P16 unloaded VOLT VOHT TX0 output voltage LOW; note 3 IOLT = 1.5 mA IOLT = 10 mA TX1 output voltage HIGH; note 4 IOHT = −1.5 mA VDD − 0.1 IOHT = −10 mA VDD − 1.0 IO < ±75 µA 0.5AVDD − 0.25 0.5AVDD + 0.25 V − 0.2VDD V 0.7VDD − V 0.5 − V ±10 µA V Reference voltage REF VREF reference output voltage Control inputs RST, XMOD and digital port inputs P0/CLK, P1 to P15 VIL input voltage LOW VIH input voltage HIGH VHYST input voltage hysteresis note 2 IIL1 input leakage current 0.45 V < VI < VDD − 0.45 V Digital port outputs P0/CLK, P1 to P16; OE bits set VOL output voltage LOW IOL = 4mA (sink) − 1.0 V VOH output voltage HIGH IOH = −4mA (source) VDD − 1.0 − V ±20 − mV OC2 comparator P12, P13 and OC3 comparator P10, P11 VDIF1 1996 Jun 19 differential input voltage 1.5 V < VI < (AVDD − 1.5 V); note 2 23 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions SYMBOL PARAMETER P82C150 CONDITIONS MIN. MAX. UNIT OC1 comparator input P15 Vi sw input switch-over voltage lower threshold 1.5 V < VI < (AVDD − 1.5 V); note 2 0.5VDD − 0.02 V − 0.5VDD + 0.02 V ILI2 input leakage current 0.45 V < VI < VDD − 0.45 V − ±400 nA CIA analog input capacitance note 2 − 20 pF between P5 to P9, P13 and P14; note 2 20 200 Ω upper threshold Analog switches; ION = ±4 mA RON On resistance Notes to the DC characteristics: 1. Alteration of VDD between two calibration messages should not exceed 0.2 V to avoid failures during CAN message transfer. If CAN devices according to CAN specification V1.0 or V1.1 (like the 82C200 V0 or V1) are in the same network with the 82C150, then this alteration of VDD should be limited to 0.1V for the 82C150. 2. These values are characterized but not 100% production tested. 3. The TX0 output pin is an open drain pull-down driver (no pull-up driver included). 4. The TX1 output pin is an open drain pull-up driver (no pull-down driver included). 10 AC CHARACTERISTICS VDD = 5 V ± 4%; VSS = 0 V; CL = 100 pF (output pins); Tamb = −40 to +85 °C and Tamb = −40 to +125 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. fCLK_INT system clock frequency on-chip internal oscillator 4 MAX. UNIT 10 MHz tbit bit time on CAN-bus note 1 8 50 µs tRST1 min. RST pulse width after power on note 2 150 − ms tRST2 min. RST pulse width during operation note 2 1 − µs thold ID hold time after end of reset note 2 100 − ns td total signal delay of CAN input comparator and CAN output driver 0.3AVDD < VI < 0.7AVDD; note 2 − 100 ns trep max. time without recalibration message − 8000 bit Analog-to-digital comparator input P15 tcyc analog-to-digital conversion cycle time 0.4 1.1 ms tinit initialization time of analog-to-digital conversion 0.4 2.1 ms 1 µs 1.1 ms OC2 comparator P12, P13 and OC3 comparator P10, P11 tresp VDIF1 = ±100 mV; note 2 response time DPM1 and DPM2 outputs tDPM repetition time of DPM cycle 0.4 Notes 1. Other bit time values are possible with the external oscillator mode (refer to Chapter 11.3). 2. These values are characterized but not 100% production tested. 1996 Jun 19 24 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions P82C150 11 APPLICATION INFORMATION 11.1.1 11.1 • The total in/out delay of external transceiver circuit is less than 180 ns (e.g. PCA82C250 CAN transceiver; see Fig.20). Maximum bus length The bit timing parameters refer to using a P8xCE598 or P8xC592 microcontroller with on-chip CAN interface as a host node (see Fig.20). ASSUMPTIONS • The propagation delay on the transmission medium is 5.0 ns/m. Table 15 Maximum bus length for CAN-bus systems with P82C150 nodes. BIT RATE (kbit/s) tprop(1) (µs) INDICATION FOR MAXIMUM BUS LENGTH (m) BIT TIMING (P8xCE598/P8xC592) fCLK (MHz) BTR0(2) BTR1(2) 125 0.8 25 15 C5H 34H 100 1 45 16 C7H 34H 50 2 145 16 CFH 34H 20 5 445 16 E7H 34H Notes 1. tprop is the maximum propagation delay between two CAN-bus nodes (delays of on- and off-chip transceiver circuits included). 2. BTR0 and BTR1 (hex values) are particular configuration registers referring to bit timing. 11.2 Start up sequence The following start-up sequence, illustrated by Figures 10 and 11, shows a simple example how P82C150 nodes can be controlled from a host node. This application example works with different system configurations: handbook, halfpage Power-on Initialization of host node's CAN controller • One conventional crystal-controlled CAN node and one or more P82C150 nodes. Wait until all P82C150 nodes are assumed to have finished Power-on-reset • More than one conventional crystal-controlled CAN node and one or more P82C150 nodes. Start-up bit time calibration procedure (1) Periodic calibration (transmit calibration message with a repetition period of maximum 8000 bit times) MHA077 (1) See Fig.11. Fig.10 General start-up procedure for CAN-bus systems with P82C150 nodes. 1996 Jun 19 25 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions P82C150 handbook, full pagewidth Load calibration message into transmit buf fer j := 18 if 'Transmit Status' = 0(1) else then Set bit 'Transmission Request' (CMR.0) in Command Register '0' if 'Transmit Status' = 1(1) else then Set bit 'Abort Transmission' (CMR.1) in Command Register j : = j −1 else if j = 0 then Wait for reception of sign-on message from P82C150 nodes from now onwards transmit calibration message periodically with a recommended repetition period between 3800 and 8000 bit times MHA079 (1) Bit SR.5 in Status Register. Fig.11 P82C150 start-up bit time calibration procedure for host node (P8xC592, P8xCE598 or P82C200). 1996 Jun 19 26 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 11.3 P82C150 External oscillator mode In this mode the P82C150 operates with an external clock instead with the on-chip RC-oscillator. Figure 14 shows the application with an external clock. +5 V P82C150 In this mode the P82C150 can achieve bit rates below 20 kbit/s and above 125 kbit/s. The DPM pulse width is 4 × tCLK of the external clock. The corresponding CAN identifier bit at Port P0 is set to a logic 0. Therefore only eight P82C150 based CAN nodes operate within the same network in external oscillator mode. 11.3.1 digital input P0 to P15 MHA072 NOTE Fig.12 Example for digital input application. The external oscillator mode is not the normal operation mode. 11.4 Using digital I/O port functions Figures 12 and 13, show the principle application for digital input and output. 11.5 P82C150 digital output Using DPM P0 to P15 The simplest way to generate an analog voltage using the P82C150 is to apply an external low pass filter at one of the DPM (Distributed Pulse Modulation) outputs. The simplest implementation concept is a RC-filter of the first order (refer to Fig.15). Regarding the selection of the time constant (edge frequency) of this filter, a trade-off between minimizing of the ripple voltage for maximum accuracy and minimum of the settling time has to be considered. MHA073 Fig.13 Example for digital output application. V V handbook, halfpage clock reset +5 V P82C150 t P0/CLK analog output XMOD t DPM1(2) P10(P4) P82C150 RST MHA074 MHA078 If the output is loaded by a resistive load, this will decrease the accuracy due to the voltage drop across the series resistor. In these cases a low value for the series resistor should be chosen. The repetition time of one DPM cycle can be derived from: 4096 t CYC = ------------f OSC Fig.14 P82C150 in external oscillator mode. 1996 Jun 19 Fig.15 Example for DPM application. 27 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions 11.6 Using ADC P82C150 11.7 The application in Fig.16 can be used for analog-to-digital conversion for only one analog input signal. The evaluation of ADC were done with the values R1 = R2 = 100 kΩ and C = 3.3 nF; under these conditions the ADC may reach an accuracy of 7 to 8 bit (depends on application). The external components should be connected close to the port pins P15 and P16 with short wiring to avoid disturbances at the analog input port pin P15. Using analog input port functions Figure 18 shows the wide range of analog input applications: • Comparison of two analog input signals. • Comparison of one analog input signal against a fixed threshold. • Window comparator including monitoring the comparator outputs at the port pins P8 and P9; additional automatically generated messages, when the corresponding port bits in the Negative Edge and/or Positive Edge register are set. Using the on-chip multiplex function the P82C150 provides up to six input port pins to convert analog input signals to digital values (see Fig.17). • Local control two-step system. The period for one ADC cycle is identical to the length of one DPM cycle. handbook, halfpage P15 P82C150 handbook, halfpage P16 P16 one analog input signal for A/D conversion R1 feedback analog signal P82C150 R2 P14 V P15 P5 C t SW3 to SW1 V MHA076 P6 t MHA075 Fig.17 Two multiplexed analog input signals switched for analog-to-digital conversion (maximum 6 signals; see Fig.5). Fig.16 ADC implementation. 1996 Jun 19 28 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions P82C150 V dbook, full pagewidth P82C150 comparison between two analog input signals P11 (P13) t OC3 (OC2) V P10 (P12) t V P82C150 message transmission when analog input signal exceeds threshold voltage P11 (P13) t +5 V threshold P10 (P12) DO8 (DO9) M3 (M2) comparator OE8 (OE9) P8 (P9) DI8 (DI9) output enabled and edge-triggered mode (PE and/or NE set) +5 V message transmission when analog input signal exceeds upper respectively lower threshold voltage (window comparator) P82C150 upper threshold P11 DO8 P10 M3 V comparators t sensor signal OE8 P13 lower threshold DO9 P12 M2 V OE9 P9 t V P8 DI9 output enabled and edge-triggered mode (PE and/or NE set) output enabled and edge-triggered mode (PE and/or NE set) DI8 t V local two-step control system t +5 V P82C150 sensor signal P11 (P13) threshold P10 (P12) DO8 (DO9) M3 (M2) comparator V OE8 (OE9) t to actuator P8 (P9) DI8 (DI9) output enabled MHA082 Fig.18 Examples of comparator applications. 1996 Jun 19 29 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions handbook, full pagewidth V bat on/off control V bat linear control with status feedback LOAD angle measurement LOAD D S D P82C150 S KM110BH/21-90 BUK105-50S BUK101-50GS P I F VS I +5 V Vo GND +5 V 10 kΩ +5 V V DD RST RX0 Pw Pz Py Px (DPM) (digital out) (digital in) PV (digital out) (analog in) V SS P82C150 REF TX0 RX1 TX1 MHA083 Fig.19 Examples of TOPFET applications with P82C150. 1996 Jun 19 30 1996 Jun 19 31 CANH Vref CRX1 CANL PCA82C250 RxD CRX0 P8xC592 / P8xCE598 CAN-CONTROLLER Rs Rext = 0 Px,y CAN BUS LINE +5 V 560 Ω TxD TX0 Vref TX1 CANL +5 V 124 Ω 6.8 kΩ MHA069 Rs RX1 digital sensor 3.6 kΩ P82C150 PCA82C250 RxD RX0 TOPFET CANH (1) analog Fig.20 P82C150 system application using CAN transceiver PCA82C250 (ISO/DIS 11898 standard). (1) TOPFET = temperature and Overload-Protected Field-Effect-Transistor 124 Ω TxD XTAL2 CTX0 XTAL1 TOPFET lamp 11.8 M motor CAN Serial Linked I/O device (SLIO) with digital and analog port functions handbook, full pagewidth Philips Semiconductors Preliminary specification P82C150 CAN-bus system applications Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions P82C150 12 PACKAGE OUTLINE SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 e bp 0 detail X w M 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.050 0.42 0.39 0.055 0.043 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013AE 1996 Jun 19 EIAJ EUROPEAN PROJECTION ISSUE DATE 91-08-13 95-01-24 32 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. 13 SOLDERING 13.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these cases reflow soldering is often used. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 13.2 13.4 Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. 1996 Jun 19 Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at between 270 and 320 °C Reflow soldering Reflow soldering techniques are suitable for all SO packages. 13.3 P82C150 33 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions P82C150 14 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Jun 19 34 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions NOTES 1996 Jun 19 35 P82C150 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 805 4455, Fax. +61 2 805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 648 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 83749, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com/ps/ (1) ADDRESS CONTENT SOURCE June 20, 1996 © Philips Electronics N.V. 1996 SCA49 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 617021/1200/02/pp36 Date of release: 1996 Jun 19 Document order number: 9397 750 00918