Revised September 2003 74LVX4245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs General Description Features The LVX4245 is a dual-supply, 8-bit translating transceiver that is designed to interface between a 5V bus and a 3V bus in a mixed 3V/5V supply environment. The Transmit/ Receive (T/R) input determines the direction of data flow. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B Ports by placing them in a high impedance condition. The A Port interfaces with the 5V bus; the B Port interfaces with the 3V bus. ■ Bidirectional interface between 5V and 3V buses ■ Control inputs compatible with TTL level ■ 5V data flow at A Port and 3V data flow at B Port ■ Outputs source/sink 24 mA at 5V bus; 12 mA at 3V bus ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Implements patented EMI reduction circuitry ■ Functionally compatible with the 74 series 245 The LVX4245 is suitable for mixed voltage applications such as laptop computers using 3.3V CPU’s and 5V LCD displays. Ordering Code: Order Number Package Number Package Description 74LVX4245WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX4245QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 74LVX4245MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Connection Diagram Description OE Output Enable Input T/R Transmit/Receive Input A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs Truth Table Inputs OE Outputs T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial © 2003 Fairchild Semiconductor Corporation DS011540 www.fairchildsemi.com 74LVX4245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs January 1993 74LVX4245 Logic Diagram www.fairchildsemi.com 2 Supply Voltage (VCCA, VCCB) DC Input Voltage (VI) @ OE, T/R Recommended Operating Conditions (Note 2) −0.5V to +7.0V −0.5V to VCCA + 0.5V Supply Voltage DC Input/Output Voltage (VI/O ) @ An −0.5V to VCCA + 0.5V @Bn −0.5V to VCCB + 0.5V 4.5V to 5.5V VCCB 2.7V to 3.6V Input Voltage (VI) @ OE, T/R DC Input Diode Current (IIN) 0V to VCCA Input/Output Voltage (VI/O) @ OE, T/R DC Output Diode Current (IOK) ±20 mA @ An ±50 mA @ Bn DC Output Source or Sink Current 0V to VCCA 0V to VCCB −40°C to +85°C Free Air Operating Temperature (TA) ±50 mA (IO) Minimum Input Edge Rate (∆t/∆V) DC VCC or Ground Current 8 ns/V VIN from 30% to 70% of VCC ±50 mA per Output Pin (ICC or IGND) and Max Current @ ICCA ±200 mA @ ICCB ±100 mA VCC @ 3.0V, 4.5V, 5.5V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Storage Temperature Range −65°C to +150°C (TSTG) VCCA DC Latch-Up Source or Note 2: Unused inputs must he held HIGH or LOW. They may not float. ±300 mA Sink Current DC Electrical Characteristics Symbol VIHA VIHB Parameter VCCA VCCB (V) (V) TA +25°C Typ TA = −40°C to +85°C Guaranteed Limits Units Conditions Minimum An, T/R, 5.5 3.3 2.0 2.0 VOUT ≤ 0.1V or HIGH Level OE 4.5 3.3 2.0 2.0 ≥ VCC − 0.1V Input Voltage Bn 5.0 3.6 2.0 2.0 5.0 2.7 2.0 2.0 V Maximum An, T/R, 5.5 3.3 0.8 0.8 VOUT ≤ 0.1V or LOW Level OE 4.5 3.3 0.8 0.8 ≥ VCC −0.1V VILB Input Voltage Bn 5.0 2.7 0.8 0.8 5.0 3.6 0.8 0.8 VOHA Minimum HIGH Level 4.5 3.0 4.5 4.4 4.4 Output Voltage 4.5 3.0 4.25 3.86 3.76 4.5 3.0 2.99 2.9 2.9 4.5 3.0 2.8 2.4 2.4 4.5 2.7 2.5 2.4 2.4 4.5 3.0 0.002 0.1 0.1 VILA VOHB VOLA Maximum LOW Level Output Voltage VOLB IIN V IOUT = −100 µA V IOH = −24 mA IOUT = −100 µA V IOH = −12 mA V IOUT =100 µA IOL = −8 mA 4.5 3.0 0.18 0.36 0.44 IOL = 24 mA 4.5 3.0 0.002 0.1 0.1 IOUT = 100 µA 4.5 3.0 0.1 0.31 0.4 4.5 2.7 0.1 0.31 0.4 5.5 3.6 ±0.1 ±1.0 µA 5.5 3.6 ±0.5 ±5.0 µA IOL = 12 mA V IOL = 8 mA VI = VCCA, GND Maximum Input Leakage Current @ OE, T/R IOZA VI = VIL, VIH Maximum 3-STATE Output Leakage OE = VCCA VO = VCCA, GND @ An IOZB VI = VIL, VIH Maximum 3-STATE Output Leakage 5.5 ±0.5 3.6 ±5.0 µA OE = VCCA VO = VCCB, GND @ Bn ∆ICC Maximum ICCT/Input 5.5 3.6 5.5 3.6 1.0 1.35 1.5 mA VI = VCCA − 2.1V 0.35 0.5 mA VI = VCCB − 0.6V @ An, T/R, OE Input @ Bn 3 www.fairchildsemi.com 74LVX4245 Absolute Maximum Ratings(Note 1) 74LVX4245 DC Electrical Characteristics Symbol ICCA Parameter (Continued) VCCA VCCB (V) (V) 5.5 3.6 TA +25°C TA = −40°C to +85°C Typ Units An = VCCA or GND Quiescent VCCA Supply Current Conditions Guaranteed Limits 8 80 µA Bn = VCCB or GND, OE = GND T/R = GND ICCB An = VCCA or GND Quiescent VCCB Supply Current 5.5 3.6 5 50 VOLPA Quiet Output Maximum 5.0 3.3 1.5 VOLPB Dynamic VOL 5.0 3.3 0.8 VOLVA Quiet Output Minimum 5.0 3.3 −1.2 VOLVB Dynamic VOL 5.0 3.3 −0.8 µA Bn = VCCB or GND, OE = GND T/R = VCCA VIHDA Minimum HIGH Level 5.0 3.3 2.0 VIHDB Dynamic Input Voltage 5.0 3.3 2.0 VILDA Maximum LOW Level 5.0 3.3 0.8 VILDB Dynamic Input Voltage 5.0 3.3 0.8 V V V V (Note 4)(Note 5) (Note 4)(Note 5) (Note 4)(Note 6) (Note 4)(Note 6) Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: Worst case package. Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND. Note 6: Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to VCC level. Input-under-test switching: VCC level to threshold (VIHD), OV to threshold (VILD), f = 1 MHz. AC Electrical Characteristics TA = +25°C Symbol Parameters TA = −40°C to +85°C TA = −40°C to +85°C CL = 50 pF CL = 50 pF CL = 50 pF VCCA = 5V (Note 7) VCCA = 5V (Note 7) VCCA = 5V (Note 7) VCCB = 3.3V (Note 8) VCCB = 3.3V (Note 8) VCCB = 2.7V Min Typ Max Min Max Min Max tPHL Propagation Delay 1.0 5.1 8.5 1.0 9.0 1.0 10.0 tPLH A to B 1.0 5.3 8.5 1.0 9.0 1.0 10.0 tPHL Propagation Delay 1.0 5.4 8.5 1.0 9.0 1.0 10.0 tPLH B to A 1.0 5.5 8.5 1.0 9.0 1.0 10.0 tPZL Output Enable Time 1.0 6.5 10.0 1.0 10.5 1.0 11.5 tPZH OE to B 1.0 6.7 10.0 1.0 10.5 1.0 11.5 tPZL Output Enable Time 1.0 5.2 9.0 1.0 9.5 1.0 10.0 tPZH OE to A 1.0 5.8 9.0 1.0 9.5 1.0 10.0 tPHZ Output Disable Time 1.0 6.0 9.5 1.0 10.0 1.0 10.0 tPLZ OE to B 1.0 3.3 6.5 1.0 7.0 1.0 7.5 tPHZ Output Disable Time 1.0 3.9 7.0 1.0 7.5 1.0 7.5 tPLZ OE to A 1.0 2.9 6.5 1.0 7.0 1.0 7.5 tOSHL Output to Output tOSLH Skew (Note 9) 1.0 1.5 1.5 1.5 Units ns ns ns ns ns ns ns Data to Output Note 7: Voltage Range 5.0V is 5.0V ± 0.5V. Note 8: Voltage Range 3.3V is 3.3V ± 0.3V. Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. www.fairchildsemi.com 4 74LVX4245 Capacitance Symbol CIN CI/O Typ Units Conditions Input Capacitance Parameter 4.5 pF VCC = Open Input/Output 15 pF VCCA = 5.0V VCCB = 3.3V Capacitance CPD Power Dissipation B→A 55 pF VCCA = 5.0V Capacitance (Note 10) A→B 40 pF VCCB = 3.3V Note 10: CPD is measured at 10 MHz 8-Bit Dual Supply Translating Transceiver The LVX4245 is a dual supply device capable of bidirectional signal translation. This level shifting ability provides an efficient interface between low voltage CPU local bus with memory and a standard bus defined by 5V I/O levels. The device control inputs can be controlled by either the low voltage CPU and core logic or a bus arbitrator with 5V I/O levels. Manufactured on a sub-micron CMOS process, the LVX4245 is ideal for mixed voltage applications such as notebook computers using 3.3V CPU’s and 5V peripheral devices. Power Up Considerations pins are configured as inputs. With VCCA receiving power first, the A I/O Port should be configured as inputs to help guard against bus contention and oscillations. To insure the system does not experience unnecessary ICC current draw, bus contention, or oscillations during power up, the following guidelines should be adhered to (refer to Table 1): • A side data inputs should be driven to a valid logic level. This will prevent excessive current draw. • Power up the control side of the device first. This is the VCCA. The above steps will ensure that no bus contention or oscillations, and therefore no excessive current draw occurs during the power up cycling of these devices. These steps will help prevent possible damage to the translator devices and potential damage to other system components. • OE should ramp with or ahead of VCCA. This will help guard against bus contention. • The Transmit/Receive control pin (T/R) should ramp with or ahead of VCCA, this will ensure that the A Port data TABLE 1. Low Voltage Translator Power Up Sequencing Table Device Type 74LVX4245 VCCA VCCB T/R OE A Side I/O 5V 3V ramp ramp logic (power up 1st) (power up 2nd) with VCCA with VCCA 0V or VCCA B Side I/O Floatable Pin Allowed outputs No Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual Supply CMOS Translating Transceivers. 5 www.fairchildsemi.com 74LVX4245 Applications: Mixed Mode Dual Supply Interface Solution either a 3V system or a 5V system without any further work to re-layout the board. LVX4245 is designed to solve 3V/5V interfacing issues when CMOS devices cannot tolerate I/O levels above their applied VCC. If an I/O pin of 3V ICs is driven by 5V ICs, the P-Channel transistor in 3V ICs will conduct causing current flow from I/O bus to the 3V power supply. The resulting high current flow can cause destruction of 3V ICs through latchup effects. To prevent this problem, a current limiting resistor is used typically under direct connection of 3V ICs and 5V ICs, but it causes speed degradation. In a better solution, the LVX4245 configures two different output levels to handle the dual supply interface issues. The “A” port is a dedicated 5V port to interface 5V ICs. The “B” port is a dedicated port to interface 3V ICs. Figure 2 shows how LVX4245 fits into a system with 3V subsystem and 5V subsystem. This device is also configured as an 8-bit 245 transceiver, giving the designer 3-STATE capabilities and the ability to select either bidirectional or unidirectional modes. Since the center 20 pins are also pin compatible to 74 series 245, as shown in Figure 1, the designer could use this device in FIGURE 1. LVX4245 Pin Arrangement is Compatible to 20-Pin 74 Series 245 FIGURE 2. LVX4245 Fits into a System with 3V Subsystem and 5V Subsystem www.fairchildsemi.com 6 74LVX4245 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA24 7 www.fairchildsemi.com 74LVX4245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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