74HC193-Q100; 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter Rev. 1 — 12 July 2013 Product data sheet 1. General description The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device counts up. If the CPD clock is pulsed while CPU is held HIGH, the device counts down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR). It may also be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU causes TCU to go LOW. TCU remains LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output goes LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs duplicate the clock waveforms and can be used as the clock input signals to the next higher-order circuit in a multistage counter. Multistage counters are not fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information on the parallel data inputs (D0 to D3), is loaded into the counter. This information appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input disables the parallel load gates. It overrides both clock inputs and sets all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock is interpreted as a legitimate signal and it is counted. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Input levels: For 74HC193-Q100: CMOS level For 74HCT193-Q100: TTL level Synchronous reversible 4-bit binary counting Asynchronous parallel load Asynchronous reset Expandable without external logic Complies with JEDEC standard no. 7A 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC193D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC193DB-Q100 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC193PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT193D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT193DB-Q100 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HCT193PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 4. Functional diagram 15 11 5 4 14 1 D0 PL 10 D1 9 D2 D3 TCU CPU COUNTER TCD CPD MR 3 Q1 2 Fig 1. Functional diagram Product data sheet 13 FLIP-FLOPS Q0 74HC_HCT139_Q100 12 Q2 6 CPU 5 CPD 4 001aag405 D0 D1 D2 D3 11 15 1 10 9 14 3 2 6 7 MR Q0 Q1 Q2 Q3 Q3 7 PL 12 TCU 13 TCD 001aag409 Fig 2. Logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 2 of 29 NXP Semiconductors 74HC193-Q100; 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter 11 5 4 14 15 1 10 9 C3 2+ G1 1− G2 R CTR4 3 2 6 7 3D 2CT = 0 1CT = 15 13 12 001aag410 Fig 3. IEC logic symbol 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 3 of 29 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx D1 D2 NXP Semiconductors 74HC_HCT139_Q100 Product data sheet D0 D3 PL CPU TCU T FF1 SD Q FF2 T FF3 Q Q T Q FF4 Q RD RD SD Q Q RD RD TCD CPD MR Q0 4 of 29 © NXP B.V. 2013. All rights reserved. Fig 4. Logic diagram Q1 Q2 Q3 001aag412 74HC193-Q100; 74HCT193-Q100 T SD Q Presettable synchronous 4-bit binary up/down counter Rev. 1 — 12 July 2013 All information provided in this document is subject to legal disclaimers. SD 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 5. Pinning information 5.1 Pinning +&4 +&74 ' 9&& 4 ' 4 05 &3' 7&' &38 7&8 4 3/ 4 ' *1' +&4 +&74 ' ' 4 9&& ' 4 05 &3' 7&' &38 7&8 4 3/ 4 ' *1' ' DDD DDD Fig 5. Pin configuration SO16 Fig 6. Pin configuration TSSOP16 and SSOP16 5.2 Pin description Table 2. Pin description Symbol Pin Description D0 15 data input 0 D1 1 data input 1 D2 10 data input 2 D3 9 data input 3 Q0 3 flip-flop output 0 Q1 2 flip-flop output 1 Q2 6 flip-flop output 2 Q3 7 flip-flop output 3 CPD 4 count down clock input[1] CPU 5 count up clock input[1] GND 8 ground (0 V) PL 11 asynchronous parallel load input (active LOW) TCU 12 terminal count up (carry) output (active LOW) TCD 13 terminal count down (borrow) output (active LOW) MR 14 asynchronous master reset input (active HIGH) VCC 16 supply voltage [1] LOW-to-HIGH, edge triggered. 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 5 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 6. Functional description Table 3. Function table[1] Operating mode Inputs Outputs MR PL CPU CPD D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD Reset (clear) H X X X X X L L L L H H X X H X X X X L L L L H H Parallel load L L X L L L L L L L L L H L L L X H L L L L L L L L H H L L L X H H H H H H H H L H H H H L X L L L H X H H H H H H H Count up L H H X X X X count up H[2] H Count down L H H X X X X count down H H[3] [1] H = HIGH voltage level L = LOW voltage level X = don’t care = LOW-to-HIGH clock transition. [2] TCU = CPU at terminal count up (HHHH) [3] TCD = CPD at terminal count down (LLLL). 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 6 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter MR(1) PL D0 D1 D2 D3 CPU(2) CPD(2) Q0 Q1 Q2 Q3 TCU TCD 0 13 CLEAR PRESET 14 15 0 COUNT UP 1 2 1 0 15 14 COUNT DOWN 13 001aag411 (1) Clear overrides load, data and count inputs. (2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input (CPU) must be HIGH. Sequence Clear (reset outputs to zero); load (preset) to binary thirteen; count up to fourteen, fifteen, terminal count up, zero, one and two; count down to one, zero, terminal count down, fifteen, fourteen and thirteen. Fig 7. Typical clear, load and count sequence 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 7 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7.0 V - 20 mA - 20 mA - 25 mA IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current VO = 0.5 V to VCC + 0.5 V ICC supply current - 50 mA IGND ground current - 50 mA Tstg storage temperature 65 +150 C - 500 mW [2] total power dissipation Ptot [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit 74HC193-Q100 VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V 74HCT193-Q100 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature 40 +25 +125 C t/V input transition rise and fall rate - 1.67 139 74HC_HCT139_Q100 Product data sheet VCC = 4.5 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 ns/V © NXP B.V. 2013. All rights reserved. 8 of 29 NXP Semiconductors 74HC193-Q100; 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter 9. Static characteristics Table 6. Static characteristics type 74HC193-Q100 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V VI = VIH or VIL - - - IO = 20 A; VCC = 2.0 V 1.9 2.0 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - V IO = 20 A; VCC = 2.0 V - 0 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 A Ci input capacitance - 3.5 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 - - V IO = 20 A; VCC = 4.5 V 4.4 - - V IO = 20 A; VCC = 6.0 V 5.9 - - V IO = 4.0 mA; VCC = 4.5 V 3.84 - - V IO = 5.2 mA; VCC = 6.0 V 5.34 - - V Tamb = 40 C to +85 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 74HC_HCT139_Q100 Product data sheet VI = VIH or VIL All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 9 of 29 NXP Semiconductors 74HC193-Q100; 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter Table 6. Static characteristics type 74HC193-Q100 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V - - 0.1 V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 20 A; VCC = 6.0 V - - 0.1 V IO = 4.0 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.0 V - - 0.33 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 80 A Tamb = 40 C to +125 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 - - V IO = 20 A; VCC = 4.5 V 4.4 - - V IO = 20 A; VCC = 6.0 V 5.9 - - V IO = 4.0 mA; VCC = 4.5 V 3.7 - - V IO = 5.2 mA; VCC = 6.0 V 5.2 - - V IO = 20 A; VCC = 2.0 V - - 0.1 V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 20 A; VCC = 6.0 V - - 0.1 V VI = VIH or VIL VI = VIH or VIL IO = 4.0 mA; VCC = 4.5 V - - 0.4 V IO = 5.2 mA; VCC = 6.0 V - - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 160 A 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 10 of 29 NXP Semiconductors 74HC193-Q100; 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter Table 7. Static characteristics type 74HCT193-Q100 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - V IO = 4.0 mA 3.98 4.32 - V IO = 20 A - 0 0.1 V IO = 4.0 mA VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V - 0.15 0.26 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 A ICC additional supply current per input pin; VI = VCC 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn - 35 126 A pins CPU, CPD - 140 504 A pin PL - 65 234 A pin MR - 105 378 A - 3.5 - pF Ci input capacitance Tamb = 40 C to +85 C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V VOL LOW-level output voltage IO = 20 A 4.4 - - V IO = 4.0 mA 3.84 - - V - - 0.1 V VI = VIH or VIL; VCC = 4.5 V IO = 20 A - - 0.33 V II input leakage current VI = VCC or GND; VCC = 5.5 V IO = 4.0 mA - - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 80 A ICC additional supply current per input pin; VI = VCC 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn - - 157.5 A pins CPU, CPD - - 630 A pin PL - - 292.5 A pin MR - - 472.5 A 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 11 of 29 NXP Semiconductors 74HC193-Q100; 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter Table 7. Static characteristics type 74HCT193-Q100 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 4.5 V to 5.5 V 2.0 - - V - - 0.8 V IO = 20 A 4.4 - - V IO = 4.0 mA 3.7 - - V IO = 20 A - - 0.1 V IO = 4.0 mA - - 0.4 V Tamb = 40 C to +125 C VIH HIGH-level input voltage VIL LOW-level input voltage VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 160 A ICC additional supply current per input pin; VI = VCC 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn - - 171.5 A pins CPU, CPD - - 686 A pin PL - - 318.5 A pin MR - - 514.5 A 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 12 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 10. Dynamic characteristics Table 8. Dynamic characteristics type 74HC193 -Q100 Symbol Parameter 25 C Conditions Min tpd propagation delay CPU, CPD to Qn; see Figure 8 [1] 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max - VCC = 2.0 V - 63 215 - 270 - 325 ns VCC = 4.5 V - 23 43 - 54 - 65 ns VCC = 6.0 V - 18 37 - 46 - 55 ns VCC = 2.0 V - 39 125 - 155 - 190 ns VCC = 4.5 V - 14 25 - 31 - 38 ns VCC = 6.0 V - 11 21 - 26 - 32 ns - 39 125 - 155 - 190 ns VCC = 4.5 V - 14 25 - 31 - 38 ns VCC = 6.0 V - 11 21 - 26 - 32 ns CPU to TCU; see Figure 9 CPD to TCD; see Figure 9 VCC = 2.0 V PL to Qn; see Figure 10 VCC = 2.0 V - 69 220 - 275 - 330 ns VCC = 4.5 V - 25 44 - 55 - 66 ns VCC = 6.0 V - 20 37 - 47 - 56 ns VCC = 2.0 V - 58 200 - 250 - 300 ns VCC = 4.5 V - 21 40 - 50 - 60 ns VCC = 6.0 V - 17 34 43 - 51 ns VCC = 2.0 V - 69 210 - 265 - 315 ns VCC = 4.5 V - 25 42 - 53 - 63 ns VCC = 6.0 V - 20 36 - 45 - 54 ns VCC = 2.0 V - 80 290 - 365 - 435 ns VCC = 4.5 V - 29 58 - 73 - 87 ns VCC = 6.0 V - 23 49 - 62 - 74 ns MR to Qn; see Figure 11 Dn to Qn; see Figure 10 PL to TCU, PL to TCD; see Figure 13 MR to TCU, MR to TCD; see Figure 13 74HC_HCT139_Q100 Product data sheet VCC = 2.0 V - 74 285 - 355 - 430 ns VCC = 4.5 V - 27 57 - 71 - 86 ns VCC = 6.0 V - 22 48 - 60 - 73 ns All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 13 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 8. Dynamic characteristics type 74HC193 …continued-Q100 Symbol Parameter tpd tTHL tTLH tW propagation delay 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max Dn to TCU, Dn to TCD; see Figure 13 VCC = 2.0 V - 80 290 - 365 - 435 ns VCC = 4.5 V - 29 58 - 73 - 87 ns VCC = 6.0 V - 23 49 - 62 - 74 ns HIGH to LOW see Figure 11 output transition VCC = 2.0 V time VCC = 4.5 V - 19 75 - 95 - 110 ns - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns LOW to HIGH see Figure 11 output transition VCC = 2.0 V time VCC = 4.5 V - 19 75 - 95 - 110 ns - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 100 22 - 125 - 150 - ns VCC = 4.5 V 20 8 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns VCC = 2.0 V 100 25 - 125 - 150 - ns VCC = 4.5 V 20 9 - 25 - 30 - ns VCC = 6.0 V 17 7 - 21 - 26 - ns pulse width CPU, CPD (HIGH or LOW); see Figure 8 MR (HIGH); see Figure 11 PL (LOW); see Figure 10 trec recovery time VCC = 2.0 V 100 19 - 125 - 150 - ns VCC = 4.5 V 20 7 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns VCC = 2.0 V 50 8 - 65 - 75 - ns VCC = 4.5 V 10 3 - 13 - 15 - ns VCC = 6.0 V 9 2 - 11 - 13 - ns VCC = 2.0 V 50 0 - 65 - 75 - ns VCC = 4.5 V 10 0 - 13 - 15 - ns VCC = 6.0 V 9 0 - 11 - 13 - ns PL to CPU, CPD; see Figure 10 MR to CPU, CPD; see Figure 11 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 14 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 8. Dynamic characteristics type 74HC193 …continued-Q100 Symbol Parameter tsu th set-up time hold time 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 0 14 - 0 - 0 - ns VCC = 4.5 V 0 5 - 0 - 0 - ns VCC = 6.0 V 0 4 - 0 0 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 8 6 - 17 - 20 - ns VCC = 2.0 V 4.0 13.5 - 3.2 - 2.6 - MHz VCC = 4.5 V 20 41 - 16 - 13 - MHz 24 49 - 19 - 15 - MHz - 24 - - - - - pF Dn to PL; see Figure 12; note: CPU = CPD = HIGH Dn to PL; see Figure 12 CPU to CPD, CPD to CPU; see Figure 14 fmax maximum frequency CPU, CPD; see Figure 8 VCC = 6.0 V CPD power dissipation capacitance VI = GND to VCC; VCC = 5 V; fi = 1 MHz [2] [1] tpd is the same as tPHL and tPLH. [2] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 15 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 9. Dynamic characteristics type 74HCT193 -Q100 Symbol Parameter tpd 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 23 43 - 54 - 65 ns - 15 27 - 34 - 41 ns - 15 27 - 34 - 41 ns - 26 46 - 58 - 69 ns - 22 40 - 50 - 60 ns - 27 46 - 58 - 69 ns - 31 55 - 69 - 83 ns - 29 55 - 69 - 83 ns VCC = 4.5 V - 32 58 - 73 - 87 ns HIGH to LOW see Figure 11 output transition VCC = 4.5 V time - 7 15 - 19 - 22 ns LOW to HIGH see Figure 11 output transition VCC = 4.5 V time - 7 15 - 19 - 22 ns 25 11 - 31 - 38 - ns 20 7 - 25 - 30 - ns 20 8 - 25 - 30 - ns propagation delay CPU, CPD to Qn; see Figure 8 VCC = 4.5 V [1] CPU to TCU; see Figure 9 VCC = 4.5 V CPD to TCD; see Figure 9 VCC = 4.5 V PL to Qn; see Figure 10 VCC = 4.5 V MR to Qn; see Figure 11 VCC = 4.5 V Dn to Qn; see Figure 10 VCC = 4.5 V PL to TCU, PL to TCD; see Figure 13 VCC = 4.5 V MR to TCU, MR to TCD; see Figure 13 VCC = 4.5 V Dn to TCU, Dn to TCD; see Figure 13 tTHL tTLH tW pulse width CPU, CPD (HIGH or LOW); see Figure 8 VCC = 4.5 V MR (HIGH); see Figure 11 VCC = 4.5 V PL (LOW); see Figure 10 VCC = 4.5 V 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 16 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 9. Dynamic characteristics type 74HCT193 …continued-Q100 Symbol Parameter trec recovery time 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 10 2 - 13 - 15 - ns 10 0 - 13 - 15 - ns 16 8 - 20 - 24 - ns 0 6 - 0 - 0 - ns 16 7 - 20 - 24 - ns 20 43 - 16 - 13 - MHz - 26 - - - - - pF PL to CPU, CPD; see Figure 10 VCC = 4.5 V MR to CPU, CPD; see Figure 11 VCC = 4.5 V tsu set-up time Dn to PL; see Figure 12; note: CPU = CPD = HIGH th hold time Dn to PL; see Figure 12 VCC = 4.5 V VCC = 4.5 V CPU to CPD, CPD to CPU; see Figure 14 VCC = 4.5 V fmax maximum frequency CPU, CPD; see Figure 8 VCC = 4.5 V CPD [1] [2] power dissipation capacitance VI = GND to VCC 1.5 V; VCC = 5 V; fi = 1 MHz [2] tpd is the same as tPHL and tPLH. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 17 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 11. Waveforms 1/fmax VI CPU, CPD input VM GND tW t PHL t PLH VOH VM Qn output 001aag413 VOL Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock pulse frequency VI CPU, CPD input VM GND tPHL tPLH VOH TCU, TCD output VM VOL 001aag414 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. The clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 18 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter VI Dn input VM GND VI PL input VM GND t rec tW VI CPU, CPD input VM GND t PLH t PHL VOH Qn output VM VOL 001aag415 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock input (CPU, CPD) VI MR input VM GND tW t rec VI CPU, CPD input VM GND t PHL VOH Qn output VOL 90 % VM 10 % t THL t TLH 001aag416 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and output transition times 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 19 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter VI VM Dn input GND tsu tsu th th VI VM PL input GND VOH Qn output VOL 001aag417 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 10. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig 12. The data input (Dn) to parallel load input (PL) set-up and hold times VI PL, MR, Dn input VM GND tPLH tPHL VOH TCU, TCD output VM VOL 001aag418 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig 13. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs (TCU, TCD) propagation delays VI CPU or CPD input VM GND th VI CPD or CPU input VM GND 001aag419 Measurement points are given in Table 10. Fig 14. The CPU to CPD or CPD to CPU hold times 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 20 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 10. Measurement points Type Input Output VM VI VM 74HC193-Q100 0.5 VCC GND to VCC 0.5 VCC 74HCT193-Q100 1.3 V GND to 3 V 1.3 V VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch Fig 15. Load circuitry for measuring switching times Table 11. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC193-Q100 VCC 6 ns 15 pF, 50 pF 1 k open 74HCT193-Q100 3V 6 ns 15 pF, 50 pF 1 k open 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 21 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 12. Application information data input D0 D1 D2 D3 D0 D1 D2 D3 up clock CPU TCU CPU TCU down clock CPD IC1 TCD CPD IC2 TCD PL MR PL Q0 Q1 Q2 Q3 carry borrow MR Q0 Q1 Q2 Q3 asynchronous parallel load reset data output 001aag420 Fig 16. Application for cascaded up/down counter with parallel load 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 22 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 17. Package outline SOT109-1 (SO16) 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 23 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 18. Package outline SOT338-1 (SSOP16) 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 24 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 19. Package outline SOT403-1 (TSSOP16) 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 25 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 14. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model MIL Military TTL Transistor-Transistor Logic 15. Revision history Table 13. Revision history Document ID Release date 74HC_HCT193_Q100 v.1 20130712 74HC_HCT139_Q100 Product data sheet Data sheet status Change notice Supersedes Product data sheet - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 26 of 29 74HC193-Q100; 74HCT193-Q100 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT139_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 27 of 29 NXP Semiconductors 74HC193-Q100; 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT139_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2013 © NXP B.V. 2013. All rights reserved. 28 of 29 NXP Semiconductors 74HC193-Q100; 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information. . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 Legal information. . . . . . . . . . . . . . . . . . . . . . . 27 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Contact information. . . . . . . . . . . . . . . . . . . . . 28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 July 2013 Document identifier: 74HC_HCT139_Q100