Data Sheet

74HC4024-Q100
7-stage binary ripple counter
Rev. 1 — 27 November 2013
Product data sheet
1. General description
The 74HC4024-Q100 is a 7-stage binary ripple counter with a clock input (CP), an
overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs
(Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR
clears all counter stages and forces all outputs LOW, independent of the state of CP. Each
counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the
circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Low power dissipation
 Complies with JEDEC standard no. 7A
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Multiple package options
3. Applications
 Frequency dividing circuits
 Time delay circuits
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
4. Ordering information
Table 1.
Ordering information
Type number
Package
74HC4024D-Q100
Temperature range
Name
Description
Version
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
TSSOP14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT402-1
74HC4024PW-Q100 40 C to +125 C
5. Functional diagram
Q6 3
Q5 4
7-STAGE
COUNTER
Q4 5
Q3 6
1
Q2
Q3
2
9
Q1 11
6
Q0 12
5
CT = 0
MR
1
2
Fig 2.
Q
T
Q
FF
2
Q
T
Q
RD
T
T
Q
FF
5
Q
RD
IEC logic symbol
Q
FF
4
Q
RD
Fig 3.
Q
FF
3
3
001aab907
Functional diagram
Q
FF
1
6
001aab908
Logic symbol
T
6
CT
4
CP
001aab906
CP
9
2
3
Q6
12
11
+
4
Q5
Fig 1.
1
5
Q4
MR
0
Q2 9
11
Q1
CP
CTR7
12
Q0
T
Q
RD
Q
FF
6
T
FF
7
Q
RD
Q
RD
RD
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
001aab909
Fig 4.
Logic diagram
74HC4024_Q100
Product data sheet
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Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
2 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
6. Pinning information
6.1 Pinning
+&4
&3
9&&
05
QF
4
4
4
4
4
QF
4
4
*1'
QF
DDD
Fig 5.
Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
CP
1
clock input (HIGH-to-LOW, edge-triggered)
MR
2
master reset input (active HIGH)
Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0
3, 4, 5, 6, 9, 11, 12
parallel output
GND
7
ground (0 V)
n.c.
8, 10, 13
not connected
VCC
14
supply voltage
7. Functional description
Table 3.
Function table[1]
Input
Output
MR
CP
Qn
H
X
L
L

no change

count
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition.
74HC4024_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
3 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
0.5
+7
V
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
-
20
mA
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
-
20
mA
IO
output current
VO = 0.5 V to VCC + 0.5 V
-
25
mA
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
-
500
mW
[1]
Tamb = 40 C to +125 C
total power dissipation
Ptot
[1]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Typ
Max
Unit
2.0
5.0
6.0
V
VI
input voltage
0
-
VCC
V
VO
output voltage
0
-
VCC
V
t/V
input transition rise and fall
rate
VCC = 2.0 V
-
-
625
ns/V
VCC = 4.5 V
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
ns/V
40
-
+125
C
Tamb
ambient temperature
74HC4024_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
4 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
HIGH-level input voltage
VCC = 2.0 V
1.5
1.2
-
V
VCC = 4.5 V
3.15
2.4
-
V
VCC = 6.0 V
4.2
3.2
-
V
VCC = 2.0 V
-
0.8
0.5
V
VCC = 4.5 V
-
2.1
1.35
V
VCC = 6.0 V
-
2.8
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
V
IO = 4 mA; VCC = 4.5 V
3.98
4.32
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
V
Tamb = 25 C
VIH
VIL
VOH
VOL
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
VI = VIH or VIL
VI = VIH or VIL
IO = 4 mA; VCC = 4.5 V
-
0.15
0.26
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
V
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
0.1
A
ICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
-
-
8.0
A
CI
input capacitance
-
3.5
-
pF
VCC = 2.0 V
1.5
-
-
V
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 4 mA; VCC = 4.5 V
3.84
-
-
V
IO = 5.2 mA; VCC = 6.0 V
5.34
-
-
V
Tamb = 40 C to +85 C
VIH
VIL
VOH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
74HC4024_Q100
Product data sheet
VI = VIH or VIL
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Rev. 1 — 27 November 2013
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5 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 4 mA; VCC = 4.5 V
-
-
0.33
V
IO = 5.2 mA; VCC = 6.0 V
-
-
0.33
V
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
-
-
80
A
VCC = 2.0 V
1.5
-
-
V
Tamb = 40 C to +125 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 4 mA; VCC = 4.5 V
3.7
-
-
V
IO = 5.2 mA; VCC = 6.0 V
5.2
-
-
V
IO = 20 A; VCC = 2.0 V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 4 mA; VCC = 4.5 V
-
-
0.4
V
VI = VIH or VIL
VI = VIH or VIL
IO = 5.2 mA; VCC = 6.0 V
-
-
0.4
V
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
-
-
160
A
74HC4024_Q100
Product data sheet
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Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
6 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
11. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
-
47
175
ns
VCC = 4.5 V
-
17
35
ns
VCC = 6.0 V
-
14
30
ns
-
14
-
ns
VCC = 2.0 V
-
25
80
ns
VCC = 4.5 V
-
9
16
ns
VCC = 6.0 V
-
7
14
ns
VCC = 2.0 V
-
63
200
ns
VCC = 4.5 V
-
23
40
ns
-
18
34
ns
VCC = 2.0 V
-
19
75
ns
VCC = 4.5 V
-
7
15
ns
VCC = 6.0 V
-
6
13
ns
VCC = 2.0 V
80
17
-
ns
VCC = 4.5 V
16
6
-
ns
VCC = 6.0 V
14
5
-
ns
VCC = 2.0 V
80
22
-
ns
VCC = 4.5 V
16
8
-
ns
VCC = 6.0 V
14
6
-
ns
VCC = 2.0 V
50
6
-
ns
VCC = 4.5 V
10
2
-
ns
VCC = 6.0 V
9
2
-
ns
VCC = 2.0 V
6.0
27
-
MHz
VCC = 4.5 V
30
82
-
MHz
Tamb = 25 C
tpd
propagation delay
CP to Q0; see Figure 6
[1]
VCC = 5.0 V; CL = 15 pF
Qn to Qn+1; see Figure 6
tPHL
HIGH to LOW
propagation delay
[1]
MR to Q0; see Figure 6
VCC = 6.0 V
tt
tW
transition time
pulse width
see Figure 6
[2]
CP HIGH or LOW; see Figure 6
MR HIGH; see Figure 6
trec
fmax
CPD
recovery time
maximum frequency
power dissipation
capacitance
74HC4024_Q100
Product data sheet
MR to CP; see Figure 6
CP; see Figure 6
VCC = 6.0 V
35
98
-
MHz
VCC = 5.0 V; CL = 15 pF
-
90
-
MHz
-
25
-
pF
VI = GND to VCC
[3]
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Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
7 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +85 C
tpd
propagation delay
CP to Q0; see Figure 6
[1]
VCC = 2.0 V
-
-
220
ns
VCC = 4.5 V
-
-
44
ns
-
-
37
ns
VCC = 6.0 V
Qn to Qn+1; see Figure 6
tPHL
HIGH to LOW
propagation delay
[1]
VCC = 2.0 V
-
-
100
ns
VCC = 4.5 V
-
-
20
ns
VCC = 6.0 V
-
-
17
ns
MR to Q0; see Figure 6
VCC = 2.0 V
-
-
250
ns
VCC = 4.5 V
-
-
50
ns
-
-
43
ns
VCC = 2.0 V
-
-
95
ns
VCC = 4.5 V
-
-
19
ns
VCC = 6.0 V
-
-
16
ns
VCC = 6.0 V
tt
tW
transition time
pulse width
see Figure 6
[2]
CP HIGH or LOW; see Figure 6
VCC = 2.0 V
100
-
-
ns
VCC = 4.5 V
20
-
-
ns
VCC = 6.0 V
17
-
-
ns
MR HIGH; see Figure 6
trec
fmax
recovery time
maximum frequency
74HC4024_Q100
Product data sheet
VCC = 2.0 V
100
-
-
ns
VCC = 4.5 V
20
-
-
ns
VCC = 6.0 V
17
-
-
ns
VCC = 2.0 V
65
-
-
ns
VCC = 4.5 V
13
-
-
ns
VCC = 6.0 V
11
-
-
ns
MR to CP; see Figure 6
CP; see Figure 6
VCC = 2.0 V
4.8
-
-
MHz
VCC = 4.5 V
24
-
-
MHz
VCC = 6.0 V
28
-
-
MHz
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Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
8 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +125 C
tpd
propagation delay
CP to Q0; see Figure 6
[1]
VCC = 2.0 V
-
-
265
ns
VCC = 4.5 V
-
-
53
ns
-
-
45
ns
VCC = 6.0 V
Qn to Qn+1; see Figure 6
tPHL
HIGH to LOW
propagation delay
[1]
VCC = 2.0 V
-
-
120
ns
VCC = 4.5 V
-
-
24
ns
VCC = 6.0 V
-
-
20
ns
MR to Q0; see Figure 6
VCC = 2.0 V
-
-
300
ns
VCC = 4.5 V
-
-
60
ns
-
-
51
ns
VCC = 6.0 V
tt
tW
transition time
pulse width
see Figure 6
[2]
VCC = 2.0 V
-
-
110
ns
VCC = 4.5 V
-
-
22
ns
VCC = 6.0 V
-
-
19
ns
CP HIGH or LOW; see Figure 6
VCC = 2.0 V
120
-
-
ns
VCC = 4.5 V
24
-
-
ns
VCC = 6.0 V
20
-
-
ns
MR HIGH; see Figure 6
trec
recovery time
74HC4024_Q100
Product data sheet
VCC = 2.0 V
120
-
-
ns
VCC = 4.5 V
24
-
-
ns
VCC = 6.0 V
20
-
-
ns
VCC = 2.0 V
75
-
-
ns
VCC = 4.5 V
15
-
-
ns
VCC = 6.0 V
13
-
-
ns
MR to CP; see Figure 6
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Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
9 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7.
Symbol
Parameter
Conditions
fmax
maximum frequency
CP; see Figure 6
[1]
Min
Typ
Max
Unit
VCC = 2.0 V
4.0
-
-
MHz
VCC = 4.5 V
20
-
-
MHz
VCC = 6.0 V
24
-
-
MHz
tpd is the same as tPLH and tPHL.
[2]
tt is the same as tTHL and tTLH.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
12. Waveforms
MR input
VM
tW
1/fmax
trec
VM
CP input
tPHL
Q0 or Qn
output
tPLH
tW
90 %
tPHL
90 %
10 %
VM
10 %
tTLH
tTHL
001aab910
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to
clock (CP) recovery time.
VM = 0.5  VI.
Fig 6.
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum frequency
74HC4024_Q100
Product data sheet
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Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
10 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
9,
QHJDWLYH
SXOVH
W:
90
90
*1'
WI
9,
WI
SRVLWLYH
SXOVH
*1'
WU
WU
90
90
W:
9&&
*
9,
92
'87
57
&/
DDK
Test data is given in Table 8.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 7.
Table 8.
Test circuit for measuring switching times
Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
2.0 V
VCC
6 ns
50 pF
4.5 V
VCC
6 ns
50 pF
6.0 V
VCC
6 ns
50 pF
5.0 V
VCC
6 ns
15 pF
74HC4024_Q100
Product data sheet
Load
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
11 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
13. Package outline
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74HC4024_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
12 of 17
74HC4024-Q100
NXP Semiconductors
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74HC4024_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
13 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
14. Abbreviations
Table 9.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
15. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC4024_Q100 v.1
20131127
Product data sheet
-
-
74HC4024_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
14 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC4024_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
15 of 17
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NXP Semiconductors
7-stage binary ripple counter
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74HC4024_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
16 of 17
74HC4024-Q100
NXP Semiconductors
7-stage binary ripple counter
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 27 November 2013
Document identifier: 74HC4024_Q100