Dual 5 A, 20 V Synchronous Step-Down Regulator with Integrated High-Side MOSFET ADP2325 Data Sheet TYPICAL APPLICATION CIRCUIT RTOP1 RBOT1 COMP1 RC1 FB1 INTVCC CINT MODE SCFG TRK2 TRK1 CBST1 L1 M1 ADP2325 M2 APPLICATIONS L2 VOUT2 BST2 PVIN2 EN2 SS2 COMP2 SW2 CBST2 RC2 RBOT2 VIN CSS2 CIN2 10036-001 CC2 Communications infrastructure Networking and servers Industrial and instrumentation Healthcare and medical Intermediate power rail conversion COUT2 DL2 PGOOD2 ROSC COUT1 PGND GND PGOOD1 SYNC RT VOUT1 SW1 DL1 VDRV CDRV VIN CIN1 CC1 CSS1 FB2 Input voltage: 4.5 V to 20 V ±1% output accuracy Integrated 48 mΩ typical high-side MOSFET Flexible output configuration Dual output: 5 A/5 A Parallel single output: 10 A Programmable switching frequency: 250 kHz to 1.2 MHz External synchronization input with programmable phase shift or internal clock output Selectable PWM or PFM mode operation Adjustable current limit for small inductors External compensation and soft start Startup into precharged output Supported by ADIsimPowerTM design tool SS1 EN1 PVIN1 BST1 FEATURES RTOP2 Figure 1. GENERAL DESCRIPTION The bidirectional synchronization pin can be programmed at a 60°, 90°, or 120° phase shift to provide for a stackable, multiphase power solution. The ADP2325 can be configured to operate in pulse frequency modulation (PFM) mode at a light load for higher efficiency or in forced PWM mode for noise sensitive applications. External compensation and soft start provide design flexibility. The ADP2325 operates over the −40°C to +125°C junction temperature range and is available in a 32-lead LFCSP_WQ package. 100 VOUT = 5.0V VOUT = 3.3V 95 90 85 80 75 70 65 60 55 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT CURRENT (A) 10036-002 The switching frequency can be programmed from 250 kHz to 1.2 MHz, or it can be synchronized to an external clock to minimize interference in multirail applications. The dual PWM channels run 180° out of phase, thereby reducing input current ripple as well as reducing the size of the input capacitor. Independent enable inputs and power-good outputs provide reliable power sequencing. To enhance system reliability, the device includes undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection, and thermal shutdown. EFFICIENCY (%) The ADP2325 is a full featured, dual output, step-down dc-to-dc regulator based on a current mode architecture. The ADP2325 integrates two high-side power MOSFETs and two low-side drivers for the external N-channel MOSFETs. The two pulse-width modulation (PWM) channels can be configured to deliver dual 5 A outputs or a parallel-to-single 10 A output. The regulator operates from input voltages of 4.5 V to 20 V, and the output voltage can be as low as 0.6 V. Figure 2. Efficiency vs. Output Current at VIN = 12 V, fSW = 600 kHz Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. 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ADP2325 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overvoltage Protection .............................................................. 19 Applications ....................................................................................... 1 Undervoltage Lockout ............................................................... 19 Typical Application Circuit ............................................................. 1 Thermal Shutdown .................................................................... 19 General Description ......................................................................... 1 Applications Information .............................................................. 20 Revision History ............................................................................... 2 Input Capacitor Selection .......................................................... 20 Functional Block Diagram .............................................................. 3 Output Voltage Setting .............................................................. 20 Specifications..................................................................................... 4 Voltage Conversion Limitations ............................................... 20 Absolute Maximum Ratings ....................................................... 6 Current-Limit Setting ................................................................ 20 Thermal Resistance ...................................................................... 6 Inductor Selection ...................................................................... 20 ESD Caution .................................................................................. 6 Output Capacitor Selection....................................................... 21 Pin Configuration and Function Descriptions ............................. 7 Low-Side Power Device Selection ............................................ 22 Typical Performance Characteristics ............................................. 9 Programming UVLO Input ...................................................... 22 Theory of Operation ...................................................................... 16 Compensation Components Design ....................................... 22 Control Scheme .......................................................................... 16 Design Example .............................................................................. 24 PWM Mode ................................................................................. 16 Output Voltage Setting .............................................................. 24 PFM Mode ................................................................................... 16 Current-Limit Setting ................................................................ 24 Precision Enable/Shutdown ...................................................... 16 Frequency Setting ....................................................................... 24 Separate Input Voltages ............................................................. 16 Inductor Selection ...................................................................... 24 Internal Regulator (INTVCC) .................................................. 16 Output Capacitor Selection....................................................... 24 Bootstrap Circuitry .................................................................... 17 Low-Side MOSFET Selection ................................................... 25 Low-Side Driver.......................................................................... 17 Compensation Components ..................................................... 25 Oscillator ..................................................................................... 17 Soft Start Time Programming .................................................. 26 Synchronization .......................................................................... 17 Input Capacitor Selection .......................................................... 26 Soft Start ...................................................................................... 17 External Components Recommendations .................................. 27 Peak Current-Limit and Short-Circuit Protection................. 17 Typical Application Circuits ......................................................... 28 Voltage Tracking ......................................................................... 18 Packaging and Ordering Information ......................................... 32 Parallel Operation....................................................................... 18 Outline Dimensions ................................................................... 32 Power Good ................................................................................. 19 Ordering Guide .......................................................................... 32 REVISION HISTORY 2/12—Revision 0: Initial Version Rev. 0 | Page 2 of 32 Data Sheet ADP2325 FUNCTIONAL BLOCK DIAGRAM ADP2325 UVLO PVIN1 1.2V EN1_BUF + ACS1 – EN1 1µA 4µA SLOPE RAMP1 Σ I1MAX + OCP – BOOST REGULATOR HICCUP MODE BST1 COMP1 ISS1 0.6V SS1 NFET1 DRIVER + + AMP1 + CMP1 – – – + TRK1 FB1 SKIP MODE THRESHOLD 0.7V – + OVP SW1 SKIP CMP1 CONTROL LOGIC AND MOSFET DRIVER WITH MODE_BUF ANTICROSS PROTECTION VDRV DRIVER DL1 PGND + CLK1 LOW-SIDE CURRENT SENSE – 0.54V – + + PGOOD1 I1MAX CURRENTLIMIT SELECTION VDRV PVIN1 MODE_BUF MODE EN1_BUF CLK1 SCFG EN2_BUF INTVCC 5V REGULATOR SLOPE RAMP1 OSCILLATOR CLK2 SYNC RT GND SLOPE RAMP2 UVLO 1.2V EN2_BUF PVIN2 + ACS2 – EN2 1µA 4µA SLOPE RAMP2 Σ I2MAX + OCP – BOOST REGULATOR HICCUP MODE BST2 COMP2 NFET2 0.6V SS2 DRIVER + + CMP2 – + + AMP2 TRK2 FB2 – 0.7V – + OVP SKIP CMP2 CONTROL LOGIC AND MOSFET + DRIVER WITH ANTICROSS MODE_BUF PROTECTION – SKIP MODE THRESHOLD SW2 DRIVER LOW-SIDE CURRENT SENSE CLK2 – 0.54V VDRV DL2 – + + PGOOD2 I2MAX Figure 3. Rev. 0 | Page 3 of 32 CURRENTLIMIT SELECTION 10036-003 ISS2 ADP2325 Data Sheet SPECIFICATIONS PVIN1 = PVIN2 = 12 V at TJ = −40°C to +125°C, unless otherwise noted. Table 1. Parameters POWER INPUT (PVINx PINS) Power Input Voltage Range Quiescent Current (PVIN1 + PVIN2) Shutdown Current (PVIN1 + PVIN2) PVINx Undervoltage Lockout Threshold PVINx Rising PVINx Falling FEEDBACK (FBx PINS) FBx Regulation Voltage1 FBx Bias Current ERROR AMPLIFIER (COMPx PINS) Transconductance Error Amplifier Source Current Error Amplifier Sink Current INTERNAL REGULATOR (INTVCC PIN) INTVCC Voltage Dropout Voltage Regulator Current Limit SWITCH NODE (SWx PINS) High-Side On Resistance2 High-Side Peak Current Limit Low-Side Negative Current-Limit Threshold Voltage3 SWx Minimum On Time3 SWx Minimum Off Time3 LOW-SIDE DRIVER (DLx PINS) Rising Time3 Falling Time3 Sourcing Resistor Sinking Resistor OSCILLATOR (RT PIN) PWM Switching Frequency PWM Frequency Range SYNCHRONIZATION (SYNC PIN) SYNC Input Synchronization Range Minimum On Pulse Width Minimum Off Pulse Width High Threshold Low Threshold SYNC Output Frequency on SYNC Pin Positive Pulse Time SOFT START (SSx PINS) SSx Pin Source Current Symbol Test Conditions/Comments VPVIN IQ ISHDN UVLO MODE = GND, no switching EN1 = EN2 = GND Min Typ Max Unit 3 30 20 5 40 V mA μA 4.2 3.7 4.4 V V 0.594 0.6 0.01 0.606 0.1 V μA 370 40 45 500 65 65 630 90 85 μS μA μA 4.75 5 300 100 5.25 V mV mA 4.5 3.5 VFB IFB PVINx = 4.5 V to 20 V gm ISOURCE ISINK IINTVCC = 30 mA 80 VBST to VSW = 5 V RILIM = floating, VBST to VSW = 5 V RILIM = 47 kΩ, VBST to VSW = 5 V 6.4 3.4 tMIN_ON tMIN_OFF tR tF CDL = 2.2 nF, see Figure 23 CDL = 2.2 nF, see Figure 26 fSW ROSC = 100 kΩ 510 250 48 8 4.8 50 120 80 9.6 6.2 mΩ A A mV 130 150 ns ns 20 10 4 1.4 6 3 ns ns Ω Ω 690 1200 kHz kHz 1200 kHz ns ns V V 600 SYNC configured as input 300 100 100 1.3 0.4 SYNC configured as output fCLKOUT fSW kHz ns 100 ISS 2.5 Rev. 0 | Page 4 of 32 3.5 4.5 μA Data Sheet Parameters TRACKING INPUT (TRKx PINS) TRKx Input Voltage Range TRKx-to-FBx Offset Voltage TRKx Input Bias Current POWER GOOD (PGOODx PINS) Power-Good Rising Threshold Power-Good Hysteresis Power-Good Deglitch Time PGOODx Leakage Current PGOODx Output Low Voltage ENABLE (ENx PINS) ENx Rising Threshold ENx Falling Threshold ENx Source Current ADP2325 Symbol Test Conditions/Comments Min TRKx = 0 mV to 500 mV 0 −12 87 From FBx to PGOODx VPGOOD = 5 V IPGOOD = 1 mA 1.02 EN voltage below falling threshold EN voltage above rising threshold MODE (MODE PIN) Input High Voltage Input Low Voltage THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Typ Max Unit 600 +12 100 mV mV nA 90 5 16 0.1 50 93 % % Clock cycles µA mV 1.2 1.1 5 1.28 1 100 1 µA 1.3 0.4 150 15 Tested in a feedback loop that adjusts VFB to achieve a specified voltage on the COMPx pin. Pin-to-pin measurements. 3 Guaranteed by design. 1 2 Rev. 0 | Page 5 of 32 V V µA V V °C °C ADP2325 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter PVIN1, PVIN2, EN1, EN2 SW1, SW2 BST1, BST2 FB1, FB2, SS1, SS2, COMP1, COMP2, PGOOD1, PGOOD2, TRK1, TRK2, SCFG, SYNC, RT, MODE INTVCC, VDRV, DL1, DL2 PGND to GND Temperature Range Operating (Junction) Storage Soldering Conditions θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.3 V to +22 V −1 V to +22 V VSW + 6 V −0.3 V to +6 V Boundary Condition θJA is measured using natural convection on a JEDEC 4-layer board, and the exposed pad is soldered to the printed circuit board (PCB) with thermal vias. −0.3 V to +6 V −0.3 V to +0.3 V Table 3. Thermal Resistance −40°C to +125°C −65°C to +150°C JEDEC J-STD-020 ESD CAUTION Package Type 32-Lead LFCSP_WQ Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 32 θJA 32.7 Unit °C/W Data Sheet ADP2325 32 31 30 29 28 27 26 25 FB1 COMP1 SS1 TRK1 EN1 PVIN1 PVIN1 SW1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADP2325 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 SW1 BST1 DL1 PGND VDRV DL2 BST2 SW2 NOTES 1. THE EXPOSED PAD SHOULD BE SOLDERED TO AN EXTERNAL GND PLANE. 10036-004 FB2 COMP2 SS2 TRK2 EN2 PVIN2 PVIN2 SW2 9 10 11 12 13 14 15 16 PGOOD1 SCFG SYNC GND INTVCC RT MODE PGOOD2 Figure 4. Pin Configuration (Top View) Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic PGOOD1 SCFG 3 SYNC 4 5 GND INTVCC 6 7 RT MODE 8 9 PGOOD2 FB2 10 COMP2 11 SS2 12 TRK2 13 EN2 14, 15 PVIN2 16, 17 18 19 SW2 BST2 DL2 20 21 22 VDRV PGND DL1 23 BST1 Description Power-Good Output (Open Drain) for Channel 1. A pull-up resistor of 10 kΩ to 100 kΩ is recommended. Synchronization Configuration Input. The SCFG pin configures the SYNC pin as an input or an output. Connect SCFG to INTVCC to configure SYNC as an output. Connecting a pull-down resistor to GND configures SYNC as an input with various phase shift degrees. Synchronization. This pin can be configured as an input or an output. When configured as an output, it provides a clock at the switching frequency. When configured as an input, this pin accepts an external clock to which the regulators are synchronized. The phase shift is configured by SCFG. Note that when SYNC is configured as an input, the PFM mode is disabled and the device works in continuous conduction mode (CCM) only. Analog Ground. Connect to the ground plane. Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a 1 μF ceramic capacitor between INTVCC and GND. Connect a resistor between RT and GND to program the switching frequency from 250 kHz to 1.2 MHz. Mode Selection. When this pin is connected to INTVCC, the PFM mode is disabled and the regulator works only in CCM. When this pin is connected to ground, the PFM mode is enabled. If the low-side device is a diode, the MODE pin must be connected to ground. Power-Good Output (Open Drain) for Channel 2. A pull-up resistor of 10 kΩ to 100 kΩ is recommended. Feedback Voltage Sense Input for Channel 2. Connect FB2 to a resistor divider from the Channel 2 output voltage, VOUT2. Connect FB2 to INTVCC for parallel applications. Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to GND. Connect COMP1 and COMP2 together for parallel applications. Soft Start Control for Channel 2. To program the soft start time, connect a capacitor from SS2 to GND. For parallel applications, SS2 remains open. Tracking Input for Channel 2. To track a master voltage, connect this pin to a resistor divider from the master voltage. If the tracking function is not used, connect TRK2 to INTVCC. Enable Pin for Channel 2. An external resistor divider can be used to set the turn-on threshold. When not using the enable pin, connect EN2 to PVIN2. Power Input for Channel 2. Connect PVIN2 to the input power source, and connect a bypass capacitor between PVIN2 and ground. Switch Node for Channel 2. Supply Rail for the Gate Drive of Channel 2. Place a 0.1 μF capacitor between SW2 and BST2. Low-Side Gate Driver Output for Channel 2. Connect a resistor between DL2 and PGND to program the currentlimit threshold of Channel 2. Low-Side Driver Supply Input. Connect VDRV to INTVCC. Place a 1 μF ceramic capacitor between the VDRV pin and PGND. Driver Power Ground. Connect to the source of the synchronous N-channel MOSFET. Low-Side Gate Driver Output for Channel 1. Connect a resistor between DL1 and PGND to program the currentlimit threshold of Channel 1. Supply Rail for the Gate Drive of Channel 1. Place a 0.1 μF capacitor between SW1 and BST1. Rev. 0 | Page 7 of 32 ADP2325 Pin No. 24, 25 26, 27 Mnemonic SW1 PVIN1 28 EN1 29 TRK1 30 31 SS1 COMP1 32 N/A1 FB1 EP 1 Data Sheet Description Switch Node for Channel 1. Power Input for Channel 1. These pins are the power inputs for Channel 1 and provide power for the internal regulator. Connect to the input power source and connect a bypass capacitor between PVIN1 and ground. Enable Pin for Channel 1. An external resistor divider can be used to set the turn-on threshold. When not using the enable pin, connect EN1 to PVIN1. Tracking Input for Channel 1. To track a master voltage, connect this pin to a resistor divider from the master voltage. If the tracking function is not used, connect TRK1 to INTVCC. Soft Start Control for Channel 1. To program the soft start time, connect a capacitor from SS1 to GND. Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to GND. Connect COMP1 and COMP2 together for parallel applications. Feedback Voltage Sense Input for Channel 1. Connect FB1 to a resistor divider from the Channel 1 output voltage, VOUT1. Exposed Pad. Solder the exposed pad to an external GND plane. N/A means not applicable. Rev. 0 | Page 8 of 32 Data Sheet ADP2325 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 12 V, VOUT = 3.3 V, L = 2.2 µH, COUT = 2 × 100 µF, fSW = 600 kHz, unless otherwise noted. 100 90 85 85 EFFICIENCY (%) 90 80 75 70 65 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 70 VOUT = 5.0V VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 55 5.0 OUTPUT CURRENT (A) 50 0 100 INDUCTOR: FDVE1040-2R2M MOSFET: FDS8880 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INDUCTOR: FDVE1040-4R7M MOSFET: FDS8880 90 80 80 70 70 60 50 40 30 60 50 40 30 20 0 0.01 0.1 20 FPWM FPWM PFM PFM 1 OUTPUT CURRENT (A) VOUT = 5.0V, VOUT = 3.3V, VOUT = 5.0V, VOUT = 3.3V, 10 0 0.01 10036-006 VOUT = 5.0V, VOUT = 3.3V, VOUT = 5.0V, VOUT = 3.3V, 10 0.1 FPWM FPWM PFM PFM 1 OUTPUT CURRENT (A) Figure 6. Efficiency at VIN = 12 V, fSW = 600 kHz, FPWM and PFM Figure 9. Efficiency at VIN = 12 V, fSW = 300 kHz, FPWM and PFM 100 100 INDUCTOR: FDVE1040-1R5M MOSFET: FDS8880 95 90 85 85 EFFICIENCY (%) 90 80 75 70 65 80 75 70 65 55 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 OUTPUT CURRENT (A) 5.0 VOUT = 5.0V VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 60 55 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 OUTPUT CURRENT (A) Figure 10. Efficiency at VIN = 18 V, fSW = 300 kHz, FPWM Figure 7. Efficiency at VIN = 5 V, fSW = 600 kHz, FPWM Rev. 0 | Page 9 of 32 5.0 10036-010 VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 60 50 INDUCTOR: FDVE1040-4R7M MOSFET: FDS8880 95 10036-007 EFFICIENCY (%) 1.5 Figure 8. Efficiency at VIN = 12 V, fSW = 300 kHz, FPWM EFFICIENCY (%) EFFICIENCY (%) 90 1.0 OUTPUT CURRENT (A) Figure 5. Efficiency at VIN = 12 V, fSW = 600 kHz, FPWM 100 0.5 10036-008 0 75 60 10036-005 55 80 65 VOUT = 5.0V VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 60 50 INDUCTOR: FDVE1040-4R7M MOSFET: FDS8880 95 10036-009 95 EFFICIENCY (%) 100 INDUCTOR: FDVE1040-2R2M MOSFET: FDS8880 ADP2325 40 Data Sheet 3.10 TJ = –40°C TJ = +25°C TJ = +125°C 3.05 QUIESCENT CURRENT (mA) 30 25 20 3.00 2.95 2.90 2.85 15 6 8 10 12 14 16 18 20 VIN (V) 2.80 10036-011 4 4 6 4.4 12 14 16 18 20 Figure 14. Quiescent Current vs. VIN 1.30 RISING FALLING RISING FALLING 1.25 ENABLE THRESHOLD (V) 4.3 UVLO THRESHOLD (V) 10 VIN (V) Figure 11. Shutdown Current vs. VIN 4.5 8 10036-014 SHUTDOWN CURRENT (μA) 35 10 TJ = –40°C TJ = +25°C TJ = +125°C 4.2 4.1 4.0 3.9 3.8 3.7 1.20 1.15 1.10 1.05 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 1.00 –40 10036-012 20 40 60 80 100 120 Figure 15. EN Threshold vs. Temperature 1.10 5.30 1.08 5.25 5.20 EN SOURCE CURRENT (µA) 1.06 1.04 1.02 1.00 0.98 0.96 0.94 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80 0.92 4.75 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 4.70 –40 10036-013 EN SOURCE CURRENT (µA) 0 TEMPERATURE (°C) Figure 12. UVLO Threshold vs. Temperature 0.90 –40 –20 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 13. EN Source Current vs. Temperature at VEN = 1.5 V Figure 16. EN Source Current vs. Temperature at VEN = 1 V Rev. 0 | Page 10 of 32 10036-016 3.5 –40 10036-015 3.6 Data Sheet ADP2325 600 604 580 TRANSCONDUCTANCE (µS) 602 601 600 599 598 597 560 540 520 500 480 460 440 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 400 –40 10036-017 INTVCC VOLTAGE (V) FREQUENCY (kHz) 60 80 100 120 5.2 620 600 580 560 5.0 4.8 4.6 4.4 4.2 0 20 40 60 80 100 120 4.0 10036-018 –20 TEMPERATURE (°C) 4 6 8 10 12 14 16 18 20 VIN (V) Figure 21. INTVCC Voltage vs. VIN Figure 18. Frequency vs. Temperature 4.5 75 4.3 SSx PIN SOURCE CURRENT (µA) 80 70 65 60 55 50 45 40 4.1 3.9 3.7 3.5 3.3 3.1 2.9 35 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 10036-019 MOSFET RESISTOR (mΩ) 40 5.4 640 30 –40 20 Figure 20. Transconductance (gm) vs. Temperature ROSC = 100kΩ 540 –40 0 TEMPERATURE (°C) Figure 17. Feedback Voltage vs. Temperature 660 –20 10036-021 596 –40 10036-020 420 Figure 19. MOSFET RDSON vs. Temperature 2.7 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 22. SSx Pin Source Current vs. Temperature Rev. 0 | Page 11 of 32 120 10036-022 FEEDBACK VOLTAGE (mV) 603 ADP2325 Data Sheet SW 1 SW 1 DL DL 2 CH2 2V M20ns T 40.4% A CH1 4V CH1 5V 9.5 6.5 9.0 6.0 8.5 8.0 7.5 A CH2 4.04V 5.5 5.0 4.5 0 20 40 60 80 100 3.5 –40 10036-024 –20 120 TEMPERATURE (°C) –20 0 20 40 60 80 100 10036-025 4.0 7.0 6.5 –40 M20ns T 40.4% Figure 26. Low-Side Driver Falling Edge Waveform, CDL = 2.2 nF PEAK CURRENT LIMIT (A) PEAK CURRENT LIMIT (A) Figure 23. Low-Side Driver Rising Edge Waveform, CDL = 2.2 nF CH2 2V 10036-026 CH1 5V 10036-023 2 120 TEMPERATURE (°C) Figure 24. Peak Current-Limit Threshold vs. Temperature, RILIM = Floating Figure 27. Peak Current-Limit Threshold vs. Temperature, RILIM = 47 kΩ VOUT (AC) VOUT (AC) 1 1 IL IL 4 SW SW 4 2 B W CH2 10V CH4 2A Ω M 1µs T 42.6% A CH2 4.6V CH1 10mV Figure 25. Continuous Conduction Mode (CCM) B W CH2 10V CH4 1A Ω M 1µs T 47.2% A CH2 8.4V Figure 28. Discontinuous Conduction Mode (DCM) Rev. 0 | Page 12 of 32 10036-029 CH1 10mV 10036-028 2 Data Sheet ADP2325 VOUT (AC) SW1 1 1 SW2 IL 4 2 IL1 SW IL2 2 B W CH2 10V CH4 1A Ω M 1ms T 47.2% A CH2 8.4V CH1 10V CH3 2A Ω Figure 29. Power Saving Mode B CH2 10V CH4 2A Ω W B W M 1µs T 50.4% A CH2 5.6V 10036-040 CH1 100mV 10036-032 4 Figure 32. Dual Phase, Single Output, VOUT = 3.3 V, IOUT = 10 A EN EN 3 3 VOUT VOUT 1 1 2 IL IOUT CH2 5V CH4 5A Ω W M 1ms T 20.2% A CH3 3.4V 10036-030 B CH1 2V CH3 10V B CH2 5V CH4 2A Ω W M 1ms T 20.2% A CH3 3.4V 10036-033 4 4 CH1 2V CH3 10V PGOOD 11.5V 10036-034 2 PGOOD Figure 33. Soft Start with Precharged Output Figure 30. Soft Start with Full Load VOUT (AC) VOUT (AC) 1 1 VIN IOUT 4 CH1 100mV B W CH4 2A Ω M 200µs T 20.2% A CH4 3.4A 10036-031 3 CH1 20mV CH3 5V Figure 31. Load Transient Response, 1 A to 4 A B B W W M 400µs T 73.8% A CH3 Figure 34. Line Transient Response, VIN from 8 V to 14 V, IOUT = 5 A Rev. 0 | Page 13 of 32 ADP2325 Data Sheet VOUT VOUT 1 1 SW SW 2 2 IL IL 4 W CH2 10V CH4 5A Ω M 10ms T 19.8% A CH1 1.32V B CH1 2V W Figure 35. Output Short CH2 10V CH4 5A Ω M 10ms T 60.2% A CH1 1.32V 10036-038 B 2.8V 10036-039 CH1 2V 10036-035 4 Figure 38. Output Short Recovery SYNC SYNC 3 3 SW1 SW1 1 1 SW2 SW2 2 CH1 10V CH3 5V CH2 10V M 1µs T 50.4% A CH3 2.8V 10036-036 2 CH1 10V CH3 5V Figure 36. External Synchronization with 60° Phase Shift CH2 10V M 1µs T 50.4% A CH3 Figure 39. External Synchronization with 90° Phase Shift SYNC SYNC 3 3 SW1 SW1 1 1 SW2 SW2 CH2 10V M 1µs T 50.4% A CH3 2.8V 10036-037 CH1 10V CH3 5V CH1 10V CH3 5V Figure 37. External Synchronization with 120° Phase Shift CH2 10V M 1µs T 50.0% A CH3 Figure 40. SYNC Pin Configured as Output Rev. 0 | Page 14 of 32 2.5V 10036-048 2 2 Data Sheet ADP2325 VMASTER VMASTER VSLAVE VSLAVE 2 CH2 1V W B W M 1ms T 50.4% A CH1 1.56V CH1 1V Figure 41. Coincident Tracking 6 VOUT1 = 1.2V VOUT2 = 3.3V fSW = 500kHz OUTPUT CURRENT OF CH1 (A) 5 4 3 2 1 0 25 CH1 = 0A CH1 = 1A CH1 = 2A CH1 = 3A CH1 = 4A CH1 = 5A 40 70 AMBIENT TEMPERATURE (°C) B W M 1ms T 49.8% A CH1 1.58V 5 VOUT1 = 1.2V VOUT2 = 3.3V fSW = 500kHz 4 3 2 1 55 CH2 1V W Figure 43. Ratiometric Tracking 85 100 0 25 10036-058 OUTPUT CURRENT OF CH2 (A) 6 B 10036-059 B Figure 42. Thermal Derating Performance at 110°C Case Temperature Based on ADP2325-EVALZ Board CH2 = 0A CH2 = 1A CH2 = 2A CH2 = 3A CH2 = 4A CH2 = 5A 40 55 70 AMBIENT TEMPERATURE (°C) 85 100 10036-060 CH1 1V 10036-057 2 Figure 44. Thermal Derating Performance at 110°C Case Temperature Based on ADP2325-EVALZ Board Rev. 0 | Page 15 of 32 ADP2325 Data Sheet THEORY OF OPERATION The ADP2325 is a full featured, dual output, step-down dc-to-dc regulator based on a current mode architecture. It integrates two high-side power MOSFETs and two low-side drivers for external MOSFETs. The ADP2325 is designed for high performance applications that require high efficiency and design flexibility. PRECISION ENABLE/SHUTDOWN The ADP2325 can operate with an input voltage from 4.5 V to 20 V and can regulate the output voltage to as low as 0.6 V. Additional features for flexible design include programmable switching frequency, programmable soft start, external compensation, independent enable inputs, and power-good outputs. When the voltage on the EN1 or EN2 pin exceeds 1.2 V (typical), Channel 1 (per the EN1 pin) or Channel 2 (per the EN2 pin) is enabled and the internal pull-down current source at the EN1 or EN2 pin is reduced to 1 μA, which allows the user to program the UVLO lockout of the input voltage. CONTROL SCHEME When the voltage on the EN1 or EN2 pin drops below 1.1 V (typical), Channel 1 or Channel 2 turns off. When EN1 and EN2 are both below 1.1 V, all of the internal circuits turn off and the device enters the shutdown mode. The ADP2325 uses a fixed frequency, current mode PWM control architecture during medium to full loads, but shifts to a power save mode (PFM) at light loads when the PFM mode is enabled. The power save mode reduces switching losses and boosts efficiency under light loads. When operating in the fixed frequency PWM mode, the duty cycle of the integrated N-channel MOSFET (referred to interchangeably as NFET or MOSFET) is adjusted, this, in turn, regulates the output voltage. When the device operates in power save mode, the switching frequency is adjusted to regu late the output voltage. PWM MODE In PWM mode, the ADP2325 operates at a fixed frequency set by an external resistor. At the start of each oscillator cycle, the high-side NFET turns on, placing a positive voltage across the inductor. The inductor current increases until the current sense signal crosses the peak inductor current threshold, turning off the high-side NFET and turning on the low-side NFET (diode). This places a negative voltage across the inductor, causing a reduction in the inductor current. The low-side NFET (diode) stays on for the remainder of the cycle or until the inductor current reaches zero. The ADP2325 has two independent enable pins (EN1 and EN2), one for each channel. The ENx pin has an internal pulldown current source of 5 μA to provide a default turn-off whenever an ENx pin is open. SEPARATE INPUT VOLTAGES The ADP2325 supports two separate input voltages. This means that the PVIN1 and PVIN2 voltages can be connected to two different supply voltages. In these types of applications, because the PVIN1 voltage provides the power supply for the internal regulator and control circuitry, the PVIN1 voltage must be above the UVLO voltage before the PVIN2 voltage begins to rise. This feature allows for a cascading supply operation, as shown in Figure 45 where PVIN2 is sourced from the Channel 1 output. In this configuration, the Channel 1 output voltage needs to be high enough to maintain Channel 2 in regulation, and the Channel 1 output voltage must be higher than the input voltage UVLO threshold. VIN L1 L2 COUT1 M1 SW1 SW2 DL1 DL2 M2 VOUT2 COUT2 PGND 10036-041 When the device enters the PFM mode, it monitors the FBx voltage to regulate the output voltage. Because the high-side and lowside NFETs are turned off, the load current discharges the output capacitor causing the output voltage to drop. When the FBx voltage drops below 0.605 V, the device starts switching and the output voltage increases as the output capacitor is charged by the inductor current. When the FBx voltage exceeds 0.62 V, the device turns off both the high-side and low-side NFETs until the FBx voltage drops to 0.605 V. In the PFM mode, the output voltage ripple is larger than the ripple in the PWM mode. PVIN2 ADP2325 VOUT1 PFM MODE To enable the PFM mode, pull the MODE pin to ground. When the COMPx voltage is below the PFM threshold voltage, the device enters the PFM mode. PVIN1 Figure 45. Cascading Supply Operation INTERNAL REGULATOR (INTVCC) The internal regulator provides a stable voltage supply for the internal control circuits and a bias voltage for the low-side gate drivers. It is recommended that a 1 μF ceramic capacitor be placed between INTVCC and GND. The internal regulator also includes a current-limit circuit for protection. The internal regulator is active when either of the channels is enabled. The PVIN1 pin provides power for the internal regulator, which is used by both channels. Rev. 0 | Page 16 of 32 Data Sheet ADP2325 The ADP2325 integrates the boot regulators to provide the gate drive voltage for the high-side NFETs. The regulators generate 5 V bootstrap voltages between the BSTx and the SWx pins. When the SYNC pin is configured as an input, the ADP2325 synchronizes to the external clock that is applied to the SYNC pin, and the internal clock must be programmed lower than the external clock. The phase shift can be programmed by the SCFG pin. It is recommended that an X7R or X5R, 0.1 μF ceramic capacitor be placed between the BSTx and the SWx pins. When working in synchronization mode, the ADP2325 disables the PFM mode and works only in the CCM mode. LOW-SIDE DRIVER SOFT START The DLx pin provides the gate drive for the low-side N-channel MOSFET. Internal circuitry monitors the gate driver signal to ensure break-before-make switching to prevent crossconduction. Use the SSx pins to program the soft start time. Place a capacitor between SSx and GND; an internal current charges this capacitor to establish the soft start ramp. The soft start time can be calculated using the following equation: BOOTSTRAP CIRCUITRY The VDRV pin provides the power supply to the low-side drivers. It is limited to a 5.5 V maximum input; placing a 1 μF ceramic capacitor close to this pin is recommended. OSCILLATOR A resistor from RT to GND programs the switching frequency according to the following equation: fSW [kHz] = 0.6 V CSS I SS where: CSS is the soft start capacitance. ISS is the soft start pull-up current (3.5 μA). If the output voltage is precharged prior to power-up, the ADP2325 prevents the low-side MOSFET from turning on until the soft start voltage exceeds the voltage on the FBx pin. 60 ,000 ROSC [kΩ] A 200 kΩ resistor sets the frequency to 300 kHz, and a 100 kΩ resistor sets the frequency to 600 kHz. Figure 46 shows the typical relationship between fSW and ROSC. 1200 1100 SWITCHING FREQUENCY (kHz) t SS 1000 900 During soft start, the ADP2325 uses frequency foldback to prevent output current runaway. The switching frequency is reduced according to the voltage present at the FBx pin, which allows more time for the inductor to discharge. The correlation between the switching frequency and the FBx pin voltage is listed in Table 6. Table 6. FBx Pin Voltage and Switching Frequency 800 FBx Pin Voltage VFB ≥ 0.4 V 0.4 V > VFB ≥ 0.2 V VFB < 0.2 V 700 600 500 400 Switching Frequency fSW 1/2 fSW 1/4 fSW PEAK CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION 200 50 70 90 110 130 150 170 190 210 230 ROSC (kΩ) 250 10036-042 300 Figure 46. fSW vs. ROSC SYNCHRONIZATION The SYNC pin can be configured as an input or an output by setting the SCFG pin, as shown in Table 5. Table 5. SCFG Configuration SCFG INTVCC GND 180 kΩ to GND 100 kΩ to GND SYNC Output Input Input Input Phase Shift 0° 90° 120° 60° When the SYNC pin is configured as an output, it generates a clock with a frequency that is equal to the internal switching frequency. The ADP2325 uses a peak current-limit protection circuit to prevent current runaway. Place a resistor between DLx and PGND to program the peak current-limit value, as listed in Table 7. The programmable peak current-limit threshold feature allows for the use of a small size inductor for low current applications. Table 7. Peak Current-Limit Threshold Setting RILIM Floating 47 kΩ Peak Current-Limit Threshold 8A 4.8 A The ADP2325 uses hiccup mode for overcurrent protection. When the peak inductor current reaches the current-limit threshold, the high-side MOSFET turns off and the low-side driver turns on until the next cycle while the overcurrent counter is incremented. Rev. 0 | Page 17 of 32 ADP2325 Data Sheet Coincident Tracking A common application is coincident tracking, which is shown in Figure 48. Coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. To enable coincident tracking, set RTRK_TOP = RTOP and RTRK_BOT = RBOT. VMASTER In some cases, the input voltage (PVIN) ramp rate is too slow or the output capacitor is too large to support the set regulation voltage during the soft start, causing the device to enter the hiccup mode. To prevent such cases, use a resistor divider at the ENx pin to program the UVLO of the input voltage or use a longer soft start time. VOLTAGE The ADP2325 provides a negative current limit. When the low-side FET voltage exceeds the negative current-limit threshold voltage (50 mV typical), the low-side FET turns off immediately for the remainder of this cycle. Both the high-side and low-side FETs turn off until the next cycle. VSLAVE TIME Figure 48. Coincident Tracking Ratiometric Tracking In ratiometric tracking, the slave output voltage is limited to a fraction of the master voltage. In this application, the slave and master voltages reach their final values at the same time (see Figure 49). VOLTAGE TRACKING VMASTER The internal error amplifier includes three positive inputs: the internal reference voltage, the soft start voltage, and the tracking input voltage. The error amplifier regulates the feedback voltage to the lowest of the three voltages. To track a master voltage, connect the TRKx pin to a resistor divider from the master voltage, as shown in Figure 47. VOLTAGE TIME Figure 49. Ratiometric Tracking The ratio of the slave output voltage to the master voltage is a function of the two dividers, as follows: 1+ VSLAVE ADP2325 FBx RBOT Figure 47. Voltage Tracking The final TRKx pin voltage must be higher than 0.54 V. If the tracking function is not used, connect the TRKx pin to INTVCC. PARALLEL OPERATION RTOP 10036-043 RTRK_BOT SWx RTOP RBOT VSLAVE = VMASTER 1 + RTRK _ TOP RTRK _ BOT VMASTER RTRK_TOP VSLAVE 10036-045 The ADP2325 has a tracking input, TRKx, that allows the output voltage to track an external (master) voltage. Voltage tracking allows power sequencing applicable for FPGAs, DSPs, and ASICs, which may require a power sequence between the core and the I/O voltages. TRKx 10036-044 If the overcurrent counter reaches 10, or if the FBx pin voltage falls to 0.2 V after the soft start, the device enters hiccup mode. During this mode, the high-side MOSFET and low-side driver are both turned off. The device remains in this mode for seven soft start cycles and then attempts to restart from soft start. If the current-limit fault is cleared, the device resumes normal operation; otherwise, it reenters hiccup mode. The ADP2325 supports a 2-phase parallel operation to provide a single output of 10 A. To configure the ADP2325 as a 2-phase single output 1. 2. 3. Connect the FB2 pin to INTVCC, thereby disabling the Channel 2 error amplifier. Connect COMP1 to COMP2 and connect EN1 to EN2. Use SS1 to set the soft start time and keep SS2 open. During parallel operation, the voltages of PVIN1 and PVIN2 should be the same. Rev. 0 | Page 18 of 32 Data Sheet ADP2325 POWER GOOD The power-good (PGOODx) pin is an active high, open-drain output that indicates whether the regulator output voltage is within regulation. Logic high indicates that the voltage at the FBx pin (and, therefore, the output voltage) is above 90% of the reference voltage. Logic low indicates that the voltage at the FBx pin (and, therefore, the output voltage) is below 85% of the reference voltage. There is a 16-cycle deglitch time between FBx and PGOODx. OVERVOLTAGE PROTECTION The ADP2325 provides an OVP feature to protect the system against an output shorting to a higher voltage supply or for when a strong load transient occurs. If the feedback voltage increases to 0.7 V, the internal high-side MOSFET and low-side driver turn off until the voltage at the FBx pin is reduced to 0.63 V, at which time the ADP2325 resumes normal operation. UNDERVOLTAGE LOCKOUT The UVLO threshold is 4.2 V with 0.5 V hysteresis to prevent power-on glitches on the device. When the PVIN1 or PVIN2 voltage rises above 4.2 V, Channel 1 or Channel 2 is enabled and the soft start period initiates. When either PVIN1 or PVIN2 drops below 3.7 V, it turns off Channel 1 or Channel 2, respectively. THERMAL SHUTDOWN In the event that the ADP2325 junction temperature exceeds 150°C, the thermal shutdown circuit turns off the regulator. A 15°C hysteresis is included so that the ADP2325 does not recover from thermal shutdown until the on-chip temperature drops below 135°C. Upon recovery, soft start initiates prior to normal operation. Rev. 0 | Page 19 of 32 ADP2325 Data Sheet APPLICATIONS INFORMATION INPUT CAPACITOR SELECTION The input decoupling capacitor attenuates high frequency noise on the input and acts as an energy reservoir. This capacitor should be a ceramic capacitor in the range of 10 µF to 47 µF and must be placed close to the PVINx pin. The loop composed of this input capacitor, high-side NFET, and low-side NFET must be kept as small as possible. The voltage rating of the input capacitor must be greater than the maximum input voltage. Ensure that the rms current rating of the input capacitor is larger than that expressed in following equation: IC IN _rms = I OUT × D × (1 − D ) OUTPUT VOLTAGE SETTING The output voltage of the ADP2325 can be set by an external resistor divider using the following equation: R VOUT = 0.6 × 1 + TOP RBOT The maximum output voltage for a given input voltage and switching frequency is also limited by the minimum off time and the maximum duty cycle. The minimum off time is typically 150 ns and the maximum duty is typically 90% in the ADP2325. The maximum output voltage that is limited by the minimum off time at a given input voltage and frequency can be calculated using the following equation: VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON1 − RDSON2) × IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON2 + RL) × IOUT_MAX where: VOUT_MAX is the maximum output voltage. tMIN_OFF is the minimum off time. IOUT_MAX is the maximum output current. The maximum output voltage that is limited by the maximum duty cycle at a given input voltage can be calculated using the following equation: VOUT_MAX = DMAX × VIN where DMAX is the maximum duty cycle. To limit output voltage accuracy degradation due to FBx pin bias current (0.1 µA maximum) to less than 0.5% (maximum), ensure that RBOT is less than 30 kΩ. Table 8 provides the recommended resistor divider for various output voltage options. As the previous equations demonstrate, reducing the switching frequency alleviates the minimum on time and minimum off time limitation. Table 8. Resistor Divider for Various Output Voltages CURRENT-LIMIT SETTING VOUT (V) 1.0 1.2 1.5 1.8 2.5 3.3 5.0 The ADP2325 has two selectable current-limit thresholds. Make sure that the selected current-limit value is larger than the peak current of the inductor, IPEAK. RTOP, ±1% (kΩ) 10 10 15 20 47.5 10 22 RBOT, ±1% (kΩ) 15 10 10 10 15 2.21 3 INDUCTOR SELECTION VOLTAGE CONVERSION LIMITATIONS The minimum output voltage for a given input voltage and switching frequency is limited by the minimum on time. The minimum on time of the ADP2325 is typically 130 ns. The minimum output voltage in CCM mode at a given input voltage and frequency can be calculated using the following equation: The inductor value is determined by the operating frequency, input voltage, output voltage, and inductor ripple current. Using a small inductor provides faster transient response but degrades efficiency due to larger inductor ripple current, whereas a large inductor value provides smaller ripple current and better efficiency but results in a slower transient response. Thus, there is a trade-off between the transient response and efficiency. As a guideline, the inductor ripple current, ΔIL, is typically set to one-third of the maximum load current. The inductor value can be calculated by using the following equation: VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON1 − RDSON2) × IOUT_MIN × tMIN_ON × fSW − (RDSON2 + RL) × IOUT_MIN where: VOUT_MIN is the minimum output voltage. tMIN_ON is the minimum on time. IOUT_MIN is the minimum output current. fSW is the switching frequency. RDSON1 is the high-side MOSFET on resistance. RDSON2 is the low-side MOSFET on resistance. RL is the series resistance of the output inductor. L= (VIN − VOUT )× D ∆I L × f SW where: VIN is the input voltage. VOUT is the output voltage. ΔIL is the inductor ripple current. fSW is the switching frequency. D is the duty cycle. D= Rev. 0 | Page 20 of 32 VOUT VIN Data Sheet ADP2325 The ADP2325 uses adaptive slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is larger than 50%. The internal slope compensation limits the minimum inductor value. For a duty cycle that is larger than 50%, the minimum inductor value is determined by the following equation: VOUT 1 D 2 f SW The inductor peak current is calculated by I PEAK OUTPUT CAPACITOR SELECTION The output capacitor selection affects both the output voltage ripple and the loop dynamics of the regulator. For example, during load step transient on the output, when the load is suddenly increased, the output capacitor supplies the load until the control loop can ramp up the inductor current, which causes an undershoot of the output voltage. Use the following equation to calculate the output capacitance that is required to meet the voltage droop requirement: COUT_UV I I OUT L 2 The saturation current of the inductor must be larger than the peak inductor current. For the ferrite core inductors with a quick saturation characteristic, the saturation current rating of the inductor should be higher than the current-limit threshold of the switch to prevent the inductor from entering saturation. The rms current of the inductor can be calculated by I RMS I OUT 2 I L 2 12 where: ΔISTEP is the load step. ΔVOUT_UV is the allowable undershoot on the output voltage. KUV is a factor, typically setting KUV = 2. Another example is when a load is suddenly removed from the output and the energy stored in the inductor rushes into the output capacitor, which causes the output to overshoot. The output capacitance required to meet the overshoot requirement can be calculated using the following equation: Shielded ferrite core materials are recommended for low core loss and low EMI. Table 9. Recommended Inductors Vendor Sumida Coilcraft Wurth Elektronik Part No. CDRH105RNP-0R8N CDRH105RNP-1R5N CDRH105RNP-2R2N CDRH105RNP-3R3N CDRH105RNP-4R7N CDRH105RNP-6R8N MSS1048-152NL MSS1048-222NL MSS1048-332NL MSS1048-472NL MSS1048-682NL 7447797110 7447797180 7447797300 7447797470 7447797620 Value (μH) 0.8 1.5 2.2 3.3 4.7 6.8 1.5 2.2 3.3 4.7 6.8 1.1 1.8 3.0 4.7 6.2 ISAT (A) 13.5 10.5 9.25 7.8 6.4 5.4 10.5 8.4 7.38 6.46 5.94 16 13.3 10.5 8.0 7.5 IRMS (A) 9.5 8.3 7.5 6.5 6.1 5.4 10.8 9.78 7.22 6.9 6.01 7.6 7.3 7.0 5.8 5.5 DCR (mΩ) 4.3 5.8 7.2 10.4 12.3 18 5.1 7.2 10.1 11.4 15.4 14 16 18 27 30 K UV I STEP 2 L 2 VIN VOUT VOUT_UV COUT_OV K OV I STEP 2 L VOUT VOUT _ OV 2 VOUT 2 where: ΔVOUT_OV is the allowable overshoot on the output voltage. KOV is a factor, typically setting KOV = 2. The output ripple is determined by the ESR of the output capacitor and its capacitance value. Use the following equation to select a capacitor that can meet the output ripple requirements: COUT_RIPPLE R ESR I L 8 f SW VOUT_RIPPLE VOUT_RIPPLE I L where: ΔVOUT_RIPPLE is the allowable output voltage ripple. RESR is the equivalent series resistance of the output capacitor. Select the largest output capacitance given by COUT_UV, COUT_OV, and COUT_RIPPLE to meet both load transient and output ripple performance. The selected output capacitor voltage rating must be greater than the output voltage. The minimum rms current rating of the output capacitor is determined by the following equation: I COUT _ rms Rev. 0 | Page 21 of 32 I L 12 ADP2325 Data Sheet LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT The ADP2325 has integrated low-side MOSFET drivers, which can drive the low-side N-channel MOSFETs (NFETs). The selection of the low-side N-channel MOSFET affects the dc-to-dc regulator performance. The precision enable input can be used to program the UVLO threshold and hysteresis of the input voltage, as shown in Figure 50. PVINx The selected MOSFET must meet the following requirements: RTOP_EN • • RBOT_EN 1µA The ADP2325 low-side gate drive voltage is 5 V. Make sure that the selected MOSFET can be fully turned on at 5 V. When the high-side MOSFET is turned off, the low-side MOSFET carries the inductor current. For low duty cycle applications, the low-side MOSFET carries the current for most of the period. To achieve higher efficiency, it is important to select a low on-resistance MOSFET. The power conduction loss for the low-side MOSFET can be calculated by PFET_LOW = IOUT2 × RDSON × (1 − D) 1.2V 4µA 10036-046 Drain source voltage (VDS) must be higher than 1.2 × VIN. Drain current (ID) must be greater than 1.2 × ILIMIT_MAX, where ILIMIT_MAX is the selected maximum current-limit threshold. Total gate charge (Qg at 5 V) must be less than 50 nC. Lower Qg characteristics constitute higher efficiency. EN CMP ENx Figure 50. Programming the UVLO Input Use the following equation to calculate RTOP_EN and RBOT_EN: RTOP_EN = 1.1 V × VIN_RISING − 1.2 V × VIN_FALLING R BOT _ EN = 1.1 V × 5 μA − 1.2 V × 1 μA 1.2 V × RTOP _ EN VIN _ RISING − RTOP _ EN × 5 μΑ − 1.2 V where: VIN_RISING is the VIN rising threshold. VIN_FALLING is the VIN falling threshold. where RDSON is the on resistance of the low-side MOSFET. COMPENSATION COMPONENTS DESIGN Make sure that the MOSFET can handle the thermal dissipation due to the power loss. In peak current mode control, the power stage can be simplified to a voltage controlled current source supplying current to the output capacitor and load resistor. It is composed of one domain pole and a zero contributed by the output capacitor ESR. The control-to-output transfer function is shown in the following equations: In some cases, efficiency is not critical for the system; therefore, the diode can be selected as the low-side power device. The average current of the diode can be calculated by IDIODE (AVG) = (1 − D) × IOUT The reverse breakdown voltage rating of the diode must be greater than the input voltage with an appropriate margin to allow for ringing, which may be present at the SWx node. A Schottky diode is recommended because it has a low forward voltage drop and a fast switching speed. s 1 + 2 ×π × fZ V (s ) = AVI × R × GVD (s) = OUT VCOMP (s) s 1 + 2×π × f P If a diode is used for the low-side device, the ADP2325 must enable the PFM mode by connecting the MODE pin to ground. fZ = 1 2 × π × RESR × COUT Table 10. Recommended MOSFETs fP = 1 2 × π × (R + RESR ) × COUT Vendor Fairchild Fairchild Fairchild Vishay Vishay AOS AOS Part No. FDS8880 FDMS7578 FDS6898A Si4804CDY SiA430DJ AON7402 AO4884L VDS 30 V 25 V 20 V 30 V 20 V 30 V 40 V ID 10.7 A 14 A 9.4 A 7.9 A 10.8 A 39 A 10 A RDSON 12 mΩ 8 mΩ 14 mΩ 27 mΩ 18.5 mΩ 15 mΩ 16 mΩ Qg 12 nC 8 nC 16 nC 7 nC 5.3 nC 7.1 nC 13.6 nC where: AVI = 8.33 A/V. R is the load resistance. COUT is the output capacitance. RESR is the equivalent series resistance of the output capacitor. Rev. 0 | Page 22 of 32 Data Sheet ADP2325 The ADP2325 uses a transconductance amplifier for the error amplifier to compensate the system. Figure 51 shows the simplified peak current mode control small signal circuit. VOUT 4. VOUT RTOP RBOT VCOMP – gm + + AVI The following design guidelines show how to select the compensation components, RC, CC, and CCP, for ceramic output capacitor applications. 5. COUT RC = R RC CCP – RESR 10036-047 CC 6. Figure 51. Simplified Peak Current Mode Control Small Signal Circuit The compensation components, RC and CC, contribute a zero, and the optional CCP and RC contribute an optional pole. 7. RBOT −gm × × RBOT + RTOP CC + CCP 1 + RC × CC× s R × CC × CCP s × 1 + C × s CC + CCP 2 × π × VOUT × COUT × f C 0.6 V × g m × AVI Place the compensation zero at the domain pole (fP). CC can be determined by CC = The closed-loop transfer equation is as follows: TV (s) = Determine the cross frequency (fC). Generally, the fC is between fSW/12 and fSW/6. RC can be calculated by using the following equation: (R + RESR )× COUT CCP is optional. It can be used to cancel the zero caused by the ESR of the output capacitor. CCP = × GVD(s) RC RESR × COUT RC The ADP2325 has an internal 10 pF capacitor at the COMPx pin; therefore, if CCP is smaller than 10 pF, no external capacitor is required. Rev. 0 | Page 23 of 32 ADP2325 Data Sheet DESIGN EXAMPLE This section describes the design procedure and component selection for the example application shown in Figure 54, and Table 11 provides a list of the required settings. Table 11. Dual Step-Down DC-to-DC Regulator Requirements Parameter Channel 1 Input Voltage Output Voltage Output Current Output Voltage Ripple Load Transient Channel 2 Input Voltage Output Voltage Output Current Output Voltage Ripple Load Transient Switching Frequency Specification Calculate the peak-to-peak inductor ripple current as follows: ∆I L = VIN1 = 12.0 V ± 10% VOUT1 = 1.2 V IOUT1 = 5 A ΔVOUT1_RIPPLE = 12 mV ±5%, 1 A to 4 A, 1 A/µs For VOUT1 = 1.2 V, ΔIL1 = 1.44 A. For VOUT2 = 3.3 V, ΔIL2 = 1.45 A. I PEAK = I OUT + ∆I L 2 For the 1.2 V rail, the peak inductor current is 5.73 A, and for the 3.3 V rail, the peak inductor current is 5.73 A. The rms current through the inductor can be estimated by VIN2 = 12.0 V ± 10% VOUT2 = 3.3 V IOUT2 = 5 A ΔVOUT2_RIPPLE = 33 mV ±5%, 1 A to 4 A, 1 A/µs fSW = 500 kHz I RMS = I OUT 2 + ∆I L 2 12 The rms current of the inductor for both the 1.2 V and 3.3 V rails is approximately 5.02 A. For the 1.2 V rail, select an inductor with a minimum rms current rating of 5.01 A and a minimum saturation current rating of 5.73 A. For the 3.3 V rail, select an inductor with a minimum rms current rating of 5.02 A and a minimum saturation current rating of 5.73 A. Choose a 10 kΩ top feedback resistor (RTOP); calculate the bottom feedback resistor using the following equation: 0. 6 RBOT = RTOP × V − 0 . 6 OUT To set the output voltage to 1.2 V, the resistor values are RTOP1 = 10 kΩ and RBOT1 = 10 kΩ. To set the output voltage to 3.3 V, the resistors values are RTOP2 = 10 kΩ and RBOT2 = 2.21 kΩ. CURRENT-LIMIT SETTING For 5 A output current operation, the typical peak current limit is 8 A. In this case, no RILIM is required. FREQUENCY SETTING Based on these requirements, for the 1.2 V rail, select a 1.5 µH inductor, such as the Sumida CDRH105RNP-1R5N, with a DCR = 5.8 mΩ; for the 3.3 V rail, select a 3.3 µH inductor, such as the Sumida CDRH105RNP-3R3N, with a DCR = 10.4 mΩ. OUTPUT CAPACITOR SELECTION The output capacitor is required to meet the output voltage ripple and load transient requirements. To meet the output voltage ripple requirement, use the following equation to calculate the capacitance and ESR: COUT_RIPPLE = To set the switching frequency to 500 kHz, use the following equation to calculate the resistor value, ROSC: 60,000 f SW (kHz ) RESR = ∆I L 8 × f SW × ∆VOUT _ RIPPLE ∆VOUT _ RIPPLE IL For VOUT1 = 1.2 V, COUT_RIPPLE1 = 30 µF and RESR1 = 8.3 mΩ. For VOUT2 = 3.3 V, COUT_RIPPLE2 = 11 µF and RESR2 = 23 mΩ. Therefore, ROSC =120 kΩ. INDUCTOR SELECTION The peak-to-peak inductor ripple current, ΔIL, is set to 30% of the maximum output current. Use the following equation to estimate the value of the inductor: L= L × f SW Find the peak inductor current using the following equation: OUTPUT VOLTAGE SETTING ROSC (kΩ ) = (VIN − VOUT ) × D (VIN − VOUT )× D ∆I L × f SW For VOUT1 = 1.2 V, Inductor L1 = 1.4 µH, and for VOUT2 = 3.3 V, Inductor L2 = 3.2 µH. Select the standard inductor value of 1.5 µH and 3.3 µH for the 1.2 V and 3.3 V rails. Rev. 0 | Page 24 of 32 Data Sheet ADP2325 For the 1.2 V rail, ESR of the output capacitor must be smaller than 8.3 mΩ, and the output capacitance must be larger than 188 µF. It is recommend that three 100 µF, X5R, 6.3 V ceramic capacitors be used, such as the GRM32ER60J107ME20 from Murata, with an ESR = 2 mΩ. For the 3.3 V rail, the ESR of the output capacitor must be smaller than 23 mΩ, and the output capacitance must be larger than 55 µF. It is recommended that two 47 µF, X5R, 6.3 V ceramic capacitors be used, such as the Murata GRM32ER60J476ME20, with an ESR = 2 mΩ. 144 36 108 24 72 12 36 0 0 –12 –36 –24 –72 –36 –108 –48 –144 –60 1k RC2 = 2 × π × 3.3 V × 2 × 32 μF × 50 kHz CC2 = CCP2 = 2 × π × 1.2 V × 3 × 64 μF × 50 kHz CC1 = CCP1 = 0.6 V × 500 μS × 8.33 A/V = 28.9 kΩ (0.24 Ω + 0.001Ω)× 3 × 64 μF = 1598 pF 28.9 kΩ 0.001 Ω × 3 × 64 μF 28.9 kΩ = 6.6 pF 0.6 V × 500 μS × 8.33 A/V = 26.5 kΩ (0.66 Ω + 0.001Ω)× 2 × 32μF = 1594 pF 26.5 kΩ 0.001 Ω × 2 × 32 μF 26.5 kΩ = 2.4 pF By using standard component values of RC2 = 27 kΩ and CC2 = 1500 pF, no CCP2 is needed. Figure 53 shows the 3.3 V rail bode plot at 5 A. The cross frequency is 55 kHz and phase margin is 67°. MAGNITUDE (dB) RC1 = –180 Figure 52. Bode Plot for 1.2 V Rail For better load transient and stability performance, set the cross frequency, fC, to fSW/10. In this case, fSW runs at 500 kHz; therefore, the fC is set to 50 kHz. For the 1.2 V rail, the 100 µF ceramic output capacitor has a derated value of 64 µF. 1M For the 3.3 V rail, the 47 µF ceramic output capacitor has a derated value of 32 µF. A low RDSON N-channel MOSFET is selected for high efficiency solutions. The MOSFET breakdown voltage must be greater than 1.2 V × VIN, and the drain current must be greater than 1.2 V × ILIMIT. COMPENSATION COMPONENTS 2 100k FREQUENCY (Hz) LOW-SIDE MOSFET SELECTION It is recommended that a 30 V, N-channel MOSFET be used, such as the FDS8880 from Fairchild. The RDSON of the FDS8880 at a 4.5 V driver voltage is 12 mΩ, and the total gate charge is 12 nC. 1 10k PHASE (Degrees) For estimation purposes, use KOV = KUV = 2. For VOUT1 = 1.2 V, use COUT_OV1 = 188 µF and COUT_UV1 = 21 µF. For VOUT2 = 3.3 V, use COUT_OV2 = 55 µF and COUT_UV2 = 21 µF. 180 48 10036-061 K UV × ∆I STEP 2 × L = 2 × (VIN − VOUT ) × ∆VOUT _UV 60 60 180 48 144 36 108 24 72 12 36 0 0 –12 –36 –24 –72 –36 –108 –48 –144 –60 1k By choosing standard components where RC1 = 28 kΩ and CC1 = 1500 pF, no CCP1 is needed. Rev. 0 | Page 25 of 32 10k 1 100k FREQUENCY (Hz) Figure 53. Bode Plot for 3.3 V Rail 2 1M –180 PHASE (Degrees) COUT_UV K OV × ∆I STEP 2 × L (VOUT + ∆VOUT _ OV ) 2 − VOUT 2 MAGNITUDE (dB) COUT_OV = Figure 52 shows the 1.2 V rail bode plot at 5 A. The cross frequency is 42 kHz and the phase margin is 50°. 10036-062 To meet the ±5% overshoot and undershoot requirement, use the following equation to calculate the capacitance: ADP2325 Data Sheet SOFT START TIME PROGRAMMING INPUT CAPACITOR SELECTION The soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during soft start and limiting inrush current. The soft start time is set to 3 ms. A minimum 10 µF ceramic capacitor is required, placed near the PVINx pin. In this application, one X5R ceramic capacitor of 10 µF and 25 V is recommended. CSS = I SS × t SS 3.5 μA × 3 ms = = 17.5 nF 0. 6 V 0. 6 V Choose a standard component value of CSS1 = CSS2 = 22 nF. Rev. 0 | Page 26 of 32 Data Sheet ADP2325 EXTERNAL COMPONENTS RECOMMENDATIONS Table 12. Recommended External Components for Typical Applications with 5 A Output Current fSW (kHz) 300 600 1000 1 VIN (V) 12 12 12 12 12 12 12 5 5 5 5 5 5 12 12 12 12 12 5 5 5 5 5 5 12 12 12 12 5 5 5 5 5 5 VOUT (V) 1 1.2 1.5 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 1.5 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 L (µH) 2.2 2.2 3.3 3.3 4.7 4.7 6.8 1.5 2.2 2.2 2.2 2.2 2.2 1.5 1.5 2.2 2.2 3.3 1 1 1 1.5 1.5 1.5 1 1 1.5 2 0.56 0.56 0.68 0.8 0.8 0.8 COUT (µF) 1 2 × 330 2 × 330 2 × 330 330 330 2 × 100 100 + 47 2 × 330 2 × 330 330 330 2 × 100 100 330 3 × 100 2 × 100 100 + 47 100 330 330 2 × 100 2 × 100 100 + 47 100 2 × 100 100 100 47 3 × 100 2 × 100 2 × 100 100 + 47 100 47 RTOP (kΩ) 10 10 15 20 47.5 10 22 10 10 15 20 47.5 10 15 20 47.5 10 22 10 10 15 20 47.5 10 20 47.5 10 22 10 10 15 20 47.5 10 RBOT (kΩ) 15 10 10 10 15 2.21 3 15 10 10 10 15 2.21 10 10 15 2.21 3 15 10 10 10 15 2.21 10 15 2.21 3 15 10 10 10 15 2.21 RC (kΩ) 47 59 75 43 62 33 36 49 59 37 43 22 15 75 53 47 47 47 49 59 27 33 33 30 56 39 53 39 47 37 47 43 43 27 330 µF: 6.3 V, Sanyo 6TPD330M; 100 µF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 µF: 6.3 V, X5R, Murata GRM32ER60J476ME20. Rev. 0 | Page 27 of 32 CC (pF) 2700 2700 2700 2700 2700 2700 2700 2700 2700 2700 2700 2700 2700 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 820 820 820 820 820 820 820 820 820 820 CCP (pF) 56 56 47 68 56 3.3 3.3 68 56 82 68 4.7 4.7 47 2.2 2.2 2.2 2.2 68 56 4.7 3.3 2.2 4.7 2.2 2.2 2.2 2.2 2.2 6.8 4.7 4.7 4.7 2.2 ADP2325 Data Sheet TYPICAL APPLICATION CIRCUITS CC1 1500pF CSS1 22nF RC1 28kΩ MODE SCFG TRK2 TRK1 ADP2325 COUT4 47µF COUT5 47µF CSS2 22nF BST2 PVIN2 EN2 SS2 COMP2 FB2 RTOP2 10kΩ COUT2 100µF SW2 RC2 27kΩ CC2 1500pF RBOT2 2.21kΩ COUT1 100µF M2 FDS8880 DL2 PGOOD2 ROSC 120kΩ M1 FDS8880 VOUT1 1.2V 5A COUT3 100µF PGND GND PGOOD1 SYNC RT L1 1.5µH SW1 DL1 VDRV CDRV 1µF CBST1 0.1µF VOUT2 3.3V 5A L2 3.3µH CBST2 0.1µF VIN 12V CIN2 10µF, 25V 10036-050 FB1 INTVCC CINT 1µF COMP1 RBOT1 10kΩ VIN 12V CIN1 10µF, 25V SS1 EN1 PVIN1 BST1 RTOP1 10kΩ Figure 54. Using an External MOSFET Application, VIN1 = VIN2 = 12 V, VOUT1 = 1.2 V, IOUT1 = 5 A, VOUT2 = 3.3 V, IOUT2 = 5 A, fSW = 500 kHz SS1 EN1 PVIN1 BST1 SCFG TRK2 TRK1 VDRV CBST1 0.1µF D1 B320B DL1 ADP2325 PGND GND MODE PGOOD2 RBOT2 2.21kΩ RTOP2 10kΩ DL2 RC2 18kΩ CC2 4.7nF PVIN2 EN2 CSS2 10nF COUT1 22µF COUT2 22µF COUT3 22µF COUT4 22µF VOUT1 5V 3A RILIM1 47kΩ RILIM2 47kΩ D2 B220A SW2 SS2 COMP2 PGOOD1 SYNC RT FB2 ROSC 100kΩ L1 4.7µH SW1 BST2 CDRV 1µF INTVCC FB1 CINT 1µF COMP1 RBOT1 3kΩ VIN 12V CIN1 10µF, 25V L2 8.2µH CBST2 0.1µF CIN2 10µF, 25V VOUT2 3.3V 1.5A VIN 12V 10036-051 CC1 2.2nF CSS1 10nF RC1 20kΩ RTOP1 22kΩ Figure 55. Using an External Diode Application, VIN1 = VIN2 = 12 V, VOUT1 = 5 V, IOUT1 = 3 A, VOUT2 = 3.3 V, IOUT2 = 1.5 A, fSW = 600 kHz Rev. 0 | Page 28 of 32 Data Sheet ADP2325 RTOP1 10kΩ CC1 1200pF RC1 59kΩ RBOT1 10kΩ CSS1 22nF VIN TRK1 M1 FDS8880 DL2 PGOOD2 COUT3 10µF SW2 SW2 BST2 PVIN2 PVIN2 EN2 SS2 COMP2 FB2 GND COUT2 330µF M2 FDS8880 TRK2 VDRV COUT1 330µF PGND MODE CDRV 1µF VOUT1 1.2V, 10A L1 1µH DL1 ADP2325 RT ROSC 200kΩ CBST1 0.1µF SW1 SW1 PGOOD1 SCFG SYNC INTVCC CINT 1µF BST1 PVIN1 PVIN1 EN1 SS1 CIN1 12V 10µF, 25V COMP1 FB1 CCP1 56pF CBST2 0.1µF L2 1µH VIN 12V 10036-052 CIN2 10µF, 25V Figure 56. Parallel Single Output Application, VIN = 12 V, VOUT = 1.2 V, IOUT = 10 A, fSW = 300 kHz CC1 1200pF BST1 SS1 DL2 RT SW2 RC2 39kΩ CC2 1200pF CSS2 22nF BST2 PVIN2 EN2 M2 FDS8880 COMP2 FB2 M1 FDS8880 COUT1 100µF COUT2 100µF COUT3 100µF COUT4 47µF COUT5 47µF COUT6 47µF PGND PGOOD2 PGOOD1 SYNC RTOP2 47.5kΩ VOUT1 1.5V, 5A L1 1.5µH CBST2 0.1µF L2 2.2µH VOUT1 2.5V, 5A VIN 12V CIN2 10µF, 25V 10036-053 RBOT2 15kΩ CBST1 0.1µF DL1 ADP2325 GND MODE ROSC 100kΩ CIN1 10µF, 25V SW1 SS2 CDRV 1µF COMP1 FB1 RC1 47kΩ INTVCC SCFG TRK2 TRK1 VDRV CINT 1µF VIN 12V CSS1 22nF EN1 RBOT1 10kΩ PVIN1 RTOP1 15kΩ Figure 57. Enable PFM Mode with the MODE Pin Pulled to GND, VIN1 = VIN2 = 12 V, VOUT1 = 1.5 V, IOUT1 = 5 A, VOUT2 = 2.5 V, IOUT2 = 5 A, fSW = 600 kHz Rev. 0 | Page 29 of 32 ADP2325 Data Sheet RTOP1 20kΩ CC1 1200pF BST1 EN1 SS1 CBST1 0.1µF SW1 SCFG INTVCC MODE TRK2 TRK1 VDRV CDRV1 1µF CIN1 12V 10µF, 25V CSS1 22nF COMP1 FB1 SYNC CINT1 1µF VIN RC1 53kΩ PVIN1 RBOT1 10kΩ DL1 ADP2325 VOUT1 1.8V, 3A L1 1.5µH M1 FDS8880 COUT1 100µF COUT2 100µF M2 FDS8880 COUT4 100µF COUT5 100µF COUT3 100µF PGND GND DL2 CDRV2 1µF BST2 EN2 PVIN2 SW1 INTVCC MODE TRK2 TRK1 VDRV DL1 ADP2325 RTOP4 10kΩ RC4 62kΩ CC4 1200pF M3 FDS8880 COUT6 100µF COUT7 100µF M4 FDS8880 COUT9 100µF COUT10 100µF SW2 BST2 PVIN2 SS2 EN2 DL2 COMP2 FB2 VOUT3 1.8V, 3A L3 1.5µH COUT8 100µF CSS4 22nF CIN4 10µF, 25V L4 CBST4 2.2µH 0.1µF VOUT4 3.3V, 5A VIN 12V 10036-054 RBOT4 2.21kΩ CBST3 0.1µF PGND GND PGOOD2 PGOOD1 ROSC2 120kΩ BST1 CIN3 12V 10µF, 25V SCFG RT VIN 12V VIN CSS3 22nF PVIN1 COMP1 FB1 SYNC L2 CBST2 2.2µH 0.1µF CIN2 10µF, 25V CC3 1200pF RC3 53kΩ RBOT3 10kΩ VOUT2 3.3V, 5A SW2 CSS2 22nF CC2 1200pF RTOP2 10kΩ RTOP3 20kΩ CINT2 1µF SS2 RC2 62kΩ EN1 RBOT2 2.21kΩ SS1 ROSC1 100kΩ COMP2 RT FB2 PGOOD2 PGOOD1 Figure 58. Synchronization with 90° Phase Shift Between Each Channel Rev. 0 | Page 30 of 32 Data Sheet ADP2325 REN_BOT 68kΩ CC1 2200pF CINT 1µF SS1 COMP1 FB1 RPGOOD1 100kΩ INTVCC MODE SCFG ADP2325 DL2 RC2 82kΩ CCP2 36pF COUT1 100µF COUT2 100µF M2 FDS8880 COUT4 330µF COUT5 330µF COUT3 100µF BST2 PVIN2 EN2 CSS2 22nF L2 CBST2 3.3µH 0.1µF VIN 12V CIN2 10µF, 25V CC2 2200pF VOUT2 1.8V, 5A SW2 10036-055 RTOP2 20kΩ SS2 FB2 COMP2 RT M1 FDS8880 PGND GND ROSC 200kΩ VOUT1 3.3V, 5A L1 4.7µH DL1 VDRV CDRV 1µF CBST1 0.1µF SW1 TRK2 TRK1 RBOT2 10kΩ BST1 CSS1 22nF RC1 47kΩ SYNC PGOOD2 PGOOD1 VIN CIN1 12V 10µF, 25V PVIN1 RBOT1 2.21kΩ REN_TOP 330kΩ EN1 RTOP1 10kΩ Figure 59. Programmable VIN_RISING = 8.7 V, VIN_FALLING = 6.7 V, 3.3 V Startup Prior to 1.8 V, VIN1 = VIN2 = 12 V, VOUT1 = 3.3 V, IOUT1 = 5 A, VOUT2 = 1.8 V, IOUT2 = 5 A, fSW = 300 kHz RTOP1 47.5kΩ CC1 1200pF BST1 SS1 PVIN1 TRK2 PGOOD2 PGOOD1 SYNC COMP1 RTRK_BOT 15kΩ FB1 RTRK_TOP 47.5kΩ CSS1 22nF RC1 33kΩ EN1 RBOT1 15kΩ CBST1 0.1µF SW1 TRK1 MODE SCFG VDRV RTOP2 13kΩ CCP2 56pF RC2 49kΩ CC2 1500pF COUT2 47µF M2 FDS8880 COUT4 330µF COUT5 10µF SW2 BST2 PVIN2 SS2 EN2 RT COUT1 47µF COUT3 47µF CSS2 10nF CBST2 0.1µF CIN2 10µF, 25V L2 1.5µH VOUT2 1.25V, 5A VIN 12V 10036-056 RBOT2 12kΩ DL2 COMP2 ROSC 120kΩ M1 FDS8880 PGND GND FB2 CDRV 1µF DL1 ADP2325 VOUT1 2.5V, 5A L1 2.2µH INTVCC CINT 1µF VIN 12V CIN1 10µF, 25V Figure 60. Channel 2 Tracking with Channel 1 VIN1 = VIN2 = 12 V, VOUT1 = 2.5 V, IOUT1 = 5 A, VOUT2 = 1.25 V, IOUT2 = 5 A, fSW = 500 kHz Rev. 0 | Page 31 of 32 ADP2325 Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 9 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 61. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP2325ACPZ-R7 ADP2325-EVALZ ADP2325-BL1-EVZ ADP2325-BL2-EVZ 1 2 Temperature Range −40°C to +125°C Output Voltage Adjustable Package Description 2 32-Lead LFCSP_WQ Evaluation Board Blank Dual Output Evaluation Board Blank Single Output Evaluation Board Package Option CP-32-7 Z = RoHS Compliant Part. For the blank evaluation boards, users can request an unpopulated board from Analog Devices, Inc., through the ADIsimPower tool found at www.analog.com/ADIsimPower, as well as generate schematics and a bill of materials from the tool. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10036-0-2/12(0) www.analog.com/ADP2325 Rev. 0 | Page 32 of 32