ISL54205B ® Data Sheet September 25, 2007 MP3/USB 2.0 High Speed Switch with Negative Signal Handling FN6557.0 Features • High Speed (480Mbps) and Full Speed (12Mbps) Signaling Capability per USB 2.0 The Intersil ISL54205B dual SPDT (Single Pole/Double Throw) switches combine low distortion audio and accurate USB 2.0 high speed data (480Mbps) signal switching in the same low voltage device. When operated with a 2.7V to 3.6V single supply these analog switches allow audio signal swings below-ground, allowing the use of a common USB and audio headphone connector in Personal Media Players and other portable battery powered devices. • Low Distortion Negative Signal Capability • Detection of VBUS Voltage on USB Cable • Control Pin to Open all Switches and Enter Low Power State • Low Distortion Headphone Audio Signals - THD+N at 20mW into 32Ω Load . . . . . . . . . . . . . <0.1% The ISL54205B incorporates circuitry for detection of the USB VBUS voltage, which is used to switch between the audio and USB signal sources in the portable device. The part has a control pin to open all the switches and put the part in a low power down state. • Cross-talk (20Hz to 20kHz) . . . . . . . . . . . . . . . . . . -110dB • Single Supply Operation (VDD) . . . . . . . . . . . . 2.7V to 3.6V • -3dB Bandwidth USB Switch . . . . . . . . . . . . . . . . . 630MHz • Available in µTQFN and TDFN Packages The ISL54205B is available in a small 10 Ld 2.1mmx1.6mm ultra-thin µTQFN package and a 10Ld 3mmx3mm TDFN package. It operates over a temperature range of -40 to +85°C. • Pb-Free (RoHS Compliant) • Compliant with USB 2.0 Short Circuit Requirements Without Additional External Components Related Literature Applications • Application Note AN1280 “ISL54205EVAL1Z Evaluation Board User’s Manual. • MP3 and Other Personal Media Players • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • PDA’s • Cellular/Mobile Phones • Audio/USB Switching • Application Note AN557 “Recommended Test Procedures for Analog Switches” Application Block Diagram VDD VBUS µCONTROLLER ISL54205B CTRL USB/HEADPHONE JACK LOGIC CIRCUITRY 22kΩ 4MΩ 4MΩ D- COM D+ 50kΩ COM + USB HIGH-SPEED TRANSCEIVER L R CODEC 50kΩ GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL54205B Pinouts (Note 1) ISL54205B (10 LD TDFN) TOP VIEW ISL54205B (10 LD μTQFN) TOP VIEW CTRL 10 VDD VBUS COM - 3 COM + 4 9 LOGIC CONTROL 1 2 4M 1 VBUS 2 4M 4M 4M 50k D- VDD 10 LOGIC CONTROL CTRL 9 D- 8 D+ COM - 3 8 D+ 7 L COM + 4 7 L 6 R GND 5 6 R 50k 50k 50k 5 GND NOTE: 1. ISL54205B Switches shown for VBUS = Logic “0” and CTRL = Logic “1”. Truth Table ISL54205B VBUS CTRL L, R D+, D- 0 0 OFF OFF 0 1 ON OFF 1 X OFF ON CTRL: Logic “0” when ≤ 0.5V or Float, Logic “1” when ≥ 1.4V VBUS: Logic “0” when ≤ VDD + 0.2V or Float, Logic “1” when ≥VDD + 0.8V Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL54205BIRUZ-T* (Note 2) FW -40 to +85 10 Ld µTQFN Tape and Reel L10.2.1x1.6A ISL54205BIRTZ-T* (Note 3) 205B -40 to +85 10 Ld TDFN Tape and Reel L10.3x3A ISL54205BIRTZ (Note 3) 205B -40 to +85 10 Ld TDFN L10.3x3A ISL54205EVAL1Z Evaluation Board *Please refer to TB347 for details on reel specifications. NOTES: 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN6557.0 September 25, 2007 ISL54205B Pin Descriptions PIN NUMBER NAME 1 VDD FUNCTION 2 VBUS Digital Control Input 3 COM- Voice and Data Common Pin 4 COM+ Voice and Data Common Pin 5 GND 6 R Power Supply Ground Connection Audio Right Input 7 L 8 D+ USB Differential Input 9 D- USB Differential Input 10 CTRL 3 Audio Left Input Digital Control Input (Audio Enable) FN6557.0 September 25, 2007 ISL54205B Absolute Maximum Ratings Thermal Information VDD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.0V Input Voltages D+, D-, L, R (Note 4) . . . . . . . . . . . . . . . . . - 2V to ((VDD) + 0.3V) VBUS (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 5.5V CTRL (Note 4) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((VDD) + 0.3V) Output Voltages COM-, COM+ (Note 4) . . . . . . . . . . . . . . . . -2V to ((VDD) + 0.3V) Continuous Current (Audio Switches) . . . . . . . . . . . . . . . . . ±150mA Peak Current (Audio Switches) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±300mA Continuous Current (USB Switches) . . . . . . . . . . . . . . . . . . . ±40mA Peak Current (USB Switches) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA ESD Rating: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>7kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>450V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV Thermal Resistance (Typical, Notes 5, 6) θJA (°C/W) θJC (°C/W) 10 Ld µTQFN Package . . . . . . . . . . . . 130 48.3 10 Ld 3x3 TDFN Package . . . . . . . . . . 110 20 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. 4. Signals on D+, D-, L, R, COM-, COM+, CTRL, VBUS exceeding VDD or GND by specified amount are clamped. Limit current to maximum current ratings. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VBUSH = 3.8V, VBUSL = 3.2V, VCTRLH = 1.4V, VCTRLL = 0.5V, (Notes 7, 8), unless otherwise specified. PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 9) TYP MAX (Note 9) UNITS ANALOG SWITCH CHARACTERISTICS AUDIO SWITCHES (L, R) Analog Signal Range, VANALOG VDD = 3.0V, VBUS = float, CTRL = 1.4V Full -1.5 - 1.5 V ON-Resistance, rON VDD = 3.0V, VBUS = float, CTRL = 1.4V, ICOMx = 100mA, VL or VR = -0.85V to 0.85V (See Figure 3) +25 - 2.65 4 Ω Full - - 5.5 Ω rON Matching Between Channels, ΔrON VDD = 3.0V, VBUS = float, CTRL = 1.4V, ICOMx = 100mA, VL or VR = Voltage at max rON over signal range of -0.85V to 0.85V (Note 11) +25 - 0.02 0.13 Ω Full - - 0.16 Ω rON Flatness, rFLAT(ON) VDD = 3.0V, VBUS = float, CTRL = 1.4V, ICOMx = 100mA, VL or VR = -0.85V to 0.85V (Note 10) +25 - 0.03 0.05 Ω Full - - 0.07 Ω VDD = 3.6V, VBUS = float, CTRL = 1.4V, VCOM- or VCOM+ = -0.85V, 0.85V, VL or VR = -0.85V, 0.85V, VD+ and VD- = floating, Measure current through the discharge pull-down resistor and calculate resistance value. +25 - 50 - kΩ Analog Signal Range, VANALOG VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V Full 0 - VDD V ON-Resistance, rON VDD = 3.3V, VBUS = 4.4V, CTRL = 3.3V, ICOMx = 1mA, VD+ or VD- = 3.3V (See Figure 4) +25 - 23.5 30 Ω Full - - 35 Ω VDD = 3.6V, VBUS = 4.4V, CTRL = 0V or 3.6V, ICOMx = 40mA, VD+ or VD- = 0V to 400mV (See Figure 4) +25 - 4.6 5 Ω Full - - 6.5 Ω Discharge Pull-Down Resistance, RL, RR USB SWITCHES (D+, D-) ON-Resistance, rON 4 FN6557.0 September 25, 2007 ISL54205B Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VBUSH = 3.8V, VBUSL = 3.2V, VCTRLH = 1.4V, VCTRLL = 0.5V, (Notes 7, 8), unless otherwise specified. (Continued) PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 9) TYP MAX (Note 9) UNITS rON Matching Between Channels, ΔrON VDD = 3.6V, VBUS = 4.4V, CTRL = 0V or 3.6V, ICOMx = 40mA, VD+ or VD- = Voltage at max rON, (Note 11) +25 - 0.06 0.5 Ω Full - - 0.55 Ω rON Flatness, RFLAT(ON) VDD = 3.6V, VBUS = 4.4V, CTRL = 0V or 3.6V, ICOMx = 40mA, VD+ or VD- = 0V to 400mV, (Note 10) +25 - 0.4 0.6 Ω Full - - 1.0 Ω OFF Leakage Current, ID+(OFF) or ID-(OFF) VDD = 3.6V, VBUS = 0V, CTRL = 3.6V, VCOM- or VCOM+ = 0.5V, 0V, VD+ or VD- = 0V, 0.5V, VL and VR = float +25 -10 - 10 nA Full -70 - 70 nA ON Leakage Current, IDx VDD = 3.3V, VBUS = 5.25V, CTRL = 0V or 3.6V, VD+ or VD- = 2.0V, VCOM-, VCOM+, VL and VR = float +25 -10 2 10 nA Full -75 - 75 nA Turn-ON Time, tON VDD = 2.7V, RL = 50Ω, CL = 10pF (See Figure 1) +25 - 67 - ns Turn-OFF Time, tOFF VDD = 2.7V, RL = 50Ω, CL = 10pF (See Figure 1) +25 - 48 - ns Break-Before-Make Time Delay, tD VDD = 2.7V, RL = 50Ω, CL = 10pF (See Figure 2) +25 - 18 - ns Skew, tSKEW VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V, RL = 45Ω, CL = 10pF, tR = tF = 720ps at 480Mbps, (Duty Cycle = 50%) (See Figure 7) +25 - 50 - ps Total Jitter, tJ VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V, RL = 50Ω, CL = 10pF, tR = tF = 750ps at 480Mbps +25 - 210 - ps Propagation Delay, tPD VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V, RL = 45Ω, CL = 10pF (See Figure 7) +25 - 250 - ps Crosstalk (Channel-to-Channel), R to COM-, L to COM+ VDD = 3.0V, VBUS = float, CTRL = 3.0V, RL = 32Ω, f = 20Hz to 20kHz, VR or VL = 0.707VRMS (2VP-P) (See Figure 6) +25 - -110 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VDD = 3.0V, VBUS = float, CTRL = 3.0V, VL or VR = 0.707VRMS (2VP-P), RL = 32Ω +25 - 0.06 - % USB Switch -3dB Bandwidth Signal = 0dBm, 0.2VDC offset, RL = 50Ω, CL = 5pF +25 - 630 - MHz D+/D- OFF Capacitance, CD+(OFF), f = 1MHz, VDD = 3.0V, VBUS = float, CTRL = 3.0V, CD-(OFF) VD- or VD+ = VCOMx = 0V (See Figure 5) +25 - 6 - pF L/R OFF Capacitance, CLOFF, CROFF f = 1MHz, VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V, VL or VR = VCOMx = 0V (See Figure 5) +25 - 9 - pF COM ON Capacitance, CCOM-(ON), f = 1MHz, VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V, CCOM+(ON) VD- or VD+ = VCOMx = 0V, (See Figure 5) +25 - 10 - pF Full 2.7 - 3.6 V +25 - 6 8 µA Full - - 10 µA +25 - 1 7 nA Full - - 140 nA DYNAMIC CHARACTERISTICS POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD VDD = 3.6V, VBUS = float or 5.25V, CTRL = 1.4V Positive Supply Current, IDD (Low Power State) VDD = 3.6V, VBUS = 0V or float, CTRL = 0V or float DIGITAL INPUT CHARACTERISTICS VBUS Voltage Low, VBUSL VDD = 2.7V to 3.6V Full - - VDD + 0.2 V VBUS Voltage High, VBUSH VDD = 2.7V to 3.6V Full VDD + 0.8 - - V CTRL Voltage Low, VCTRLL VDD = 2.7V to 3.6V Full - - 0.5 V 5 FN6557.0 September 25, 2007 ISL54205B Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VBUSH = 3.8V, VBUSL = 3.2V, VCTRLH = 1.4V, VCTRLL = 0.5V, (Notes 7, 8), unless otherwise specified. (Continued) PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 9) TYP MAX (Note 9) UNITS CTRL Voltage High, VCTRLH VDD = 2.7V to 3.6V Full 1.4 - - V Input Current, IBUSL, ICTRLL VDD = 3.6V, VBUS = 0V or float, CTRL = 0V or float Full -50 20 50 nA Input Current, IBUSH VDD = 3.6V, VBUS = 5.25V, CTRL = 0V or float Full -2 1.1 2 µA Input Current, ICTRLH VDD = 3.6V, VBUS = 0V or float, CTRL = 3.6V Full -2 1.1 -2 µA VBUS Pull-Down Resistor, RVBUS VDD = 3.6V, VBUS = 5.25V, CTRL = 0V or float Full - 4 - MΩ CTRL Pull-Down Resistor, RCTRL VDD = 3.6V, VBUS = 0V or float, CTRL = 3.6V Full - 4 - MΩ NOTES: 7. VLOGIC = Input voltage to perform proper function. 8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 9. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. 10. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range. 11. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between L and R or between D+ and D-. Test Circuits and Waveforms VBUSH LOGIC INPUT VBUSL tr < 20ns tf < 20ns 50% VDD CTRL tOFF SWITCH V INPUT INPUT VINPUT SWITCH INPUT VOUT 90% SWITCH OUTPUT C VOUT AUDIO OR USB COMX VBUS 90% VBUS RL 50Ω GND 0V CL 10pF tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray RL capacitance. --------------------------V OUT = V (INPUT) R + r L FIGURE 1A. MEASUREMENT POINTS ( ON ) FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES 6 FN6557.0 September 25, 2007 ISL54205B Test Circuits and Waveforms (Continued) VDD C CTRL D- OR D+ VBUSH VINPUT LOGIC INPUT VOUT COMx L OR R VBUSL RL 50Ω VBUS GND VBUS VOUT CL 10pF 90% SWITCH OUTPUT 0V tD Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2B. TEST CIRCUIT FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME VDD VDD C rON = V1/100mA C rON = V1/40mA CTRL CTRL D- OR D+ L OR R VD- or D+ VL OR R VBUS V1 100mA 0V OR FLOAT 40mA COMX GND Repeat test for all switches. VBUS 4.4V TO 5.25V V1 COMx GND Repeat test for all switches. FIGURE 3. AUDIO rON TEST CIRCUIT 7 FIGURE 4. USB rON TEST CIRCUIT FN6557.0 September 25, 2007 ISL54205B Test Circuits and Waveforms (Continued) VDD VDD C C CTRL CTRL SIGNAL GENERATOR AUDIO OR USB L OR R VBUS IMPEDANCE ANALYZER VBUS 0V OR FLOAT VBUSL OR VBUSH COMx GND 32Ω COMx R OR L COMx ANALYZER NC GND RL Repeat test for all switches. Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 6. AUDIO CROSSTALK TEST CIRCUIT FIGURE 5. CAPACITANCE TEST CIRCUIT VDD tri C 90% DIN+ 10% 50% CTRL tskew_i VBUSH VBUS DIN90% 50% 15.8Ω 10% DIN+ COM+ 143Ω tfi tro 15.8Ω DIN90% 10% CL COM- OUT- DCL 143Ω 45Ω 45Ω 50% OUT+ OUT- OUT+ D+ tskew_o GND 50% 90% |tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals. 10% tf0 |tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals. |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals. FIGURE 7B. TEST CIRCUIT FIGURE 7A. MEASUREMENT POINTS FIGURE 7. SKEW TEST 8 FN6557.0 September 25, 2007 ISL54205B Application Block Diagram VDD VBUS µCONTROLLER ISL54205B CTRL USB/HEADPHONE JACK LOGIC CIRCUITRY 22kΩ 4MΩ 4MΩ DCOM D+ 50kΩ COM + USB HIGH-SPEED TRANSCEIVER L R CODEC 50kΩ GND Detailed Description Audio Switches The ISL54205B device is a dual single pole/double throw (SPDT) analog switch device that operates from a single DC power supply in the range of 2.7V to 3.6V. It was designed to function as a dual 2 to 1 multiplexer to select between USB differential data signals and audio L and R stereo signals. It comes in tiny µTQFN and TDFN packages for use in MP3 players, PDAs, cell phones, and other personal media players. The two audio switches (L, R) are 3Ω switches that can pass signals that swing below ground. Crosstalk between the audio switches over the audio band is <-110dB. The part consists of two 3Ω audio switches and two 5Ω USB switches. The audio switches can accept signals that swing below ground. They were designed to pass audio left and right stereo signals, that are ground referenced, with minimal distortion. The USB switches were designed to pass high-speed USB differential data signals with minimal edge and phase distortion. The ISL54205B was specifically designed for MP3 players, cell phones and other personal media player applications that need to combine the audio headphone jack and the USB data connector into a single shared connector, thereby saving space and component cost. See “Application Block Diagram” on page 9. The ISL54205B incorporates circuitry for the detection of the USB VBUS voltage, which is used to switch between the audio CODEC drivers and USB transceiver of the MP3 player or cell phone. The ISL54205B contains a logic control pin (CTRL) that when driven low while VBUS is low, opens all switches and puts the part into a low power state, drawing typically 1nA of IDD current. A detailed description of the two types of switches is provided in the following sections. The USB transmission and audio playback are intended to be mutually exclusive operations. 9 Over a signal range of ±1V (0.707VRMS) with VDD >2.7V, these switches have an extremely low rON resistance variation. They can pass ground referenced audio signals with very low distortion (<0.06% THD+N) when delivering 15.6mW into a 32Ω headphone speaker load. See Figures 8, 9, 10, and 11 THD+N in the “Typical Performance Curves on page 11. These switches are uni-directional switches. The audio drivers should be connected at the L and R side of the switch (pins 7 and 8) and the speaker loads should be connected at the COM side of the switch (pins 3 and 4). The audio switches are active (turned ON) whenever the VBUS voltage is ≤ to VDD + 0.2V or floating and the CTRL voltage ≥ to 1.4V. Note: Whenever the audio switches are ON the USB transceivers need to be in the high impedance state. USB Switches The two USB switches (D+, D-) are bidirectional switches that can pass rail-to-rail signals. When powered with a 3.6V supply these switches have a nominal r(ON) of 4.6Ω over the signal range of 0V to 400mV with a r(ON) flatness of 0.4Ω. The r(ON) matching between the D+ and D- switches over this signal range is only 0.06Ω ensuring minimal impact by the switches to USB high speed signal transitions. As the signal level increases the r(ON) resistance increases. At signal level of 3.3V the switch resistance is nominally 23Ω. The USB switches were specifically designed to pass USB 2.0 high-speed (480Mbps) differential signals typically in the range of 0V to 400mV. They have low capacitance and high bandwidth to pass the USB high-speed signals with FN6557.0 September 25, 2007 ISL54205B minimum edge and phase distortion to meet USB 2.0 high speed signal quality specifications. See high-speed eye diagram in the “Typical Performance Curves” on page 12, Figure 12. The USB switches can also pass USB full-speed signals (12Mbps) with minimal distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See full-speed eye diagram in the “Typical Performance Curves” on page 13, Figure 13. The maximum signal range for the USB switches is from -1.5V to VDD. The signal voltage at D- and D+ should not be allowed to exceed the VDD voltage rail or go below ground by more than -1.5V. The USB switches are active (turned ON) whenever the VBUS voltage is ≥ to VDD + 0.8V. VBUS is internally pulled low, so when VBUS is floating, the USB switches are OFF. Note: Whenever the USB switches are ON the audio drivers of the CODEC need to be at AC or DC ground or floating to keep from interfering with the data transmission. USB Mode If the VBUS pin = Logic “1” and CTRL pin = Logic “0” or Logic “1,” the part will go into USB mode. In USB mode, the D- and D+ 5Ω switches are ON and the L and R 3Ω audio switches are OFF (high impedance). When a USB cable from a computer or USB hub is connected at the common connector, the voltage at the VBUS pin will be driven to be in the range of 4.4V to 5.25V. The ISL54205B part will go into the USB mode. In USB mode, the computer or USB hub transceiver and the MP3 player or cell phone USB transceiver are connected and digital data will be able to be transmitted back and forth. When the USB cable is disconnected, the ISL54205B automatically turns the D+ and D- switches OFF. Low Power Mode If the VBUS pin = Logic “0” and CTRL pin = Logic “0,” the part will be in the Low Power mode. In the Low Power mode, the audio switches and the USB switches are OFF (high impedance). In this state, the device draws typically 1nA of current. EXTERNAL VBUS SERIES RESISTOR ISL54205B Operation The discussion that follows will discuss using the ISL54205B in the “Application Block Diagram” on page 9. LOGIC CONTROL The state of the ISL54205B device is determined by the voltage at the VBUS pin (pin 2) and the CTRL pin (pin 10). Refer to “Truth Table” on page 2. The VBUS pin and CTRL pin are internally pulled low through 4MΩ resistors to ground and can be left floating. The CTRL control pin is only active when VBUS is logic “0”. Logic Control Voltage Levels: VBUS = Logic “0” (Low) when VBUS ≤ VDD + 0.2V or Floating. VBUS = Logic “1” (High) when VBUS ≥ VDD + 0.8V CTRL = Logic “0” (Low) when ≤ 0.5V or floating. CTRL = Logic “1” (High) when ≥ 1.4V Audio Mode If the VBUS pin = Logic “0” and CTRL pin = Logic “1,” the part will be in the Audio mode. In Audio mode the L (left) and R (right) 3Ω audio switches are ON and the D- and D+ 5Ω switches are OFF (high impedance). In a typical application, VDD will be in the range of 2.7V to 3.6V and will be connected to the battery or LDO of the MP3 player or cell phone. When a headphone is plugged into the common connector, nothing gets connected at the VBUS pin (it is floating) and as long as the CTRL = Logic “1,” the ISL54205B part remains in the audio mode and the audio drivers of the player can drive the headphones and play music. 10 The ISL54205B contains a clamp circuit between VBUS and VDD. Whenever the VBUS voltage is greater than the VDD voltage by more than 2.55V, current will flow through this clamp circuitry into the VDD power supply bus. During normal USB operation, VDD is in the range of 2.7V to 3.6V and VBUS is in the range of 4.4V to 5.25V. The clamp circuit is not active and no current will flow through the clamp into the VDD supply. In a USB application, the situation can exist where the VBUS voltage from the computer could be applied at the VBUS pin before the VDD voltage is up to its normal operating voltage range and current will flow through the clamp into the VDD power supply bus. This current could be quite high when VDD is OFF or at 0V and could potentially damage other components connected in the circuit. In the application circuit, a 22kΩ resistor has been put in series with the VBUS pin to limit the current to a safe level during this situation. It is recommended that a current limiting resistor in the range of 10kΩ to 50kΩ be connected in series with the VBUS pin. It will have minimal impact on the logic level at the VBUS pin during normal USB operation and protect the circuit during the time VBUS is present before VDD is up to its normal operating voltage. Note: No external resistor is required in applications where VBUS will not exceed VDD by more than 2.55V. POWER The power supply connected at VDD (pin 1) provides power to the ISL54205B part. Its voltage should be kept in the range of 2.7V to 3.6V when used in a USB/Audio application to ensure you get proper switching when the VBUS voltage is at its lower limit of 4.4V. FN6557.0 September 25, 2007 ISL54205B Typical Performance Curves TA = +25°C, Unless Otherwise Specified 0.11 0.4 RLOAD = 32Ω VDD = 3V RLOAD = 32Ω VLOAD = 0.707VRMS 0.10 3VP-P 0.3 0.09 THD+N (%) THD+N (%) VDD = 2.6V 0.08 0.07 VDD = 2.7V 0.06 0.05 2VP-P 1VP-P 0 0.04 20 200 2k FREQUENCY (Hz) 20k 20 FIGURE 8. THD+N vs SUPPLY VOLTAGE vs FREQUENCY 200 2k FREQUENCY (Hz) 20k FIGURE 9. THD+N vs SIGNAL LEVELS vs FREQUENCY 0.5 0.5 RLOAD = 32Ω FREQ = 1kHz VDD = 3V 0.4 RLOAD = 32Ω FREQ = 1kHz VDD = 3V 0.4 0.3 THD+N (%) THD+N (%) 2.5VP-P 0.1 VDD = 3.6V VDD = 3V 0.2 0.2 0.3 0.2 0.1 0.1 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE (VP-P) FIGURE 10. THD+N vs OUTPUT VOLTAGE 11 3.5 0 10 20 30 40 50 OUTPUT POWER (mW) FIGURE 11. THD+N vs OUTPUT POWER FN6557.0 September 25, 2007 ISL54205B VOLTAGE SCALE (0.1V/DIV) Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) TIME SCALE (10ns/DIV) FIGURE 12. EYE PATTERN: 480Mbps WITH SWITCH IN THE SIGNAL PATH 12 FN6557.0 September 25, 2007 ISL54205B Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) VOLTAGE SCALE (0.5V/DIV) VDD = 3.3V TIME SCALE (10ns/DIV) FIGURE 13. EYE PATTERN: 12MBps WITH SWITCHES IN THE SIGNAL PATH 13 FN6557.0 September 25, 2007 ISL54205B Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 1 Die Characteristics USB SWITCH 0 SUBSTRATE POTENTIAL (POWERED UP): NORMALIZED GAIN (dB) -1 GND -2 TRANSISTOR COUNT: -3 98 -4 PROCESS: Submicron CMOS RL = 50Ω VIN = 0.2VP-P to 2VP-P 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 14. FREQUENCY RESPONSE 14 FN6557.0 September 25, 2007 ISL54205B Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D 6 INDEX AREA A L10.2.1x1.6A B N 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS E SYMBOL 2X MIN NOMINAL MAX 1 2X 2 0.10 C TOP VIEW C A 0.05 C SEATING PLANE 1 0.45 0.50 0.55 - A1 - - 0.05 - 0.127 REF - b 0.15 0.20 0.25 5 D 2.05 2.10 2.15 - E 1.55 1.60 1.65 - A1 e SIDE VIEW k 0.20 - - L 0.35 0.40 0.45 (DATUM A) PIN #1 ID A A3 0.10 C 4xk 2 NX L 0.50 BSC - NX b e 2 Nd 4 3 Ne 1 3 0 12 - NOTES: 5 BOTTOM VIEW CL (A1) L 5 e SECTION "C-C" TERMINAL TIP C C 4 Rev. 3 6/06 0.10 M C A B 0.05 M C 3 (ND-1) X e - 10 (DATUM B) N-1 - N θ N NX (b) NOTES 0.10 C FOR ODD TERMINAL/SIDE b 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. Same as JEDEC MO-255UABD except: No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm "L" MAX dimension = 0.45 not 0.42mm. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 2.50 1.75 0.05 MIN L 2.00 0.80 0.275 0.10 MIN DETAIL “A” PIN 1 ID 0.50 0.25 LAND PATTERN 10 15 FN6557.0 September 25, 2007 ISL54205B Thin Dual Flat No-Lead Plastic Package (TDFN) L10.3x3A 2X 0.10 C A A 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE D MILLIMETERS 2X 0.10 C B SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - E A3 6 INDEX AREA TOP VIEW B // A C SEATING PLANE 0.08 C b 0.20 0.25 0.30 5, 8 D 2.95 3.0 3.05 - D2 2.25 2.30 2.35 7, 8 E 2.95 3.0 3.05 - E2 1.45 1.50 1.55 7, 8 e 0.50 BSC - k 0.25 - - - L 0.25 0.30 0.35 8 A3 SIDE VIEW D2 (DATUM B) 0.10 C 0.20 REF 7 8 N 10 2 Nd 5 3 Rev. 3 3/06 D2/2 NOTES: 6 INDEX AREA 1 2 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. NX k 3. Nd refers to the number of terminals on D. (DATUM A) 4. All dimensions are in millimeters. Angles are in degrees. E2 E2/2 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 0.10 M C A B 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-229-WEED-3 except for D2 dimensions. CL NX (b) (A1) L1 5 9 L e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6557.0 September 25, 2007