Data Sheet

74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
Rev. 1 — 17 July 2012
Product data sheet
1. General description
The 74HC165-Q100; 74HCT165-Q100 are high-speed Si-gate CMOS devices that
comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky
TTL (LSTTL).
The 74HC165-Q100; 74HCT165-Q100 are 8-bit parallel-load or serial-in shift registers
with complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0  Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Asynchronous 8-bit parallel load
 Synchronous serial input
 Complies with JEDEC standard no. 7A
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Multiple package options
3. Applications
 Parallel-to-serial data conversion
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
4. Ordering information
Table 1.
Ordering information
Type number
Package
74HC165D-Q100
Temperature range Name
Description
Version
40 C to +125 C
SO16
plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5  3.5  0.85 mm
74HCT165D-Q100
74HC165PW-Q100
74HCT165PW-Q100
74HC165BQ-Q100
74HCT165BQ-Q100
SOT763-1
5. Functional diagram
1
SRG8
C2[LOAD]
G1[SHIFT]
15
10
11
12
13
14
3
4
5
6
1
≥1
2
1
C3/
DS
D0
10
D1
11
D2
12
D3
3D
2D
2D
13
D4
14
D5
D6
Q7
D7
Q7
9
3
7
4
5
PL
9
6
CP CE
2
mna985
Fig 1.
Logic symbol
74HC_HCT165_Q100
Product data sheet
7
15
mna986
Fig 2.
IEC logic symbol
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Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
2 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
11 12 13 14 3
4
5
6
D0 D1 D2 D3 D4 D5 D6 D7
1 PL
10 DS
2 CP
15 CE
Q7 9
8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT
Q7 7
mna992
Fig 3.
Functional diagram
6. Pinning information
6.1 Pinning
74HC165-Q100
74HCT165-Q100
PL
terminal 1
index area
16 VCC
74HC165-Q100
74HCT165-Q100
1
16 VCC
CP
2
15 CE
CP
2
15 CE
D4
3
14 D3
D4
3
14 D3
D5
4
13 D2
D5
4
13 D2
D6
5
12 D1
D7
6
Q7
7
6
11 D0
Q7
7
10 DS
GND
8
9
Q7
GND(1)
11 D0
10 DS
9
D7
Q7
12 D1
8
5
GND
D6
1
PL
aaa-003156
Transparent top view
aaa-003155
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO16 and TSSOP16
74HC_HCT165_Q100
Product data sheet
Fig 5.
Pin configuration DHVQFN16
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
3 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
PL
1
asynchronous parallel load input (active LOW)
CP
2
clock input (LOW-to-HIGH edge-triggered)
Q7
7
complementary output from the last stage
GND
8
ground (0 V)
Q7
9
serial output from the last stage
DS
10
serial data input
D0 to D7
11, 12, 13, 14, 3, 4, 5, 6
parallel data inputs (also referred to as Dn)
CE
15
clock enable input (active LOW)
VCC
16
positive supply voltage
7. Functional description
Table 3.
Function table[1]
Operating modes
Inputs
PL
parallel load
serial shift
hold “do nothing”
[1]
Qn registers
CE
CP
DS
D0 to D7 Q0
Outputs
Q1 to Q6 Q7
Q7
L
X
X
X
L
L
L to L
L
H
L
X
X
X
H
H
H to H
H
L
H
L

l
X
L
q0 to q5
q6
q6
H
L

h
X
H
q0 to q5
q6
q6
H

L
l
X
L
q0 to q5
q6
q6
H

L
h
X
H
q0 to q5
q6
q6
H
H
X
X
X
q0
q1 to q6
q7
q7
H
X
H
X
X
q0
q1 to q6
q7
q7
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
 = LOW-to-HIGH clock transition.
74HC_HCT165_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
4 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
inhibit
serial shift
mna993
load
Fig 6.
Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[1]
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1]
IO
output current
0.5 V < VO < VCC + 0.5 V
ICC
IGND
Tstg
storage temperature
Max
Unit
0.5
+7
V
-
20
mA
-
20
mA
-
25
mA
supply current
-
50
mA
ground current
50
-
mA
65
+150
C
-
500
mW
total power dissipation
Ptot
Conditions
Tamb = 40 C to +125 C
Min
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT165_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
5 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC165-Q100
Min
Typ
74HCT165-Q100
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
40
-
+125
40
-
+125
C
t/V
input transition rise and fall rate
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
Min
40 C to +85 C 40 C to +125 C Unit
Typ
Max
Min
Max
Min
Max
74HC165-Q100
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VCC = 2.0 V
1.5
1.2
-
1.5
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
4.2
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
5.9
-
5.9
-
V
IO = 4.0 mA; VCC = 4.5 V 3.98
4.32
-
3.84
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V 5.48
5.81
-
5.34
-
5.2
-
V
VI = VIH or VIL
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
-
0.33
-
0.4
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
-
0.1
-
1
-
1
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
74HC_HCT165_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
6 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
Min
CI
input
capacitance
40 C to +85 C 40 C to +125 C Unit
Typ
Max
Min
Max
Min
Max
-
3.5
-
-
-
-
-
pF
74HCT165-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA
3.98
4.32
-
3.84
-
3.7
-
V
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
-
0.33
-
0.4
V
VOL
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
-
0.1
-
1
-
±1
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
ICC
additional
supply current
per input pin;
VI = VCC  2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
CI
input
capacitance
74HC_HCT165_Q100
Product data sheet
Dn and DS inputs
-
35
126
-
157.5
-
171.5
A
CP CE, and PL inputs
-
65
234
-
292.5
-
318.5
A
-
3.5
-
-
-
-
-
pF
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
7 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
11. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
-
52
165
-
205
-
250
ns
VCC = 4.5 V
-
19
33
-
41
-
50
ns
VCC = 6.0 V
-
15
28
-
35
-
43
ns
VCC = 5.0 V; CL = 15 pF
-
16
-
-
-
-
-
ns
VCC = 2.0 V
-
50
165
-
205
-
250
ns
VCC = 4.5 V
-
18
33
-
41
-
50
ns
VCC = 6.0 V
-
14
28
-
35
-
43
ns
VCC = 5.0 V; CL = 15 pF
-
15
-
-
-
-
-
ns
VCC = 2.0 V
-
36
120
-
150
-
180
ns
VCC = 4.5 V
-
13
24
-
30
-
36
ns
VCC = 6.0 V
-
10
20
-
26
-
31
ns
-
11
-
-
-
-
-
ns
VCC = 2.0 V
-
19
75
-
95
-
110
ns
VCC = 4.5 V
-
7
15
-
19
-
22
ns
VCC = 6.0 V
-
6
13
-
16
-
19
ns
VCC = 2.0 V
80
17
-
100
-
120
-
ns
VCC = 4.5 V
16
6
-
20
-
24
-
ns
VCC = 6.0 V
14
5
-
17
-
20
-
ns
VCC = 2.0 V
80
14
-
100
-
120
-
ns
VCC = 4.5 V
16
5
-
20
-
24
-
ns
VCC = 6.0 V
14
4
-
17
-
20
-
ns
VCC = 2.0 V
100
22
-
125
-
150
-
ns
VCC = 4.5 V
20
8
-
25
-
30
-
ns
VCC = 6.0 V
17
6
-
21
-
26
-
ns
74HC165-Q100
tpd
propagation
delay
[1]
CP or CE to Q7, Q7;
see Figure 7
PL to Q7, Q7; see Figure 8
D7 to Q7, Q7; see Figure 9
VCC = 5.0 V; CL = 15 pF
tt
tW
transition
time
pulse width
Q7, Q7 output; see Figure 7
[2]
CP input HIGH or LOW;
see Figure 7
PL input LOW; see Figure 8
trec
recovery time PL to CP, CE; see Figure 8
74HC_HCT165_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
8 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
tsu
set-up time
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
80
11
-
100
-
120
-
ns
VCC = 4.5 V
16
4
-
20
-
24
-
ns
VCC = 6.0 V
14
3
-
17
-
20
-
ns
VCC = 2.0 V
80
17
-
100
-
120
-
ns
VCC = 4.5 V
16
6
-
20
-
24
-
ns
VCC = 6.0 V
14
5
-
17
-
20
-
ns
VCC = 2.0 V
80
22
-
100
-
120
-
ns
VCC = 4.5 V
16
8
-
20
-
24
-
ns
VCC = 6.0 V
14
6
-
17
-
20
-
ns
VCC = 2.0 V
5
6
-
5
-
5
-
ns
VCC = 4.5 V
5
2
-
5
-
5
-
ns
VCC = 6.0 V
5
2
-
5
-
5
-
ns
VCC = 2.0 V
5
17
-
5
-
5
-
ns
VCC = 4.5 V
5
6
-
5
-
5
-
ns
VCC = 6.0 V
5
5
-
5
-
5
-
ns
VCC = 2.0 V
6
17
-
5
-
4
-
MHz
VCC = 4.5 V
30
51
-
24
-
20
-
MHz
VCC = 6.0 V
35
61
-
28
-
24
-
MHz
-
56
-
-
-
-
-
MHz
-
35
-
-
-
-
-
pF
DS to CP, CE; see Figure 10
CE to CP and CP to CE;
see Figure 10
Dn to PL; see Figure 11
th
hold time
DS to CP, CE and Dn to PL;
see Figure 10
CE to CP and CP to CE;
see Figure 10
fmax
maximum
frequency
CP input; see Figure 7
VCC = 5.0 V; CL = 15 pF
CPD
power
dissipation
capacitance
74HC_HCT165_Q100
Product data sheet
per package;
VI = GND to VCC
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
9 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ
Max
Min
Max
Min
Max
VCC = 4.5 V
-
17
34
-
43
-
51
ns
VCC = 5.0 V; CL = 15 pF
-
14
-
-
-
-
-
ns
VCC = 4.5 V
-
20
40
-
50
-
60
ns
VCC = 5.0 V; CL = 15 pF
-
17
-
-
-
-
-
ns
74HCT165-Q100
tpd
propagation
delay
[1]
CE, CP to Q7, Q7;
see Figure 7
PL to Q7, Q7; see Figure 8
D7 to Q7, Q7; see Figure 9
tt
tW
VCC = 4.5 V
-
14
28
-
35
-
42
ns
VCC = 5.0 V; CL = 15 pF
-
11
-
-
-
-
-
ns
-
7
15
-
19
-
22
ns
16
6
-
20
-
24
-
ns
20
9
-
25
-
30
-
ns
20
8
-
25
-
30
-
ns
20
2
-
25
-
30
-
ns
20
7
-
25
-
30
-
ns
20
10
-
25
-
30
-
ns
7
1
-
9
-
11
-
ns
0
7
-
0
-
0
-
ns
VCC = 4.5 V
26
44
-
21
-
17
-
MHz
VCC = 5.0 V; CL = 15 pF
-
48
-
-
-
-
-
MHz
transition
time
Q7, Q7 output; see Figure 7
pulse width
CP input; see Figure 7
VCC = 4.5 V
VCC = 4.5 V
[2]
PL input; see Figure 8
VCC = 4.5 V
trec
recovery time PL to CP, CE; see Figure 8
VCC = 4.5 V
tsu
set-up time
DS to CP, CE; see Figure 10
VCC = 4.5 V
CE to CP and CP to CE;
see Figure 10
VCC = 4.5 V
Dn to PL; see Figure 11
VCC = 4.5 V
th
hold time
DS to CP, CE and Dn to PL;
see Figure 10
VCC = 4.5 V
CE to CP and CP to CE;
see Figure 10
VCC = 4.5 V
fmax
maximum
frequency
74HC_HCT165_Q100
Product data sheet
CP input; see Figure 7
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Rev. 1 — 17 July 2012
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74HC165-Q100; 74HCT165-Q100
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8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
CPD
power
dissipation
capacitance
per package;
VI = GND to VCC  1.5 V
[1]
tpd is the same as tPHL and tPLH.
[2]
tt is the same as tTHL and tTLH.
[3]
25 C
Conditions
[3]
40 C to +85 C 40 C to +125 C Unit
Min Typ
Max
-
-
35
Min
-
Max
-
Min
-
Max
-
pF
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
 (CL  VCC2  fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
12. Waveforms
1/fmax
VI
CP or CE input
VM
GND
tW
tPLH
tPHL
VOH
90 %
90 %
VM
Q7 or Q7 output
VOL
10 %
tTHL
10 %
tTLH
mna987
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7.
Clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width, maximum
clock frequency and output transition times
74HC_HCT165_Q100
Product data sheet
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74HC165-Q100; 74HCT165-Q100
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8-bit parallel-in/serial out shift register
VI
VM
PL input
GND
tW
trec
VI
CE, CP input
VM
GND
tPHL
VOH
VM
Q7 or Q7 output
VOL
mna988
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8.
Parallel load (PL) pulse width, parallel load to output (Q7 or Q7) propagation delays, parallel load to clock
(CP) and clock enable (CE) recovery time
VI
VM
D7 input
GND
tPLH
tPHL
VOH
VM
Q7 output
VOL
tPLH
tPHL
VOH
VM
Q7 output
VOL
mna989
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9.
Data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW
74HC_HCT165_Q100
Product data sheet
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74HC165-Q100; 74HCT165-Q100
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8-bit parallel-in/serial out shift register
(1)
VI
VM
CP, CE input
GND
th
th
tsu
tsu
VI
VM
DS input
GND
tsu
tW
VI
VM
CP, CE input
GND
mna990
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
(1) CE may change only from HIGH-to-LOW while CP is LOW, see Section 1.
Fig 10. Waveforms showing set-up and hold times
VI
Dn input
VM
VM
GND
tsu
th
tsu
th
VI
PL input
VM
VM
mna991
GND
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
Table 8.
Measurement points
Type
Input
Output
VI
VM
VM
74HC165-Q100
VCC
0.5VCC
0.5VCC
74HCT165-Q100
3V
1.3 V
1.3 V
74HC_HCT165_Q100
Product data sheet
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Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
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74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VCC
VCC
G
VI
VO
RL
S1
open
DUT
CL
RT
001aad983
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 12. Test circuit for measuring switching times
Table 9.
Test data
Type
Input
VI
tr, tf
CL
RL
tPHL, tPLH
74HC165-Q100
VCC
6 ns
15 pF, 50 pF
1 k
open
74HCT165-Q100
3V
6 ns
15 pF, 50 pF
1 k
open
74HC_HCT165_Q100
Product data sheet
Load
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
S1 position
© NXP B.V. 2012. All rights reserved.
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74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 13. Package outline SOT109-1 (SO16)
74HC_HCT165_Q100
Product data sheet
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Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
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74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 14. Package outline SOT403-1 (TSSOP16)
74HC_HCT165_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
16 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT763-1
16 terminals; body 2.5 x 3.5 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
7
y
y1 C
v M C A B
w M C
b
L
1
8
Eh
e
16
9
15
10
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT763-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 15. Package outline SOT763-1 (DHVQFN16)
74HC_HCT165_Q100
Product data sheet
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Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
17 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
14. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
MIL
Military
15. Revision history
Table 11.
Revision history
Document ID
Release date
74HC_HCT165_Q100 v.1 20120717
74HC_HCT165_Q100
Product data sheet
Data sheet status
Change notice
Supersedes
Product data sheet
-
-
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Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
18 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT165_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
19 of 21
NXP Semiconductors
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74HC_HCT165_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 July 2012
© NXP B.V. 2012. All rights reserved.
20 of 21
NXP Semiconductors
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 17 July 2012
Document identifier: 74HC_HCT165_Q100