Data Sheet

74LV165A-Q100
8-bit parallel-in/serial-out shift register
Rev. 3 — 28 March 2014
Product data sheet
1. General description
The 74LV165A-Q100 is an 8-bit parallel-load or serial-in shift register with complementary
serial outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL)
is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously.
When input PL is HIGH, data enters the register serially at the input DS. It shifts one place
to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the
succeeding stage. The clock input is a gate-OR structure which allows one input to be
used as an active LOW clock enable input (CE) input. The pin assignment for the inputs
CP and CE is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH
transition of the input CE should only take place while CP HIGH for predictable operation.
Schmitt-trigger action at all inputs, makes the circuit tolerant for slower input rise and fall
times. It is fully specified for partial-power-down applications using IOFF. The IOFF circuitry
disables the output, preventing the damaging current backflow through the device when it
is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 3)
 Specified from 40 C to +85 C
 Wide supply voltage range from 2.0 V to 5.5 V
 Synchronous parallel-to-serial applications
 Synchronous serial input for easy expansion
 Latch-up performance exceeds 250 mA
 CMOS LOW power consumption
 5.5 V tolerant inputs/outputs
 Direct interface with TTL levels (2.7 V to 3.6 V)
 Power-down mode
 Complies with JEDEC standards:
 JESD8-5 (2.3 V to 2.7 V)
 JESD8B/JESD36 (2.7 V to 3.6 V)
 JESD8-1A (4.5 V to 5.5 V)
 ESD protection:
 MIL-STD-833, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LV165AD-Q100
40 C to +85 C
SO16
plastic small outline package; 16 leads; body width SOT109-1
3.9 mm
74LV165APW-Q100
40 C to +85 C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
4. Functional diagram
65*
&>/2$'@
*>6+,)7@
•
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4
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4
3/
&3 &(
PQD
Fig 1.
&
'6
DDD
Logic symbol
Fig 2.
IEC logic symbol
' ' ' ' ' ' ' '
3/
'6
&3
&(
4 %,76+,)75(*,67(5
3$5$//(/,16(5,$/287
4 DDD
Fig 3.
Functional diagram
74LV165A_Q100
Product data sheet
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Rev. 3 — 28 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 19
74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
'
'
'
'
'
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'
'6
&3
'
&(
6'
4
'
6'
4
'
6'
4
'
6'
4
'
6'
4
'
6'
4
'
6'
4
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6'
&3
))
&3
))
&3
))
&3
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&3
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&3
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&3
))
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))
5'
5'
5'
5'
5'
5'
5'
5'
4
4
4
4
3/
DDD
Fig 4.
Logic diagram
74LV165A_Q100
Product data sheet
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Rev. 3 — 28 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
5. Pinning information
5.1 Pinning
/9$4
3/
9&&
&3
&(
'
'
'
'
'
'
'
'
4
'6
*1'
4
DDD
Fig 5.
Pin configuration (SO16 and TSSOP16)
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
PL
1
parallel enable input (active LOW)
CP
2
clock input (LOW-to-HIGH edge-triggered)
Q7
7
complementary serial output from the last stage
GND
8
ground (0 V)
Q7
9
serial output from the last stage
DS
10
serial data input
D0 to D7
11, 12, 13, 14, 3, 4, 5, 6
parallel data inputs
CE
15
clock enable input (active LOW)
VCC
16
positive supply voltage
74LV165A_Q100
Product data sheet
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Rev. 3 — 28 March 2014
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
6. Functional description
Function table[1]
Table 3.
Operating modes
parallel load
serial shift
hold “do nothing”
[1]
Inputs
Qn registers
Output
PL
CE
CP
DS
D0 to D7
Q0
Q1 to Q6
Q7
Q7
L
X
X
X
L
L
L to L
L
H
L
X
X
X
H
H
H to H
H
L
H
L

l
X
L
q0 to q5
q6
q6
H
L

h
X
H
q0 to q5
q6
q6
H

L
l
X
L
q0 to q5
q6
q6
H

L
h
X
H
q0 to q5
q6
q6
H
H
X
X
X
q0
q1 to q6
q7
q7
H
X
H
X
X
q0
q1 to q6
q7
q7
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
 = LOW-to-HIGH clock transition.
&3
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'6
3/
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'
'
4
4
LQKLELW
VHULDOVKLIW
PQD
ORDG
Fig 6.
Timing diagram
74LV165A_Q100
Product data sheet
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Rev. 3 — 28 March 2014
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)[1]
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
VO
output voltage
IO
output current
ICC
Conditions
VI < 0 V
VO > VCC or VO < 0
Min
Max
Unit
0.5
+7
V
-
20
mA
0.5
+7
V
-
50
mA
0.5
VCC + 0.5
V
power-down mode
0.5
+7
V
0 V < VO < VCC
-
25
mA
supply current
-
+50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
Tamb = 40 C to +85 C
SO16 package
[2]
-
500
mW
TSSOP16 package
[3]
-
500
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Ptot derates linearly with 8 mW/K above 70 C.
[3]
Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
Parameter
Min
Typ
Max
Unit
VCC
supply voltage
Conditions
2.0
-
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
t/V
input transition rise and fall rate
74LV165A_Q100
Product data sheet
40
-
+85
C
VCC = 2.3 V to 2.7 V
0
-
200
ns/V
VCC = 3.0 V to 3.6 V
0
-
100
ns/V
VCC = 4.5 V to 5.5 V
0
-
20
ns/V
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 40 C to +85 C
Conditions
Min
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
Typ
Unit
Max
VCC = 2.0 V
1.5
-
-
V
VCC = 2.3 V to 2.7 V
0.7VCC
-
-
V
VCC = 3.0 V to 3.6 V
0.7VCC
-
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 2.3 V to 2.7 V
-
-
0.3VCC
V
VCC = 3.0 V to 3.6 V
-
-
0.3VCC
V
VCC = 4.5 V to 5.5 V
-
-
0.3VCC
V
IO = 50 A; VCC = 2.0 V to 5.5 V
VCC  0.1
-
-
V
IO = 2.0 mA; VCC = 2.3 V
2.0
-
-
V
IO = 6.0 mA; VCC = 3.0 V
2.48
-
-
V
IO = 12 mA; VCC = 4.5 V
3.8
-
-
V
IO = 50 A; VCC = 2.0 V to 5.5 V
-
-
0.10
V
IO = 2.0 mA; VCC = 2.3 V
-
-
0.40
V
HIGH-level output voltage VI = VIH or VIL
LOW-level output voltage
VI = VIH or VIL
IO = 6.0 mA; VCC = 3.0 V
-
-
0.44
V
IO = 12 mA; VCC = 4.5 V
-
-
0.55
V
VI = VCC or GND; VCC = 5.5 V
-
0.01
1
A
-
0.05
5
A
II
input leakage current
IOFF
power-off leakage current VI or VO = 5.5 V; VCC = 0.0 V
ICC
supply current
CI
input capacitance
74LV165A_Q100
Product data sheet
VI = VCC or GND; IO = 0 A; VCC = 5.5 V
-
0.2
20
A
-
3.0
-
pF
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Rev. 3 — 28 March 2014
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); for test circuit, see Figure 12
Symbol Parameter
Tamb = 40 C to +85 C
Conditions
Typ[1]
Min
tpd
propagation
delay
CE, CP to Q7, Q7; CL = 15 pF; see Figure 7
and Figure 8
Unit
Max
[2]
VCC = 2.3 V to 2.7 V
[3]
1.0
11.0
22.0
ns
VCC = 3.0 V to 3.6 V
[4]
1.0
7.5
18.0
ns
VCC = 4.5 V to 5.5 V
[5]
1.0
5.5
11.5
ns
VCC = 2.3 V to 2.7 V
[3]
1.0
11.5
23.5
ns
VCC = 3.0 V to 3.6 V
[4]
1.0
8.0
18.5
ns
VCC = 4.5 V to 5.5 V
[5]
1.0
5.5
11.5
ns
VCC = 2.3 V to 2.7 V
[3]
1.0
12.0
24.0
ns
VCC = 3.0 V to 3.6 V
[4]
1.0
8.5
16.5
ns
VCC = 4.5 V to 5.5 V
[5]
1.0
6.0
10.5
ns
VCC = 2.3 V to 2.7 V
[3]
1.0
13.0
26.0
ns
VCC = 3.0 V to 3.6 V
[4]
1.0
9.0
21.5
ns
VCC = 4.5 V to 5.5 V
[5]
1.0
6.1
13.5
ns
VCC = 2.3 V to 2.7 V
[3]
1.0
14.0
28.0
ns
VCC = 3.0 V to 3.6 V
[4]
1.0
10.0
22.0
ns
VCC = 4.5 V to 5.5 V
[5]
1.0
6.5
13.5
ns
VCC = 2.3 V to 2.7 V
[3]
1.0
14.0
28.0
ns
VCC = 3.0 V to 3.6 V
[4]
1.0
10.0
20
ns
VCC = 4.5 V to 5.5 V
[5]
1.0
6.5
12.5
ns
VCC = 2.3 V to 2.7 V
[3]
9.0
-
-
ns
VCC = 3.0 V to 3.6 V
[4]
7.0
-
-
ns
VCC = 4.5 V to 5.5 V
[5]
4.0
-
-
ns
VCC = 2.3 V to 2.7 V
[3]
13.0
-
-
ns
VCC = 3.0 V to 3.6 V
[4]
9.0
-
-
ns
VCC = 4.5 V to 5.5 V
[5]
6.0
-
-
ns
VCC = 2.3 V to 2.7 V
[3]
8.5
-
-
ns
VCC = 3.0 V to 3.6 V
[4]
6.0
-
-
ns
VCC = 4.5 V to 5.5 V
[5]
4.0
-
-
ns
PL to Q7, Q7; CL = 15 pF; see Figure 8
D7 to Q7, Q7; CL = 15 pF; see Figure 9
CE, CP to Q7, Q7; see Figure 7 and Figure 8
PL to Q7, Q7; see Figure 8
D7 to Q7, Q7; see Figure 9
tW
pulse width
CP input HIGH to LOW; see Figure 7
PL input LOW; see Figure 8
trec
recovery time
74LV165A_Q100
Product data sheet
PL to CP, CE; see Figure 8
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure 12
Symbol Parameter
Tamb = 40 C to +85 C
Conditions
Typ[1]
Min
tsu
set-up time
Unit
Max
DS to CP, CE; see Figure 10
VCC = 2.3 V to 2.7 V
[3]
6.0
-
-
ns
VCC = 3.0 V to 3.6 V
[4]
4.0
-
-
ns
VCC = 4.5 V to 5.5 V
[5]
7.0
-
-
ns
VCC = 2.3 V to 2.7 V
[3]
7.0
-
-
ns
VCC = 3.0 V to 3.6 V
[4]
5.0
-
-
ns
VCC = 4.5 V to 5.5 V
[5]
3.5
-
-
ns
VCC = 2.3 V to 2.7 V
[3]
12
-
-
ns
VCC = 3.0 V to 3.6 V
[4]
8.5
-
-
ns
VCC = 4.5 V to 5.5 V
[5]
5.0
-
-
ns
VCC = 2.3 V to 2.7 V
[3]
0
-
-
ns
VCC = 3.0 V to 3.6 V
[4]
0
-
-
ns
VCC = 4.5 V to 5.5 V
[5]
0.5
-
-
ns
VCC = 2.3 V to 2.7 V
[3]
0.5
-
-
ns
VCC = 3.0 V to 3.6 V
[4]
0.5
-
-
ns
VCC = 4.5 V to 5.5 V
[5]
1.0
-
-
ns
VCC = 2.3 V to 2.7 V
[3]
45
80
-
MHz
VCC = 3.0 V to 3.6 V
[4]
50
115
-
MHz
VCC = 4.5 V to 5.5 V
[5]
90
165
-
MHz
VCC = 2.3 V to 2.7 V
[3]
35
65
-
MHz
VCC = 3.0 V to 3.6 V
[4]
50
90
-
MHz
VCC = 4.5 V to 5.5 V
[5]
85
125
-
MHz
CE to CP, CP to CE; see Figure 10
D7 to PL; see Figure 11
th
hold time
DS to CP, CE; PL to CP, CE; see Figure 10
Dn to PL; see Figure 11
fmax
maximum
frequency
CP input; CL = 15 pF; see Figure 7
CP input; see Figure 7
74LV165A_Q100
Product data sheet
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Rev. 3 — 28 March 2014
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure 12
Symbol Parameter
Tamb = 40 C to +85 C
Conditions
Min
CPD
power
dissipation
capacitance
[6]
VI = GND to VCC; VCC = 3.3 V
[1]
Typical values are measured at Tamb = 25 °C and nominal VCC.
[2]
tpd is the same as tPHL and tPLH.
[3]
Typical values are measured at VCC = 2.5 V.
[4]
Typical values are measured at VCC = 3.3 V.
-
Typ[1]
24
Unit
Max
-
[5]
Typical values are measured at VCC = 5.0 V.
[6]
CPD is used to determine the dynamic power dissipation PD = CPD  VCC2  fi + (CL  VCC2  fo) (PD in W), where:
pF
fi = input frequency in MHz;
fo = output frequency in MHz;
 (CL  VCC2  fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
IPD[
9,
&3&(LQSXW
90
*1'
W:
W3+/
W3/+
92+
90
4RU4RXWSXW
92/
DDD
Measurement points are given in Table 8.
The changing to output assumes that internal Q6 is opposite state from Q7.
Fig 7.
Clock pulse (CP) and clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width and
maximum clock frequency
74LV165A_Q100
Product data sheet
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Rev. 3 — 28 March 2014
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
9,
90
3/LQSXW
*1'
W:
WUHP
9,
&(&3LQSXW
90
*1'
W3+/
92+
90
4RU4RXWSXW
92/
DDD
Measurement points are given in Table 8.
The changing to output assumes that internal Q6 is opposite state from Q7.
Fig 8.
Parallel load (PL) pulse width, parallel load to output (Q7 or Q7) propagation delays, parallel load to clock
(CP) and clock enable (CE) recovery time
9,
90
'LQSXW
*1'
W3/+
W3+/
92+
90
4RXWSXW
92/
W3/+
W3+/
92+
90
4RXWSXW
92/
DDD
Measurement points are given in Table 8.
The changing to output assumes that internal Q6 is opposite state from Q7.
Fig 9.
Data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW
74LV165A_Q100
Product data sheet
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Rev. 3 — 28 March 2014
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
9,
90
&3&(LQSXW
*1'
WK
WK
WVX/
9,
WVX
VWDEOH
90
'6LQSXW
*1'
WVX
WK
W:
9,
90
&3&(LQSXW
*1'
DDD
Measurement points are given in Table 8.
(1) CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for
predictable output performance.
Fig 10. Set-up and hold times
9,
'QLQSXW
90
90
*1'
WVX
WK
WVX
WK
9,
3/LQSXW
90
90
*1'
DDD
Measurement points are given in Table 8.
Fig 11. Set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
Table 8.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
2.0 V to 5.5 V
0.5VCC
0.5VCC
74LV165A_Q100
Product data sheet
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Rev. 3 — 28 March 2014
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
W:
9,
QHJDWLYH
SXOVH
90
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
90
90
9
W:
9(;7
9&&
*
9,
5/
92
'87
57
5/
&/
DDH
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 12. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
2.0 V to 5.5 V
74LV165A_Q100
Product data sheet
Input
Load
VEXT
VI
tr, tf
CL
RL
tPHL, tPLH
VCC
3.0 ns
50 pF, 15 pF
1 k
open
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 28 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 19
74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
12. Package outline
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74LV165A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 28 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 19
74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
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Fig 14. Package outline SOT403-1 (TSSOP16)
74LV165A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 28 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 19
74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LV165A_Q100 v.3
20140328
Product data sheet
-
74LV165A_Q100 v.2
Modifications:
74LV165A_Q100 v.2
Modifications:
74LV165A_Q100 v.1
74LV165A_Q100
Product data sheet
•
Minimum limit VOH for VCC = 4.5 V corrected from 3.0 V to 3.8 V (errata) in Table 6 “Static
characteristics”
20140219
•
Product data sheet
-
74LV165A_Q100 v.1
-
-
Typo corrected in Table 2 “Pin description”
20131021
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 28 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LV165A_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 28 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
17 of 19
74LV165A-Q100
NXP Semiconductors
8-bit parallel-in/serial-out shift register
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LV165A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 28 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
18 of 19
NXP Semiconductors
74LV165A-Q100
8-bit parallel-in/serial-out shift register
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 28 March 2014
Document identifier: 74LV165A_Q100