74HC166-Q100; 74HCT166-Q100 8-bit parallel-in/serial out shift register Rev. 1 — 25 September 2013 Product data sheet 1. General description The 74HC166-Q100; 74HCT166-Q100 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Synchronous parallel-to-serial applications Synchronous serial input for easy expansion Complies with JEDEC standard no. 7A Input levels: For 74HC166-Q100: CMOS level For 74HCT166-Q100: TTL level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number 74HC166D-Q100 Package Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT166D-Q100 74HC166PW-Q100 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register 4. Functional diagram 15 1 PE DS SRG8 2 6 7 15 9 D0 3 D1 4 D2 5 D3 10 D4 11 D5 12 D6 14 D7 1 2 3 Q7 4 13 ≥1 C1/2 M2 R 2,1D 2,1D 2,1D 5 10 9 MR 11 CP CE 7 6 12 14 13 aaa-008817 aaa-008816 Fig 1. Logic symbol Fig 2. 3 2 D0 15 1 9 7 6 4 D1 5 D2 10 D3 D4 11 D5 IEC logic symbol 12 14 D6 D7 PE DS MR CP CE 8-BIT PARALLEL/SERIAL-IN/ SERIAL-OUT SHIFT REGISTER Q7 13 aaa-008818 Fig 3. Functional diagram 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 2 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx D1 D2 D3 D4 D5 D6 NXP Semiconductors 74HC_HCT166_Q100 Product data sheet D0 D7 PE DS CE S S S S S S S S FF CP 1 FF CP 2 FF CP 3 FF CP 4 FF CP 5 FF CP 6 FF CP 7 CP R RD R RD R RD R RD R RD R RD R RD R RD FF 8 MR Q7 aaa-008819 Logic diagram 3 of 19 © NXP B.V. 2013. All rights reserved. 8-bit parallel-in/serial out shift register Fig 4. 74HC166-Q100; 74HCT166-Q100 Rev. 1 — 25 September 2013 All information provided in this document is subject to legal disclaimers. CP 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register 5. Pinning information 5.1 Pinning +&4 +&74 '6 9&& ' 3( ' ' ' 4 ' ' &( ' &3 ' *1' 05 DDD Fig 5. Pin configuration (SO16 and TSSOP16) 5.2 Pin description Table 2. Pin description Symbol Pin Description DS 1 serial data input D0 to D7 2, 3, 4, 5, 10, 11, 12, 14 parallel data inputs CE 6 clock enable input (active LOW) CP 7 clock input (LOW-to-HIGH edge-triggered) GND 8 ground (0 V) MR 9 asynchronous master reset (active LOW) Q7 13 serial output from the last stage PE 15 parallel enable input (active LOW) VCC 16 positive supply voltage 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 4 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register 6. Functional description Function table[1] Table 3. Operating modes Inputs parallel load serial shift hold “do nothing” [1] Qn registers Output PE CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 I I X I L L to L L I I X h H H to H H h I l X L q0 to q5 q6 h I h X H q0 to q5 q6 X H X X X q0 q1 to q6 q7 H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; = LOW-to-HIGH clock transition. CP mode control inputs CE MR DS shift/ load D0 H L D1 D2 H L D3 parallel inputs D4 H L D5 output D6 H D7 H Q7 H serial shift H L H L H L H serial shift inhibit load clear Fig 6. aaa-008820 Typical clear, shift, load, inhibit, and shift sequences 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 5 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C SO16 package [2] - 500 mW TSSOP16 package [3] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 8 mW/K above 70 C. [3] Ptot derates linearly with 5.5 mW/K above 60 C. 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 6 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC166-Q100 Min Typ 74HCT166-Q100 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 - +125 40 - +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max 74HC166-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL VI = VIH or VIL IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 7 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min CI input capacitance 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT166-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 4.5 V - 0.16 0.26 - 0.33 - 0.4 V VOL II input leakage current VI = VCC or GND; VCC = 4.5 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 4.5 V - - 8.0 - 80 - 160 A ICC additional supply current per input pin; VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V CI input capacitance 74HC_HCT166_Q100 Product data sheet Dn and DS inputs - 35 126 - 157.5 - 171.5 A CP and CE inputs - 80 288 - 360 - 392 A MR input - 40 144 - 180 - 196 A PE input - 60 216 - 270 - 294 A - 3.5 - - - - - pF All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 8 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 50 150 - 190 - 225 ns VCC = 4.5 V - 18 30 - 38 - 45 ns 74HC166-Q100 tpd propagation delay CP to Q7; see Figure 7 [1] VCC = 5.0 V; CL = 15 pF - VCC = 6.0 V 15 - - - - - ns - 14 26 - 33 - 38 ns VCC = 2.0 V - 47 160 - 200 - 240 ns VCC = 4.5 V - 17 32 - 40 - MR to Q7; see Figure 8 VCC = 5.0 V; CL = 15 pF - VCC = 6.0 V tt tW transition time pulse width 14 - - - 48 - ns - ns - 14 27 - 34 - 41 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 100 25 - 125 - 150 - ns VCC = 4.5 V 20 9 - 25 - 30 - ns VCC = 6.0 V 17 7 - 21 - 26 - ns VCC = 2.0 V 0 19 - 0 - 0 - ns VCC = 4.5 V 0 7 - 0 - 0 - ns VCC = 6.0 V 0 6 - 0 - 0 - ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns VCC = 2.0 V 100 33 - 125 - 150 - ns VCC = 4.5 V 20 12 - 25 - 30 - ns VCC = 6.0 V 17 10 - 21 - 26 - ns [2] output; see Figure 7 CP input HIGH or LOW; see Figure 7 MR input LOW; see Figure 8 trec tsu recovery time MR to CP; see Figure 8 set-up time Dn, CE to CP; see Figure 9 PE to CP; see Figure 9 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 9 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register Table 7. Dynamic characteristics …continued GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter 25 C Conditions Min Typ th hold time 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max Dn, CE to CP; see Figure 9 VCC = 2.0 V 2 8 - 2 - 2 - ns VCC = 4.5 V 2 3 - 2 - 2 - ns VCC = 6.0 V 2 2 - 2 - 2 - ns PE to CP; see Figure 9 fmax maximum frequency VCC = 2.0 V 0 28 - 0 - 0 - ns VCC = 4.5 V 0 10 - 0 - 0 - ns VCC = 6.0 V 0 8 - 0 - 0 - ns CP input; see Figure 7 VCC = 2.0 V 6 19 - 4.8 - 4 - MHz VCC = 4.5 V 30 57 - 24 - 20 - MHz VCC = 5.0 V; CL = 15 pF - 63 - - - - - MHz 35 68 - 28 - 24 - MHz - 41 - - - - - pF - 23 40 - 50 - 60 ns VCC = 6.0 V CPD power dissipation capacitance per package; VI = GND to VCC [3] CP to Q7; see Figure 7 [1] 74HCT166-Q100 tpd propagation delay VCC = 4.5 V VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns - ns MR to Q7; see Figure 8 VCC = 4.5 V - VCC = 5.0 V; CL = 15 pF tt tW 22 - 40 19 - - 50 - - 60 - ns [2] transition time output; see Figure 7 pulse width CP input HIGH or LOW; see Figure 7 VCC = 4.5 V VCC = 4.5 V - 7 15 - 19 - 22 ns 20 9 - 25 - 30 - ns 25 11 - 31 - 38 - ns 0 7 - 0 - 0 - ns 16 8 - 20 - 24 - ns 30 15 - 38 - 45 - ns 0 3 - 0 - 0 - ns 0 13 - 0 - 0 - ns MR input LOW; see Figure 8 VCC = 4.5 V trec recovery time MR to CP; see Figure 8 VCC = 4.5 V tsu set-up time Dn, CE to CP; see Figure 9 VCC = 4.5 V PE to CP; see Figure 9 VCC = 4.5 V th hold time Dn, CE to CP; see Figure 9 VCC = 4.5 V PE to CP; see Figure 9 VCC = 4.5 V 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 10 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register Table 7. Dynamic characteristics …continued GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter fmax maximum frequency power dissipation capacitance CPD [1] 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 4.5 V 25 45 - 20 - 17 - MHz VCC = 5.0 V; CL = 15 pF - 50 - - - - - MHz - 41 - - - - - pF CP input; see Figure 7 [3] per package; VI = GND to VCC tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL VCC2 fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 11. Waveforms 1/fmax VI CP input VM GND tW tPHL VOH tPLH 90 % 90 % VM Q7 output 10 % VOL tTHL 10 % tTLH aaa-008821 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Clock (CP) to output (Q7) propagation delays, pulse width, output transition times and maximum frequency 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 11 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register VI VM MR input GND tW trec VI VM CP input GND tPHL VOH VM Q7 output VOL aaa-008822 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Master reset (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time. see note (1) VI CE input VM GND tsu tsu th VI tsu th th VM PE input GND tsu tsu th VI th stable VM Dn input GND tsu th VI stable VM DS input GND tsu th VI tW VM CP input GND condition: MR = HIGH aaa-008823 The shaded areas indicate when the input is permitted to change for predictable output performance Measurement points are given in Table 8. (1) CE may change only from HIGH-to-LOW while CP is LOW Fig 9. Set-up and hold times 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 12 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register Table 8. Measurement points Type Input Output VI VM VM 74HC166-Q100 VCC 0.5VCC 0.5VCC 74HCT166-Q100 3V 1.3 V 1.3 V VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 10. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 10. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC166-Q100 VCC 6 ns 15 pF, 50 pF 1 k open 74HCT166-Q100 3V 6 ns 15 pF, 50 pF 1 k open 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 13 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT109-1 (SO16) 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 14 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 12. Package outline SOT403-1 (TSSOP16) 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 15 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74HC_HCT166_Q100 v.1 20130925 74HC_HCT166_Q100 Product data sheet Data sheet status Change notice Supersedes Product data sheet - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 16 of 19 74HC166-Q100; 74HCT166-Q100 NXP Semiconductors 8-bit parallel-in/serial out shift register 15. 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NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 17 of 19 NXP Semiconductors 74HC166-Q100; 74HCT166-Q100 8-bit parallel-in/serial out shift register No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT166_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 18 of 19 NXP Semiconductors 74HC166-Q100; 74HCT166-Q100 8-bit parallel-in/serial out shift register 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 September 2013 Document identifier: 74HC_HCT166_Q100