5 4 3 2 1 D D A Keystone 2 EVM Board for TI Product name : K2EVM-HK C C Rev. 4.0 TOP L2_GND 0.5 oz+plating 3.06mils 1.0 oz 5mils L3 0.5 oz L4_PWR 1.0 oz L5 0.5 oz L6_GND 1.0 oz 4.83mils 5mils PCB PN : Project Code : 4.83mils 4mils L7_GND L8 PCB Thickness : 63 mils(1.6mm) 12 Layers L10 B BOT DISCLAIMER: THIS CIRCUIT DESIGN IS PROVIDED AS REFERENCE ONLY, WITHOUT WARRANTY EXPRESSED OR IMPLIED. THE USER IS ENCOURAGED TO PERFORM ALL DUE DILIGENCE WITH RESPECT TO DESIGN AND ANALYSIS. FOR COMMITTED PERFORMANCE AND FUNCTIONALITY , PLEASE REFER TO THE DEVICE DATA MANUAL. A p.p core p.p core 4.83mils p.p 0.5 oz core 1.0 oz 4.83mils p.p 0.5 oz B 5mils L11_GND core 1.0 oz 5mils L9_PWR p.p core 0.5 oz 3.06mils 0.5 oz+plating p.p Copyright (C) 2013 Texas Instruments Incorporated. All rights reserved. NOTE: TI Information – Selective Disclosure NOTE: EVM design supports multiple devices. Check your device datasheet to determine if a given functionality is supported. A DSPM-8305E Designed for TI by ADVANTECH Title COVER PAGE Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 1 of 43 5 4 3 2 1 K2EVM-HK Revision Table K2EVM-HK (Rev 104-1 / PCB- 19C2830503-01) Item 1 Description Page Update Blockdiagram for EMIF Feature Page. 05 D D 2 Rserve R812 3 Added Inverter U69 to solve EMIF and NAND 4 Adding SN74LVC1G07 Buffer for USBDRVVBUS net Page. 15 5 Remove C387 for VCC5 feedback compensation optimization Page. 43 6 Adding R815,R816,R817 Pull down resistance for CLK 7 8 9 C 10 for Buffer OE control Change R310 3K to 200ohm for USB Page. 13 read/write issue Page. 19 PDN Page.25,26,27 PHY PVT sense path Page.15 Change R25 1K to 470ohm for EMIFWAIT0 PU Page.19 Change R116,R117,R468 0ohm to 10ohm for PWR Solution Page.40,41 U39 to U43 Page.28, 29 DDR SDRAM Change to Samsung K4B4G1646D-BCK0 C B B A A DSPM-8305E Designed for TI by ADVANTECH Title K2EVM-HK Revision Table I Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 2 of 43 5 4 Item 3 2 Description 1 Page D D C C B B A A DSPM-8305E Designed for TI by ADVANTECH Title K2EVM-HK Revision Table II Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 3 of 43 5 4 3 2 1 TITLE & TABLE OF CONTENTS Page D C Description Page Description D 01 COVER PAGE 31 Connectors for Debug 02 K2EVM-HK Revision Table I 32 GBE Ethernet PHY1 03 K2EVM-HK Revision Table II 33 GBE Ethernet PHY2 04 TITLE & TABLE OF CONTENTS 34 88E1111 (RJ45) 05 BLOCK DIAGRAM_AMC 35 GPS & SIM CARD 06 POWER SEQUENCE 36 MCU_LM3S2D93 07 POWER DISTRIBUTION 37 MCU_MISC 08 CLOCK & TIMER DIAGRAM 38 MCU LCD 09 MCU_BLOCK_ Diagram 39 mTCA_ZD3/120-pin Expansion 10 Intentionally Left Blank 40 Smart-Reflex AVS 11 K2EVM-HK EVM Placement 41 Smart_Reflex 1.8V/1.5V/0.85V 12 AMC GF 42 Power_1.2V/2.5V/0.75V/1.8V 13 SPI to GPIO Converter 43 Power_VCC5 / VCC3_AUX/MP_ALT 14 SOC_SRIO_SGMII_PCIE_MCM 15 SOC_XFI_USB 16 SOC_DDR3A 17 SOC_DDR3B 18 SOC_MISC 19 SOC_JTAG_EMU 20 SOC_AIF 21 SOC CLOCKs & Smart-Reflex VID 22 SOC_POWERA 23 SOC_POWERB 24 SOC_GND 25 CLOCK_GEN1 26 CLOCK_GEN2 27 CLOCK_GEN3 28 DDR3 29 DDR3_ECC 30 DDR3_SODIMM C B B A A DSPM-8305E Designed for TI by ADVANTECH Title TITLE & TABLE OF CONTENTS Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 4 of 43 5 4 3 2 1 Keystone-2 EVM BLOCK DIAGRAM UART0 I2C1 SPI1 I2C SPI to GPIO MCP23S17T Level Shift & ISOLATOR UART1(RX) RST# PJ0 PJ1 WARM RESET (MCU PJ0) FULL RESET (MCU PJ1) Exp Conn A MCU_RESET_SWz MCU_JTAG_RESET# AND NAND_WPz X4 GPIO[16:0] EMIF16(16bit) GPIO[16:0] GPIO[16:0] RX From MCU UART0 BOARDID[0:2] /Presence RX TX RX NOR FLASH 128Mb (CS0) MAX3221 UART K2H SoC TX RX Level Shift & ISOLATOR RX MUX AMC.0 Card-Edge A (5 Gbit/s) XDS200 Mezzanine MUX TI_TS3L301DGG JTAG BUF JTAG Stand-off JTAG Level shift SGMII 0 (x1) SGMII 1 (x1) MDIO 1.25 Gbit/s JTAG MMC 25 MHz (TCLKBP/N) RJ-45 SGMII 2 (x1) I2C 2 1Mb EEPROM To SO-DIMM TIMO0 SGMII 0 (x1) 100 MHz (FCLKAP/N) Timer1(TINI1) MUX AMC.0 TIMI0 TIMO0 From SOC TIMO0/1 TIMO0/TIMO1 TIMI1 GPS Antenna SMA GPS Receiver TIMO1 Sync Event Select Jumper Block PPS output Exp Conn A TSPUSHEVT0 TSPUSHEVT1 TSCOMPOUT TSSYNCEVT LCD DISPLAY RSV_CLK_P/N Accessory IC SYNC DAC8550 From SOC SPI1 (CS0) Rakon 19.2 MHz VCTCXO (SYSCLK) RF Switch MM8030 U0 122.88 Mhz LVDS U3 U1 122.88 Mhz LVDS SYNC U2 122.88 Mhz LVDS SECREF+ REF_SEL CDCM6208 Status From AMC.0 Card Edge TCLKD_P/N 19.2 Mhz SOC I2C From SOC I2C2 AIF2 (x2) microTCA.4 Card-Edge B (12.5 Gbit/s) SYNC-E IEEE1588 SGMIIMDIO 6.144 Gbit/s AIF2 (x4) SYS_CLKP/N TSREFCLKP/N 10.125 Gbit/s XF0 (x1) PASS_CLKP/N U6 XFI0 (x1) 10.125 Gbit/s XF1 (x1) SOC I2C XFI1 (x1) From SOC I2C2 Termination U7 10.125 Gbit/s XFIMDIO PRI_REF+/U4 19.2 Mhz SPI U5 19.2 Mhz U0 156.25 Mhz LVDS SYNC LVDS U1 156.25 Mhz CLK1 To SoC AT Module Signal Selection Block PCI-E (x2) 6.144 Gbit/s AIF2 (x6) RP1_CLKP/N RP1FBP/N RADSYNC PHYSYNC To 4Pin CONN AT Module Sync Signals SRIO (x4) 5 Gbit/s PCI-E (x2) CLOCK MUX SGMII 1 (x1) 5 Gbit/s SRIO (x4) Timer0(TIMI0) To CDCM620x Clock Generator PLL C 1.25 Gbit/s SGMII 3 (x1) AMC.0 BUF To 2Pin CONN microTCA.4 Card-Edge B mTCA.4 mini-USB MUX TIMO1 AMC.0 Card-Edge A To FTDI MAX3221 To CDCM620x Clock Generator PLL 30.72 MHz (TCLKDP/N) 1.25 Gbit/s I2C 1 Exp Conn A To MCU I2C0/GPIO RJ-45 Gigabit Ethernet PHY x2 UART 1 I2C 2 B JTAG 1.25 Gbit/s UART 0 RX/TX MCU Connector EMU[0:33] SPI 1 I2C 0 C EMU[18:0] EMU[33:19] SPI 0 Level Shift & ISOLATOR (CS1~CS3) MUX DDR3-1600 (128/256M x16x5) with ECC (1-2GB) JTAG/EMU SPI 2 RX DDR3B(72bit) From SOC I2C1 EXT_EMU_DET To 4Pin CONN SPI 2 Level Shift &ISOLATOR 204-Pin DDR3 SO-DIMM (1-8GB) with ECC MIPI-60 Header and MUX To Sync DAC8550 (CS0) RX/TX I2C DDR3A(72bit) D From MCU WP (CE1) SPI K2H SoC BUFFER & TRANSCEIVER EMIF16(16bit) LCD Display (128x32) 4Gb NAND FLASH (CE0) EMIFD[7:0] PH[0:3] BM_GPIO(0~3) D Level Shift & ISOLATOR MCU_GPS_ENABLE I2C1 MMC DIP SW SPI MCU LM3S2D93 EEPROM_WP SPI0 TCLKD_P/N GPIO[16:0] From AMC.0 Card Edge XFIMDIO B U.FL 12.5 Gbit/s Hyperlink0 (x4) Hyperlink0 (x4) MCU SPI0 (CS0) 12.5 Gbit/s Hyperlink1 (x4) MCU SPI to GPIO SECREF+ U.FL XFI_CLKP/N U2 PRIREF+/SPI MCU SPI0 (CS1) USB 3.0 CDCM6208 CLK2 From AMC.0 Card Edge TCLKB_P/N RF Switch MM8030 25 Mhz SmartReflex (DSP) U4 U0 312.5 Mhz LVDS SYNC U1 312.5 Mhz LVDS SECREF+/- 125 Mhz LVDS U2 125 Mhz LVDS U3 100 Mhz LVDS U6 LVDS U7 100 Mhz 100 Mhz LVDS SPI CDCM6208 A U.FL HYPER0_LINK_CLKP/N Status CLK3 U4 U5 From AMC.0 Card Edge FCLKA_P/N 100 Mhz PMBUS_CNTRL PMBUS_Alert From MCU GPIO Level Shift & ISOLATOR VID/PMBUS Power Good UCD9244 Smart-Reflex Regulator 0.75V-1.0V Power VID/PMBUS CLK/DATA AL CN UCD9090 Power Sequencing Controller Power ALT_CORE_CLKP/N DDR3A_CLKP/N DDR3B_CLKP/N Fixed Digital and Analog Supplies UCD9244 Smart-Reflex Regulator 0.85V 1.5V 1.8V 3.3V LDO Regulators 0.75V 1.2V 1.8V 2.5V Power Planes And Filters USB_CLKP/N PCIE_CLKP/N CLOCK MUX FPWM5 FAN_PWM 4-PIN FAN Header Power Good Enable PWM[1:2] FPWM[6:8] FPWM4 A FPWM Connector DSPM-8305E Designed for TI by ADVANTECH USIM SOCKET Voltage Translator TSRXCLKOUTP/N0 USIM TSRXCLKOUTP/N1 Exp Conn A +12V Power Jack Title AMC.0 Card Edge uTCA.4 Card Edge BLOCK DIAGRAM_AMC Size 4 3 2 Document Number D Date: 5 Thermal Sensor SOC_TEMP1 MON10 Enable 0.95V Fixed for ARM & DSP ARM_CLKP/N From MCU I2C1 CLK/DATA Power LVDS 100 Mhz 100 Mhz SmartReflex (ARM) HYPER1_LINK_CLKP/N REF_SEL MCU SPI to GPIO PMBUS Connector I2C 10 Mhz PRIREF+/- MCU SPI0 (CS2) PMBUS_Alert U6 U7 Status Fox FXO-LC53 25 MHz XO USB 3.0 Host Connector Termination REF_SEL MCU SPI to GPIO 5 Gbit/s U3 U5 Hyperlink1 (x4) SRIO_SGMII_CLKP/N Rev A104 K2EVM-HK Tuesday, November 04, 2014 1 Sheet 5 of 43 5 4 Power Sequence D C Has not been modify , wait TI provide document. 1 VCC3V3_MP VCC3_LCD MAIN_POWER_START(From MCU) VCC3V3_AUX_EN D VCC3V3_AUX Other VCC3_AUX_MON 5ms VCC1V2_EN 88E1111 VCC1V2 VCC1V2_MON 5ms VCC2V5_EN 88E1111 VCC2V5 VCC2V5_MON 5ms MAIN_POWER_GOOD(To MCU) 5ms SOC_POWER_START(From MCU) PMBUS &UCD9244_EN SOC K2H CVDD SOC K2H CVDD1(0.95V) 5ms SOC K2H CVDDT1(0.95V) CVDD_PWR_OK SOC K2H VDD33 SOC K2H VCC0V85 SOC K2H VCC1V8 DDR3 SOC K2H DDR3 SDRAM Power Sequence 5ms PMBUS &Farm1_UCD_EN C 5ms S23 5ms S24 S25 S26 S27 B VCC3V3_MP_AMC 2 VCC12 S22 S31 S32 S33 S34 S35 S36 VCC3V3_MP_ALT MicroTCA LCD S18 S19 S20 S21 S28 S29 S30 Tabletop MCU S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 3 5ms VCC1V5 UCD_PWR_OK 5ms VCC0V75_EN DDR3 SOC K2H DDR3 Vref VCCA0V75 VCCB0V75 VCCB0V75_MON VCCA0V75_MON 5ms VCC5_EN USB SOC K2H VCC5 VCC5_MON 5ms SOC_POWER_GOOD(To MCU) T=5mS SOC_VPPB_EN(From MCU) SOC K2H VPP1V8 SOC K2H VPP1V8_MON B T=18mS RESET# including peripherals. Reset Sequence T=5mS POR# T=5mS RESETFULL# by SOC chip RESETSTAT# REFCLKP&N by REFCLK1_PD# CLOCK1_PLL_LOCK REFCLKP&N by REFCLK2_PD# CLK Sequence CLOCK2_PLL_LOCK DDRCLKP&N by REFCLK3_PD# VCC3V3_MP 3.3V TI_UCD9090 Ther is no specific power-up nor power-down sequence. MCU_LM3S2D93 VDD33 1.5V (SOC) CLOCK3_PLL_LOCK TI_UCD9090 1.0V_fixed Ther is no specific power-up nor power-down sequence. VCC3V3_MP When power down 1.5V/(DDR3_IO) 0.75V/(DDR3_Vref) VDD33 VCC1V8 VCC1V8 VCC_1V0 Fixed Ther is no specific power-up nor power-down sequence. VDD33 1.5V/(DDR3_IO) 0.75V/(DDR3_Vref) VCC0V85 VCC_1V0 scaled SOC K2H VCC1V0 Scaled/(CVDD) VCC0V95 Fixed/(CVDD1) VCC1V0 Scaled/(CVDDT) VCC0V95 Fixed/(CVDDT1) VCC1V8/ (DVDD18) VCC0V85/ (CVDDS) VDD33/ (USBVDD3V3) 1.5V/(DDR3_IO) 0.75V/(DDR3_Vref) SOC K2H 88E1111 (PHY) Title 88E1111 2.5V 1.2V Power Sequence Size Document Number Custom Date: 5 4 DSPM-8305E Designed for TI by ADVANTECH 2.5V VCC0V85 VCC_1V0 Fixed 1.2V VCC_1V0 scaled VCC0V85 VCC1V8 MCU_LM3S2D94 When power on 0.75V (SOC) A 1.0V_scaled A 3 2 Rev A104 K2EVM-HK Tuesday, November 04, 2014 1 Sheet 6 of 43 5 4 3 2 1 POWER DISTRIBUTION uTCA.4 CONN APL431LBAI-TRG VCC3V3_AUX AMC.0 VCC3_LCD DC 12V Adapter D 3.3V_MP(min=150mA) VCC3V3_MP_AMC D VCC12 VCC3V3_MP Diode OR VCC3V3_MP_ALT VCC3V3_MP_AMC 0.22A TLV1117-33CDCY Note :PMBUS Includ I2C&Alert/CNTRL PMBUS Connector From SoC PMBUS PMBUS Connector SmartReflex PMBUS 1.83 A 1.04A 0.679A VNCTL SmartReflex VCC3V3_MP_ALT Efficiency=90% Efficiency=80% VCC5_PGOOD UCD9244 Farm1_UCD_EN UCD9244 UCD9244_EN Efficiency=90% C VCC3_AUX_PGOOD UCD_PWR_OK VCC_5V_EN Efficiency=90% TPS54620 TPS54620 VCC3V3_AUX_EN_R C CVDD_PWR_OK VCC2V5_PGOOD PWM4 Vsense4 Isense4 Tsense4 PWM3 Vsense3 Isense3 Tsense3 PWM2 Vsense2 Isense2 Tsense2 UCD7242 (10A) (10A) PWM4 Vsense4 Isense4 Tsense4 PWM1 Vsense1 Isense1 Tsense1 UCD74111 (15A) PWM3 Vsense3 Isense3 Tsense3 PWM2 Vsense2 Isense2 Tsense2 UCD7242 (10A) (10A) UCD74106 (6A) PWM1 Vsense1 Isense1 Tsense1 UCD74120 (25A) TPS73701DCQ VCC2P5_EN VCC1V2_PGOOD UCD74120 (25A) TPS73701DCQ VCC1V2_EN SOC_VPPB TPS74701DRCT B VCC0V85 VDD33 For SERDES For USB I/O VCC1V8 VCC1V5 For DDR3 For PLL I/O CVDDD0V95 CVDDA0V95 CVDD For DSP Fixed For ARM Fixed For ARM AVS For DSP AVS PMBUS Connector VCC0V75_PGOOD VCCA0V75_PGOOD TP51200 VCC0V75_EN TP51200 VCC5 CLK/DATA AL UCD9244_EN From MCU GPIO Level Shift & ISOLATOR GPIO2 VCC0V75 GPIO3 VCC3V3_AUX_EN_R VCC2P5_EN MAIN_POWER_GOOD SOC_POWER_GOOD GPIO16 VCC1V2_EN EEPROM * DDR3 A 3.3V 1.5V / 0.6A (VDD)*5 Total:3A 0.75V / 1A (Vref) * DDR3 SODIMM Quad Core SOC RS232 3.3V VCC1V0 / 20A Scaled/(CVDD) VCC1V0 / 6A Scaled/(CVDDT) VCC0V95/ 5A/ (CVDD1) VCC0V95/ 5A/(CVDD1T) 0.85V / 3A Fixed/(USB) VCC1V8 / 1A (DVDD18) 1.5V / 2A (DDR3_IO) 0.75V/0.2A(DDR3_Vref) VCC0V75_EN TI/LM3S2D93 3.3V_AUX/ 0.135A (VDD) V_RTC/ 141uA (VBAT) MAIN_POWER_START NOR FLASH SOC_POWER_START Standyby mode 1.8V/80uA 88E1111 (PHY) 1.5V / 3A (VDD) 4-PIN FAN Header 2.5V / 0.07A *2 Total:0.14A 1.2V / 0.29A *2 Total:58A 0.75V / 1A (Vref) FAN_PWM GPIO15 GPIO17 FPWM1/GPI1 FPWM2/GPI2 VCC3_AUX_MON MON4 UCD9090 Power GPIO14 Sequencing Controller VPP1V8 VCC5_MON MON3 GPIO4 GPIO13 UCD_PWR_MON MON2 VCC_5V_EN VCCAV75 CVDD_PWR_OK MON1 Farm1_UCD_EN For DDR3-1600 SO-DIMM VCC1V2 VCC2V5 From MCU I2C1 CN GPIO1 DDR3-1600 DiscreteSDRAM ArrayI From MCU GPIO B PMBUS_CNTRL PMBUS_Alert PMBUS_I2C VCC0V75_EN VCC3V3_AUX VCC2V5_MON MON5 VCC1V2_MON MON6 MON7 VCCB0V75_MON MON8 VCCA0V75_MON A VPP1V8_MON MON9 SOC_TEMP1 MON10 Thermal Sensor FPWM5 Title PWM[1:2] FPWM[6:8] FPWM4 FPWM Connector POWER DISTRIBUTION Size 4 3 2 Document Number Custom Date: 5 DSPM-8305E Designed for TI by ADVANTECH Rev A104 K2EVM-HK Tuesday, November 04, 2014 1 Sheet 7 of 43 5 4 3 2 1 CLOCK & TIMER DIAGRAM SOC K2H Clocking and Synchronization D ExpConn A U3 RSVCLK_P/N CDCM6208 SYNC SYNC DAC8550 From SOC SPI1 (CS0) From AMC.0 Card Edge Rakon (SYSCLK) 19.2 MHz VCTCXO RF Switch MM8030 19.2 MHz 19.2 Mhz U.FL 122.88 Mhz LVDS U0 122.88 Mhz LVDS U1 122.88 Mhz LVDS U2 CORECLKSEL SECREF+ PRI_REF+/- TCLKD_P/N U4 PACLKSEL SYS_CLKP/N From MCU PLLLOCK TSREFCLKP/N PASS_CLKP/N REF_SEL SYSCLKOUT Status MCU SPI to GPIO D PLL Lock LED U6 COREPLLOBSCLKP/N Termination U7 SPI MCU SPI0 (CS0) DDR3APLLOBSCLKP/N CLK1 U5 19.2 Mhz DDR3BPLLOBSCLKP/N TEST POINT PAPLLOBSCLKP/N C C SYNC U0 CDCM6208 U1 SECREF+ PRIREF+/- LVDS 156.25 Mhz LVDS TETRISPLLCLKP/N SRIO_SGMII_CLKP/N XFI_CLKP/N U2 ARMPLLOBSCLKN ARMPLLOBSCLKP COREPLLOBSCLKN COREPLLOBSCLKP PAPLLOBSCLKN PAPLLOBSCLKP U3 REF_SEL MCU SPI to GPIO U5 Status Termination U6 U7 SPI MCU SPI0 (CS1) U4 CLK2 SYNC B From AMC.0 Card Edge Fox FXO-LC53 25 MHz XO TCLKB_P/N RF Switch MM8030 25 MHz 10 Mhz U.FL SECREF+/- 312.5 Mhz LVDS U0 LVDS U1 312.5 Mhz 125 Mhz LVDS U2 HYPER0_LINK_CLKP/N HYPER1_LINK_CLKP/N Status 125 Mhz LVDS U3 LVDS U6 100 Mhz 100 Mhz LVDS U7 100 Mhz LVDS U4 U5 TSPUSHEVT0 DDR3B_CLKP/N TSPUSHEVT1 TSCOMPOUT TSSYNCEVT USB_CLKP/N LVDS CLOCK MUX PCIE_CLKP/N TCLKA_P/N K2H SoC Exp Conn A 25MHZ Marvell 88E1111 4.194304MHz LM3S2D93 ( MCU ) Crystal From AMC.0 Card Edge TX20 RP1CLKP/N TX19 RP1FBP/N MCU AMC.0 Card-Edge A X'TAL 25MHZ Marvell 88E1111 OSC 32.768 Khz TCLKC_N TIMO0 TCLKC_P TIMI0 PHYSYNC TSRXCLKOUTP/N1 RADSYNC PHYSYNC 16MHz A RADSYNC Sync Event Select Jumper Block TSRXCLKOUTP/N0 Crystal X'TAL TIMO1 DDR3A_CLKP/N 100 Mhz 100 Mhz SYNC-E IEEE1588 ALT_CORE_CLKP/N SPI CLK3 B ARM_CLKP/N REF_SEL MCU SPI0 (CS2) GPS Antenna SMA GPS Receiver CDCM6208 PRIREF+/- MCU SPI to GPIO TEST POINT Exp Conn A U.FL 156.25 Mhz TIMO1 TIMI1 A EXTFRAMEEVENT GPS Module DSPM-8305E Designed for TI by ADVANTECH Accessory IC Connector Title CLOCK & TIMER DIAGRAM Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 8 of 43 5 4 3 Microcontroller Block Diagram 2 SPI GPIO CLK[1..3]_REF_SEL REFCLK[1..3]_PD# PLL_LOCK[1..3] CLK_RST# CS#6 INT3 1 CLOCK Group TI_CDCM6208 CLK1 TI_CDCM6208 CLK2 TI_CDCM6208 CLK3 MIPI-60pin emulation D NAND FLASH (Female) GPS Receiver D BOARDID[0:2]/PRESENCE Exp Conn A MCU_GPS_ENABLE GPIO[0:16] Microcontroller CS#3 INT0 Level Shift K2H SoC SPI1_CS0# SPI1_CLK SPI1_MOSI LCD_RSTz LCD_A0 LCD Display (128x32) 3.3V LCD Control UARRX EEPROM_WPz NAND_WPz To FTDI JTAG JTAG 10pin Header JTAG MCU_JTAG_RESET# mini-USB SOC DIP_SW_B[0..3] Function SWITCH Boot loder SW C SPI0_CS[0..2]# SPI0_CLK SPI0_MOSI SPI0_MISO CLOCK Group TI_CDCM6208 CLK1 TI_CDCM6208 CLK2 TI_CDCM6208 CLK3 BLACK LCD DISPLAY CS#5 INT2 SPI0 (CS#5) FTDI UARRX Accessory IC AMC.0 Card-Edge A SPI GPIO RED CLOCK SOC SPI_GPIO_RESET RESET & Interrupts Control SOC (MCU PJ1) BOOTCOMPLETE SOC_RESETSTATz C RESETSTATz 1.8V Level Shift 3.3V 1.8V RESET MCU_RESET# DSP_SDA MCU_EXP_SCL DSP_SCL Power Sequences Control EEPROM MAIN_POWER_START SOC_POWER_START MAIN_POWER_GOOD SOC_POWER_GOOD PW_SEQ_SCL RESET 88E1111 x 2 PW_SEQ_I2C_EN ISOLATOR MMC LED BF MMC_BLUE_LED AMC MMC SMB_SCL_IPMBL SMB_SDA_IPMBL MMC_GA[0..2] Control I2C0 VCC3V3_MP VDD VDDA MMC_ENABLE_N VCC2V5_EN VCC0V75_EN VCC5_EN VCC1V2_EN VCC3V3_AUX_EN_R TI_TPS73701DRBT x2 CVDD_PWR_OK UCD9244_EN AMC.0 Card Edge A PG1 ENA1 Control TI mircroController LM3S2D93 B PIN HEADER PM BUS Alert Alert Control Clk Power Data TI UCD9244 FAN_PWM PM BUS MCU_BOOTSELECT UCD_PWR_OK Farm1_UCD_EN PG7 Control NOR_WP# CVDD (UCD74120) CVDDT (UCD74120) CVDDD0V95/ CVDDA0V95 (UCD7242) FULL RESET MCU_WAKE# AMC_Detect PG0 NOR FLASH x2 TI_TPS51200DRCT VCC3V3_MP_ALT VBAT Wake# MMC_PS_N0 VCC3V3_MP_AMC Power TI_TPS74701DRCT x1 TI_TPS54620RGY x2 UCD9090 Power Sequencing controller PW_SEQ_RSTz DIODE MMC_RED_LED VCC2V5_MON VCCA0V75_MON VCCB0V75_MON VCC5_MON VCC1V2_MON VCC3_AUX_MON VPP1V8_MON PW_SEQ_SDA PHY PHY_RSTz SDA0 SCL0 I2C1 Exp Conn A MCU_EXP_SDA SOC_I2C_EN BLACK To AMC.0 Card Edge A PORz RESETFULLz RESETz PACLKSEL LRRESETNMIENz CORESEL[0:2] NMIz LRESETz CLKSEL HOUT UART0 TX (MCU RSTz) B SOC_PORz SOC_RESETFULLZ SOC_RESETz SOC_PACLKSEL SOC_LRESETNMIENZ SOC_CORESEL[0..3] SOC_NMIz SOC_LRESETz SOC_CORECLKSEL SOC_HOUT UART1 RX Board Controller Register AND AMC LED (RED & BLUE) DEBUG LED0 ~ LED2 Configurations WARM_RESETz (MCU PJ0) Marvell BF VPPB I2C1 PLLLOCK SOC_BOOTCOMPLETE Level Shift 3.3V SOC FULL_RESETz SPI GPIO SPI_GPIO_INT SPI0 CS5# (SPI0 CS0/CS1/CS2) MCU_RESETz Connector BOARDID[0:2]/PRESENCE PLLLOCK_LED SOC_VPPB_EN SOC_SCL1/SDA1 SOC_PLLLOCK UART0 MUX UARRX PLLLOCK LED K2H SOC CS#4 INT1 SPI_GPIO_INT UARTX MAX3221E RS232 BF EMU[0:33] GPIO[0:16] SPI_GPIO_RESET Boot & Device configurations SPI0 CS3# / CS4# UARTX 3.3V UART 4pin Header SPI0 (CS#3/4) GPIO[12:15] 1.8V SOC (SPI1 CS0) 4th to detect Microcontroller 1.8V SPI GPIO 4-PIN FAN Header PB7 PG1 ENA1 VCC1V8 (UCD74106) VCC1V5 (UCD74111) VDD33/ VCC0V85 (UCD7242) Alert PM BUS Clk Power Data TI UCD9244 PW_SEQ_SDA/SCL A A DSPM-8305E Designed for TI by ADVANTECH Title Microcontroller Block Diagram Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 9 of 43 5 4 3 2 1 Intentionally Left Blank D D C C B B A A DSPM-8305E Designed for TI by ADVANTECH Title Intentionally Left Blank Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 10 of 43 5 4 3 2 1 K2EVM-HK EVM PLACEMENT (TOP SIDE) 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D 0 D 16 15 14 NAND FLASH 120-pin Expansion Header KEY 13 12 MicroUSB#1 LCD Display (128*32) 11 10 Z3 ADF CONN (30PIN) 9 MCU LM3S2D93 LED Debug LED(BLUE) NOR FLASH PMBUS CLK#2 CDCM62008 CDCM62008 FULL Reset UCD9090 UCD9244 XDS200 Area DDR3A USB3.0 UART TIMER0 & I2C EMU[0:18] RP1/SYNC Hyper Link USB3.0 EEPROM 512Kb AIFx6 Marvell 88E1111-B2 XFIX2 TI_TMS320TCI663x SRIOx4 SPI SGMIIX4 SOC PCIEX2 GPIO 6 I2C #2 AIFX2 SRIOX4 PCIEX2 SO-DIMM (1GB-8GB) &MDIO POWER control JTAG&USIM RJ45 Marvell 88E1111-B2 EMIF16 DDR3B Heat Sink PWR B B UCD9244 DDR3 DDR3 DDR3 DDR3 DDR3 x16b x16b x16b x16b x16b 4Gb 4Gb 4Gb 4Gb 4Gb MMC USIM Socket X2 X2 2 WARM Reset PWR CLK#3 Hyper Link 7 3 C LED Debug LED(G/R) COM PWR CLK#1 8 4 Debug LED(BLUE) EMIF16 CDCM62008 5 MMC LED(RED) MMC LED(BLUE) MMC Z3 ADF XFI CONN (30PIN) AIFX4 C USB to UR FT2232 TC6000G 0 MDIO PWR JACK 1 PIN1 GPS SMA MCU Reset 1.25Gbit/s POWER 12V JTAG PIN170 22 21 20 19 18 17 16 Dotted line is Bottom SIDE Component EVM with K2H device does not support XGMII 15 14 13 12 11 Note: Note: 10 9 8 7 6 5 4 3 2 1 0 PCB Half Length = 181.5x148.5mm A A DSPM-8305E Designed for TI by ADVANTECH Title K2EVM-HK Placement Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 11 of 43 5 4 3 2 AMC_JTAG_TDI AMC_JTAG_TDO AMC_JTAG_TMS AMC_JTAG_TCK VCC12 R793 R791 R780 R773 10K 10K 10K 10K AMC_JTAG_RST# R787 10K 1 VCC3V3_AUX AMC1 D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 MMC_PS_N1 VCC3V3_MP_AMC 36 MMC_GA0 OUT Management Power 14 14 AMC0_SGMII2_TX_DP AMC0_SGMII2_TX_DN 14 14 AMC0_SGMII2_RX_DP AMC0_SGMII2_RX_DN SGMII[1:0] 36 MMC_GA1 14 14 AMC1_SGMII3_TX_DP AMC1_SGMII3_TX_DN 14 14 AMC1_SGMII3_RX_DP AMC1_SGMII3_RX_DN 36 MMC_GA2 IN IN OUT OUT OUT IN IN OUT OUT OUT C 36 14 14 AMCC_P4_PCIe_TX1P AMCC_P4_PCIe_TX1N IN IN 14 14 AMCC_P4_PCIe_RX1P AMCC_P4_PCIe_RX1N OUT OUT 14 14 AMCC_P5_PCIe_TX2P AMCC_P5_PCIe_TX2N IN IN 14 14 AMCC_P5_PCIe_RX2P AMCC_P5_PCIe_RX2N OUT OUT SMB_SCL_IPMBL OUT 36 36 TCLKB also serves as a 25.0MHz LVDS clock to CLK3 PRI_REF for the HyperLink synchronization. SMB_SDA_IPMBL 27 27 21 21 TCLKB_P TCLKB_N PCIe_REF_CLK_P PCIe_REF_CLK_N MMC_PS_N1 36 BI OUT OUT OUT OUT 1 D10 ASD500V 0.1A MMC_PS_N0 2 MMC_PS_N0 OUT S S S D D D D 3 2 1 C351 3 D8 BZX84-C12 12V 1 R434 1uF 25V 100K EXP_SCL2_3V3 EXP_SDA2_3V3 OUT OUT AMC_RP1FBP AMC_RP1FBN OUT OUT PHYSYNC RADSYNC IN IN TCLKC_P TCLKC_N R742 R740 0 10 AMC_RP1CLKP AMC_RP1CLKN IN BI IN IN 19 19 19 19 19 D JTAG external RP1CLK 20 20 Expansion I2C 18,39 18,39 20 20 AIF CLK & FS 20,35 20,35 AMCC_P18_AIF5_TXP AMCC_P18_AIF5_TXN AMCC_P18_AIF5_RXP AMCC_P18_AIF5_RXN AMCC_P17_AIF4_TXP AMCC_P17_AIF4_TXN OUT OUT AMCC_P17_AIF4_RXP AMCC_P17_AIF4_RXN OUT OUT TCLKD_P TCLKD_N OUT IN AMC_TIMO0 SOC_TIMO0 20 20 20 20 AIF[4:5] 20 20 20 20 TCLKD also serves as a 30.72MHz LVDS clock to CLK1 PRI_REF for the AIF synchronization 25 25 18 18,39 TCLKCp/n alsp servers as the DSP_TIMI0 and DSP_TIMO0 and 3.3V I/O respectively TCLKC_P : output for DSP_TIMI0 TCLKC_N : intput for DSP_TIMO0 IN IN OUT OUT IN IN OUT OUT IN IN OUT OUT IN IN OUT OUT AMCC_P11_SRIO4_TXP AMCC_P11_SRIO4_TXN 14 14 AMCC_P11_SRIO4_RXP AMCC_P11_SRIO4_RXN 14 14 AMCC_P10_SRIO3_TXP AMCC_P10_SRIO3_TXN 14 14 AMCC_P10_SRIO3_RXP AMCC_P10_SRIO3_RXN AMCC_P9_SRIO2_TXP AMCC_P9_SRIO2_TXN C 14 14 SRIO[1:4] 14 14 AMCC_P9_SRIO2_RXP AMCC_P9_SRIO2_RXN 14 14 AMCC_P8_SRIO1_TXP AMCC_P8_SRIO1_TXN 14 14 AMCC_P8_SRIO1_RXP AMCC_P8_SRIO1_RXN 14 14 B 3 G WB_4V_2.00mm <Characteristic> Q20 2N7002 0.3A/60V R427 100K A IN C724 1uF 16V S C745 Q9 0.1uF MMBT3904LT1G50V FAN_PWM VCC12 C729 1uF 16V DSPM-8305E Designed for TI by ADVANTECH 2 1 1 2 3 4 C731 1uF 16V 37 D 1 FAN1 VCC12 3 A TP57 R431 100K R436 100K R437 100K 0 0 AMC_JTAG_TDI AMC_JTAG_TDO AMC_JTAG_RST# AMC_JTAG_TMS AMC_JTAG_TCK DC FAN Connector for SOC 8 7 6 5 C346 10uF 16V 2 R435 1K 1% R764 R759 OUT OUT G 1 3 2 JACK_3H <Characteristic> OUT OUT DSP_SCL_AMC DSP_SDA_AMC -8.1A/30V SI4435DDY-T1-GE3 Q19 DC_IN1 C348 1000pF 50V OUT IN OUT OUT OUT GF-AMC-B OVP: ~12.7V+0.6V = ~13.3V C354 0.1uF 50V AMC_JTAG_TDI AMC_JTAG_TDO AMC_JTAG_RST# AMC_JTAG_TMS AMC_JTAG_TCK 2 B OUT 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 GND_56 TDI TDO TRST TMS TCK GND_55 Tx20+ Tx20GND_54 Rx20+ Rx20GND_53 Tx19+ Tx19GND_52 Rx19+ Rx19GND_51 Tx18+ Tx18GND_50 Rx18+ Rx18GND_49 Tx17+ Tx17GND_48 Rx17+ Rx17GND_47 TCLKD+ TCLKDGND_46 TCLKC+ TCLKCGND_45 Tx15+ Tx15GND_44 Rx15+ Rx15GND_43 Tx14+ Tx14GND_42 Rx14+ Rx14GND_41 Tx13+ Tx13GND_40 Rx13+ Rx13GND_39 Tx12+ Tx12GND_38 Rx12+ Rx12GND_37 Tx11+ Tx11GND_36 Rx11+ Rx11GND_35 Tx10+ Tx10GND_34 Rx10+ Rx10GND_33 Tx9+ Tx9GND_32 Rx9+ Rx9GND_31 Tx8+ Tx8GND_30 Rx8+ Rx8GND_29 4 PCIe[2:1] MMC_ENABLE_N GND_1 PWR_12V_1 PS1 MP GA0 RSRVD6 GND_2 RSRVD8 PWR_12V_2 GND_3 Tx0+ Tx0GND_4 Rx0+ Rx0GND_5 GA1 PWR_12V_3 GND_6 Tx1+ Tx1GND_7 Rx1+ Rx1GND_8 GA2 PWR_12V_4 GND_9 Tx2+ Tx2GND_10 Rx2+ Rx2GND_11 Tx3+ Tx3GND_12 Rx3+ Rx3GND_13 ENABLE PWR_12V_5 GND_14 Tx4+ Tx4GND_15 Rx4+ Rx4GND_16 Tx5+ Tx5GND_17 Rx5+ Rx5GND_18 SCL_L PWR_12V_6 GND_19 Tx6+ Tx6GND_20 Rx6+ Rx6GND_21 Tx7+ Tx7GND_22 Rx7+ Rx7GND_23 SDA_L PWR_12V_7 GND_24 TCLKA+ TCLKAGND_25 TCLKB+ TCLKBGND_26 FCLKA+ FCLKAGND_27 PS0 PWR_12V_8 GND_28 0.2A Title AMC GF Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 12 of 43 5 4 SPI level shift VCC1V8 2 19 B1 B2 B3 B4 B5 B6 B7 B8 OE A1 A2 A3 A4 A5 A6 A7 A8 10 1 3 4 5 6 7 8 9 4.7K VCC1V8 SPI_GPIO_INT0_1V8 SPI_GPIO_INT1_1V8 SPI_GPIO_INT2_1V8 MCU_SPI0_CLK_1V8 MCU_SPI0_MOSI_1V8 MCU_SPI0_MISO_1V8 SPI_GPIO_RESET_1V8 39 36 MCU_SPI0_CS3z 36 MCU_SPI0_CS4z 36 MCU_SPI0_CS5z EXP_UART1_TXD_3V3 MCU_SPI0_CS3z MCU_SPI0_CS4z MCU_SPI0_CS5z EXP_UART1_TXD_3V3 IN IN IN IN C418 0.1uF 16V U51 1 2 3 4 5 6 7 8 VCCA 1DIR 2DIR 1A1 1A2 2A1 2A2 GND1 VCCB 1OE 2OE 1B1 1B2 2B1 2B2 GND2 16 15 14 13 12 11 10 9 D MCU_SPI0_CS3z_1V8 MCU_SPI0_CS4z_1V8 MCU_SPI0_CS5z_1V8 SOC_UART1_RXD_1V8 OUT SOC_UART1_RXD_1V8 18 TI_SN74AVC4T245PWR IN EXP_UARTTXD 18 11 20 18 17 16 15 14 13 12 VCC1V8 C45 0.1uF 16V R521 VCCA SPI_GPIO_INT0 OUT SPI_GPIO_INT1 OUT SPI_GPIO_INT2 OUT MCU_SPI0_CLK IN MCU_SPI0_MOSI IN MCU_SPI0_MISO OUT SPI_GPIO_RESET IN EXP_UART1_RXD_3V3 OUT VCCB D GND U52 1 VCC3V3_MP C421 0.1uF 16V C427 0.1uF 16V SPI_GPIO_INT0 SPI_GPIO_INT1 SPI_GPIO_INT2 25,26,27,36 MCU_SPI0_CLK 25,26,27,36 MCU_SPI0_MOSI 25,26,27,36 MCU_SPI0_MISO 36 SPI_GPIO_RESET 39 EXP_UART1_RXD_3V3 2 3.3V <=> 1.8V VCC3V3_MP 36 36 36 3 TI_TXS0108EPWR 1.8V Level U50 1.8V Level U48 18,39 18,39 18,39 18,39 18,39 18,39 18,39 18,39 SOC_GPIO_07 SOC_GPIO_06 SOC_GPIO_05 SOC_GPIO_04 SOC_GPIO_03 SOC_GPIO_02 SOC_GPIO_01 SOC_GPIO_00 OUT OUT OUT OUT OUT OUT OUT OUT SPI_GPIO_INT0_1V8 SPI_GPIO_RESET_1V8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS CS SCK SI SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OUT OUT OUT OUT OUT OUT OUT OUT SOC_GPIO_08 SOC_GPIO_09 SOC_GPIO_10 SOC_GPIO_11 SOC_GPIO_12 SOC_GPIO_13 SOC_GPIO_14 SOC_GPIO_15 18,39 18,39 18,39 18,39 18,39 18,39 18,39 18,39 18 36 18,39 42 35 19 19 SOC_PLLLOCK PLLLOCK_LED SOC_GPIO_16 SOC_VPPB_EN MCU_GPS_ENABLE EMIF_DIR EMIF_OEz IN PLLLOCK_LED OUT OUT OUT OUT OUT R812 NL/0 OUT SPI_GPIO_INT1_1V8 SPI_GPIO_RESET_1V8 VCC1V8 MCU_SPI0_CS3z_1V8 MCU_SPI0_CLK_1V8 MCU_SPI0_MOSI_1V8 MCU_SPI0_MISO_1V8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS CS SCK SI SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OUT NAND_WPz 19 OUT EEPROM_WPz 18 BD_PRESENT 39 IN BD_ID0 39 IN BD_ID1 39 IN BD_ID2 39 IN SOC_SCL1 18 IN BI SOC_SDA1 18 VCC1V8 MCU_SPI0_CS4z_1V8 MCU_SPI0_CLK_1V8 MCU_SPI0_MOSI_1V8 MCU_SPI0_MISO_1V8 MICROCHIP_MCP23S17T-E/SS MICROCHIP_MCP23S17T-E/SS MicroChip SPI to GPIO C C MicroChip SPI to GPIO 3.3V Level U53 1.8V Level 39 U47 18,36 18 18 18 18 18 18 18 SOC_RESETSTATZ SOC_BOOTCOMPLETE SOC_LRESETNMIENZ SOC_LRESETZ SOC_NMIZ SOC_HOUT SOC_PACLKSEL SOC_CORECLKSEL IN IN OUT OUT OUT IN OUT OUT SPI_GPIO_INT2_1V8 SPI_GPIO_RESET_1V8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS CS SCK SI SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OUT OUT OUT OUT OUT OUT OUT OUT SOC_CORESEL0 18 SOC_CORESEL1 18 SOC_CORESEL2 18 SOC_CORESEL3 18 TIMI_MUX_OEz 18 SOC_RESETFULLZ 18 SOC_RESETZ 18 SOC_PORZ 18 VCC1V8 25 26 27 19 39 36 uRTM_PS# CLK1_REF_SEL CLK2_REF_SEL CLK3_REF_SEL MCU_EMU_DET 39 EXT_PS# MCU_RESETSTATz 32 PHY1_INT# SPI_GPIO_INT3 MCU_SPI0_CS5z_1V8 MCU_SPI0_CLK_1V8 MCU_SPI0_MOSI_1V8 MCU_SPI0_MISO_1V8 IN OUT OUT OUT OUT IN OUT R568 IN SPI_GPIO_INT3 OUT SPI_GPIO_RESET 28 27 26 25 24 23 22 NL/0 21 20 19 18 17 16 15 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS CS SCK SI SO 1 2 3 4 5 6 7 8NL/0 9 10 11 12 13 14 REFCLK1_PD# OUT REFCLK2_PD# OUT REFCLK3_PD# OUT PLL_LOCK1 IN PLL_LOCK2 IN PLL_LOCK3 IN CLK_RSTz OUT R801 PHY2_INT# IN VCC3V3_AUX MCU_SPI0_CS6z MCU_SPI0_CLK MCU_SPI0_MOSI MCU_SPI0_MISO IN 25 26 27 25 26 27 25,26,27 33 MCU_SPI0_CS6z CDCM-620X Control 36 MICROCHIP_MCP23S17T-E/SS MICROCHIP_MCP23S17T-E/SS MicroChip SPI to GPIO MicroChip SPI to GPIO B B A A DSPM-8305E Designed for TI by ADVANTECH Title SPI to GPIO Converter Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 13 of 43 5 4 3 2 1 U24F SRIO X4 D TI_TMS320TCI6638 12 12 12 12 12 12 12 12 AMCC_P8_SRIO1_RXN AMCC_P8_SRIO1_RXP AMCC_P9_SRIO2_RXN AMCC_P9_SRIO2_RXP AMCC_P10_SRIO3_RXN AMCC_P10_SRIO3_RXP AMCC_P11_SRIO4_RXN AMCC_P11_SRIO4_RXP 12 12 12 12 12 12 12 12 AMCC_P8_SRIO1_TXN AMCC_P8_SRIO1_TXP AMCC_P9_SRIO2_TXN AMCC_P9_SRIO2_TXP AMCC_P10_SRIO3_TXN AMCC_P10_SRIO3_TXP AMCC_P11_SRIO4_TXN AMCC_P11_SRIO4_TXP C258 C265 C253 C257 C245 C248 C240 C243 IN IN IN IN IN IN IN IN 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF AMCC_P8_SRIO1_RXN_C AMCC_P8_SRIO1_RXP_C AMCC_P9_SRIO2_RXN_C AMCC_P9_SRIO2_RXP_C AMCC_P10_SRIO3_RXN_C AMCC_P10_SRIO3_RXP_C AMCC_P11_SRIO4_RXN_C AMCC_P11_SRIO4_RXP_C 16V 16V 16V 16V 16V 16V 16V 16V AV24 AV25 AU22 AU23 AW22 AW23 AV21 AV22 AT24 AT25 AR23 AR24 AP22 AP23 AT21 AT22 OUT OUT OUT OUT OUT OUT OUT OUT Caution! RIORXN0 RIORXP0 RIORXN1 RIORXP1 RIORXN2 RIORXP2 RIORXN3 RIORXP3 RIOTXN0 RIOTXP0 RIOTXN1 RIOTXP1 RIOTXN2 RIOTXP2 RIOTXN3 RIOTXP3 "Place ALL SRIO DC-blocking caps on top layer adjacent to the SOC’s RX pins so that there are no additional vias" RSV021 RIOREFRES 6 of 26 TI_TMS320TCI6638 <Characteristic> AM23 D TP76 AM21 R671 3K 1% SGMII X4 VCC1V8 VCC3V3_AUX U24G TI_TMS320TCI6638 32 32 33 33 12 12 12 12 32 32 33 33 12 12 12 12 C SOC_SGMII0_RXN SOC_SGMII0_RXP SOC_SGMII1_RXN SOC_SGMII1_RXP AMC0_SGMII2_RX_DN AMC0_SGMII2_RX_DP AMC1_SGMII3_RX_DN AMC1_SGMII3_RX_DP IN IN IN IN IN IN IN IN SOC_SGMII0_TXN SOC_SGMII0_TXP SOC_SGMII1_TXN SOC_SGMII1_TXP AMC0_SGMII2_TX_DN AMC0_SGMII2_TX_DP AMC1_SGMII3_TX_DN AMC1_SGMII3_TX_DP OUT OUT OUT OUT OUT OUT OUT OUT C668 C686 C717 C716 C277 C288 C267 C276 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 16V 16V 16V 16V 16V 16V 16V 16V SOC_SGMII0_RXN_C SOC_SGMII0_RXP_C SOC_SGMII1_RXN_C SOC_SGMII1_RXP_C AMC0_SGMII2_RX_DN_C AMC0_SGMII2_RX_DP_C AMC1_SGMII3_RX_DN_C AMC1_SGMII3_RX_DP_C AW28 AW29 AV27 AV28 AU25 AU26 AW25 AW26 AU28 AU29 AT27 AT28 AR26 AR27 AP25 AP26 SGMII0RXN SGMII0RXP SGMII1RXN SGMII1RXP SGMII2RXN SGMII2RXP SGMII3RXN SGMII3RXP SGMII0TXN SGMII0TXP SGMII1TXN SGMII1TXP SGMII2TXN SGMII2TXP SGMII3TXN SGMII3TXP MDCLK MDIO AP31 SOC_MDC AR32 SOC_MDIO C321 0.1uF 16V R403 100K U31 SOC_MDC SOC_MDIO VCC1V8 RSV023 SGMIIREFRES 7 of 26 TI_TMS320TCI6638 <Characteristic> AM25 AM24 R404 4.7K 1% R405 4.7K 1% 1 2 3 4 GND VREF1 SCL1 SDA1 EN VREF2 SCL2 SDA2 TI_PCA9306DCUT 8 7 6 5 C325 0.1uF 16V SOC_MDC_3V3 SOC_MDIO_3V3 OUT BI R399 220 5% R400 220 5% 32,33,39 32,33,39 VCC2V5 TP79 C R685 3K 1% PCIE X2 Caution! U24P TI_TMS320TCI6638 12 12 AMCC_P4_PCIe_TX1N AMCC_P4_PCIe_TX1P OUT OUT 12 12 AMCC_P5_PCIe_TX2N AMCC_P5_PCIe_TX2P 12 12 AMCC_P4_PCIe_RX1N AMCC_P4_PCIe_RX1P IN IN OUT OUT 12 12 AMCC_P5_PCIe_RX2N AMCC_P5_PCIe_RX2P IN IN C308 C311 0.1uF 16V AMCC_P4_PCIe_TX1N_C 0.1uF 16V AMCC_P4_PCIe_TX1P_C AT30 AT31 C291 C300 0.1uF 16V AMCC_P5_PCIe_TX2N_C 0.1uF 16V AMCC_P5_PCIe_TX2P_C AR29 AR30 AU31 AU32 AV30 AV31 "Place ALL PCIe DC-blocking caps close to the TX pins" PCIETXN0 PCIETXP0 PCIETXN1 PCIETXP1 PCIERXN0 PCIERXP0 RSV022 AM28 TP86 R698 PCIERXN1 PCIERXP1 PCIEREFRES 16 of 26 TI_TMS320TCI6638 <Characteristic> 3K 1% AM26 B B HyperLink X8 TI_TMS320TCI6638 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 A Note: Only supported on K2H devices U24S HyperLink0_RXN0 HyperLink0_RXP0 HyperLink0_RXN1 HyperLink0_RXP1 HyperLink0_RXN2 HyperLink0_RXP2 HyperLink0_RXN3 HyperLink0_RXP3 HyperLink0_RXFLCLK HyperLink0_RXFLDAT HyperLink0_RXPMCLK HyperLink0_RXPMDAT IN IN IN IN IN IN IN IN OUT OUT IN IN HyperLink0_TXN0 HyperLink0_TXP0 HyperLink0_TXN1 HyperLink0_TXP1 HyperLink0_TXN2 HyperLink0_TXP2 HyperLink0_TXN3 HyperLink0_TXP3 HyperLink0_TXFLCLK HyperLink0_TXFLDAT HyperLink0_TXPMCLK HyperLink0_TXPMDAT OUT OUT OUT OUT OUT OUT OUT OUT IN IN OUT OUT C216 C218 C210 C215 C200 C203 C190 C199 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R628 16V 16V 16V 16V 16V 16V 16V 16V 22 HyperLink0_RXN0_C AW10 HyperLink0_RXP0_C AW11 HyperLink0_RXN1_C AU10 HyperLink0_RXP1_C AU11 HyperLink0_RXN2_C AV9 HyperLink0_RXP2_C AV10 HyperLink0_RXN3_C AW7 HyperLink0_RXP3_C AW8 HyperLink0_RXFLCLK_R AJ5 HyperLink0_RXFLDAT AJ4 HyperLink0_RXPMCLK AJ2 HyperLink0_RXPMDAT AG3 HyperLink0_TXN0 AP11 HyperLink0_TXP0 AP12 HyperLink0_TXN1 AR10 HyperLink0_TXP1 AR11 HyperLink0_TXN2 AP8 HyperLink0_TXP2 AP9 HyperLink0_TXN3 AR7 HyperLink0_TXP3 AR8 HyperLink0_TXFLCLK AJ3 HyperLink0_TXFLDAT AG5 22 HyperLink0_TXPMCLK_R AH5 HyperLink0_TXPMDAT AJ1 R609 HYPLNK0RXN0 HYPLNK0RXP0 HYPLNK0RXN1 HYPLNK0RXP1 HYPLNK0RXN2 HYPLNK0RXP2 HYPLNK0RXN3 HYPLNK0RXP3 HYPLNK0RXFLCLK HYPLNK0RXFLDAT HYPLNK0RXPMCLK HYPLNK0RXPMDAT HYPLNK1RXN0 HYPLNK1RXP0 HYPLNK1RXN1 HYPLNK1RXP1 HYPLNK1RXN2 HYPLNK1RXP2 HYPLNK1RXN3 HYPLNK1RXP3 HYPLNK1RXFLCLK HYPLNK1RXFLDAT HYPLNK1RXPMCLK HYPLNK1RXPMDAT HYPLNK0TXN0 HYPLNK0TXP0 HYPLNK0TXN1 HYPLNK0TXP1 HYPLNK0TXN2 HYPLNK0TXP2 HYPLNK0TXN3 HYPLNK0TXP3 HYPLNK0TXFLCLK HYPLNK0TXFLDAT HYPLNK0TXPMCLK HYPLNK0TXPMDAT HYPLNK1TXN0 HYPLNK1TXP0 HYPLNK1TXN1 HYPLNK1TXP1 HYPLNK1TXN2 HYPLNK1TXP2 HYPLNK1TXN3 HYPLNK1TXP3 HYPLNK1TXFLCLK HYPLNK1TXFLDAT HYPLNK1TXPMCLK HYPLNK1TXPMDAT AU7 AU8 AV6 AV7 AU4 AU5 AV3 AV4 AH4 AG2 AF3 AF4 HyperLink1_RXN0_C HyperLink1_RXP0_C HyperLink1_RXN1_C HyperLink1_RXP1_C HyperLink1_RXN2_C HyperLink1_RXP2_C HyperLink1_RXN3_C HyperLink1_RXP3_C HyperLink1_RXFLCLK_R HyperLink1_RXFLDAT HyperLink1_RXPMCLK HyperLink1_RXPMDAT AT6 AT7 AP5 AP6 AR4 AR5 AT3 AT4 AH3 AH2 AH1 AF2 HyperLink1_TXN0 HyperLink1_TXP0 HyperLink1_TXN1 HyperLink1_TXP1 HyperLink1_TXN2 HyperLink1_TXP2 HyperLink1_TXN3 HyperLink1_TXP3 HyperLink1_TXFLCLK HyperLink1_TXFLDAT HyperLink1_TXPMCLK_R HyperLink1_TXPMDAT 16V 16V 16V 16V 16V 16V 16V 16V 22 22 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R621 R309 C517 C523 C511 C513 C505 C510 C502 C506 IN IN IN IN IN IN IN IN OUT OUT IN IN HyperLink1_RXN0 HyperLink1_RXP0 HyperLink1_RXN1 HyperLink1_RXP1 HyperLink1_RXN2 HyperLink1_RXP2 HyperLink1_RXN3 HyperLink1_RXP3 HyperLink1_RXFLCLK HyperLink1_RXFLDAT HyperLink1_RXPMCLK HyperLink1_RXPMDAT 39 39 39 39 39 39 39 39 OUT OUT OUT OUT OUT OUT OUT OUT IN IN OUT OUT HyperLink1_TXN0 HyperLink1_TXP0 HyperLink1_TXN1 HyperLink1_TXP1 HyperLink1_TXN2 HyperLink1_TXP2 HyperLink1_TXN3 HyperLink1_TXP3 HyperLink1_TXFLCLK HyperLink1_TXFLDAT HyperLink1_TXPMCLK HyperLink1_TXPMDAT 39 39 39 39 39 39 39 39 “The HyperLink routes should have a maximum of 2 vias and no via stubs – All routes should be on the outer layer of the board.” 39 39 39 39 39 39 39 39 A TP67 TP68 AN10 1% 3K R635 AM9 RSV019 HYPLNK0REFRES 19 of 26 TI_TMS320TCI6638 <Characteristic> RSV020 HYPLNK1REFRES AM7 R632 3K 1% AM6 DSPM-8305E Designed for TI by ADVANTECH Title SOC_SERDES_PORTS Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 14 of 43 5 4 XFI X2 3 2 1 Note: Only supported on K2K devices U24X TI_TMS320TCI6638 D D 39 39 39 39 SOC_XFI_RX_DN0 SOC_XFI_RX_DP0 SOC_XFI_RX_DN1 SOC_XFI_RX_DP1 39 39 39 39 26 26 C241 C238 C237 C234 IN IN IN IN SOC_XFI_TX_DN0 SOC_XFI_TX_DP0 SOC_XFI_TX_DN1 SOC_XFI_TX_DP1 0.1uF 0.1uF 0.1uF 0.1uF 16V 16V 16V 16V SOC_XFI_RXN0_C SOC_XFI_RXP0_C SOC_XFI_RXN1_C SOC_XFI_RXP1_C AV19 AV18 AW20 AW19 AT19 AT18 AR20 AR19 OUT OUT OUT OUT SOC_XFI_CLKN SOC_XFI_CLKP XFIRXN0 XFIRXP0 XFIRXN1 XFIRXP1 R669 R658 IN IN 0 0 SOC_XFI_CLKN_R SOC_XFI_CLKP_R 3K 3K TSRXCLKOUT0N TSRXCLKOUT0P TSRXCLKOUT1N TSRXCLKOUT1P AC2 AC1 TSPUSHEVt0_E TSPUSHEVt1_E AC3 AB1 TSSYNCEVT_E TSCOMPOUT_E AL1 AM1 AT_CLKN_C AT_CLKP_C IN IN OUT OUT C177 C176 AP1 AN1 TSRX_CLK0N TSRX_CLK0P AP3 AN3 TSRX_CLK1N TSRX_CLK1P TSPUSHEVt0_E TSPUSHEVt1_E 39 39 TSSYNCEVT_E TSCOMPOUT_E 39 35,39 0.1uF 16V 0.1uF 16V IN IN AT_CLKN AT_CLKP OUT OUT TSRX_CLK0N TSRX_CLK0P 39 39 OUT OUT TSRX_CLK1N TSRX_CLK1P 39 39 25 25 122.88MHz XFIMDIO XFIMDCLK 1% 1% AN16 AM19 XFIREFRES0 XFIREFRES1 AN19 TP74 TSREFCLKN TSREFCLKP XFICLKN XFICLKP AT33 AR34 R656 R667 TSSYNCEVT TSCOMPOUT XFITXN0 XFITXP0 XFITXN1 XFITXP1 AU20 AU19 SOC_XFI_MDIO SOC_XFIMD_CLK TSPUSHEVT0 TSPUSHEVT1 RSV026 24 of 26 TI_TMS320TCI6638 <Characteristic> VCC1V8 VCC3V3_AUX C345 0.1uF 16V C R440 100K C U36 SOC_XFIMD_CLK SOC_XFI_MDIO VCC1V8 R425 4.7K 1% R426 4.7K 1% 1 2 3 4 GND VREF1 SCL1 SDA1 EN VREF2 SCL2 SDA2 8 7 6 5 C360 0.1uF 16V SOC_XFIMD_CLK_3V3 SOC_XFI_MDIO_3V3 OUT BI TI_PCA9306DCUT R438 220 5% R439 220 5% 39 39 VCC3V3_AUX USB3.0 X1 Adding 0815'13 VCC1V8 U70 1 2 3 USBDRVVBUS_R VCC 5 C844 Current limiting is 1.5A VCC5 U59 16V 0.1uF 5 4 4 GND TI_SN74LVC1G07DCKR <Characteristic> R813 NL/0 IN OUT GND FLT EN 1 2 3 VBUS C173 100uF 16V TI_TPS2065CDBVR VCC5 <Characteristic> R814 C183 0.1uF 16V 4.7K 1% GND GND GND SOC_USB 90_100MHZ U24Y 15 15 15 15 27 27 USB_CLKN USB_CLKP IN IN USBDP USBDN USB_RXN USB_RXP USB_TXN USB_TXP R608 R607 BI BI IN IN OUT OUT 0 USB_CLKN_R 0 USB_CLKP_R U2 T2 Y1 W1 V1 U1 V2 W2 VPH USBDP USBDM USBRX0M USBRX0P USBTX0M USBTX0P VDDUSB VP VPTX USBID0 USBVBUS USBDRVVBUS USBCLKM USBCLKP USBRESREF 25 of 26 TI_TMS320TCI6638 <Characteristic> Y13 AB13 AA12 Y11 USBVDD3V3 B48 0.5A 120_100MHz VBUS 2 15 USBDP BI 1 R799 100 TP43 R809 3 USBDN_R 4 USBDP_R 1 2 3 4 5 6 7 8 9 B24 B22 VCC0V85 USB0V85 R1 T1 L3 USBDRVVBUS BI USBVBUS 10 USBDRVVBUS_R 15 15 USB_RXN USB_RXP IN IN 1 4 USB_RXN_R 2 3 USB_RXP_R C839 0.1uF 16V USB_TXN_R C840 0.1uF 16V USB_TXP_R H1 H2 90_100MHZ AA1R310 200 1%_1/16W R800 NL/100 15 USB_TXN OUT 15 USB_TXP OUT USB3.0 TypeA VBUS DD+ GND B StdA_SSRXStdA_SSRX+ GND_DRAIN StdA_SSTXStdA_SSTX+ PTH_1 PTH_2 PB1 30_100MHz USB3.0_9H <Characteristic> 3A D14 1 15 15 USBDN 2 TI_TMS320TCI6638 B 15 TPD2EUSB30DRTR 1A B29 3 1 VDD33 3 USBVDD3V3 C558 0.01uF 16V 0.1uF 2A 8KV C557 4.7uF 6.3V 2 C225 0.1uF 16V Remove ESD Diode in 0516'13 2A B28 3 C208 0.1uF 16V C522 0.01uF 16V 0.1uF 2A 1 A VCC0V85 C508 4.7uF 6.3V 2 USB0V85 A DSPM-8305E Designed for TI by ADVANTECH Title SOC_XFI_USB Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 15 of 43 5 4 3 2 1 D D U24K TI_TMS320TCI6638 30 30 30 OUT SOC_DDR3A_EDQSN_[0..7] SOC_DDR3A_EDQSN_8 SOC_DDR3A_EDQSP_[0..7] 30 OUT OUT SOC_DDR3A_EDQSP_8 30 30 30 SOC_DDR3A_EBA_0 SOC_DDR3A_EBA_1 SOC_DDR3A_EBA_2 OUT SOC_DDR3A_EDQSN_0 SOC_DDR3A_EDQSN_1 SOC_DDR3A_EDQSN_2 SOC_DDR3A_EDQSN_3 SOC_DDR3A_EDQSN_4 SOC_DDR3A_EDQSN_5 SOC_DDR3A_EDQSN_6 SOC_DDR3A_EDQSN_7 SOC_DDR3A_EDQSN_8 SOC_DDR3A_EDQSP_0 SOC_DDR3A_EDQSP_1 SOC_DDR3A_EDQSP_2 SOC_DDR3A_EDQSP_3 SOC_DDR3A_EDQSP_4 SOC_DDR3A_EDQSP_5 SOC_DDR3A_EDQSP_6 SOC_DDR3A_EDQSP_7 SOC_DDR3A_EDQSP_8 D1 C3 B5 A7 B17 A19 B21 B23 A15 E1 B3 A5 B7 A17 B19 A21 A23 B15 B11 C11 G11 OUT OUT OUT DDR3ADQS0N DDR3ADQS1N DDR3ADQS2N DDR3ADQS3N DDR3ADQS4N DDR3ADQS5N DDR3ADQS6N DDR3ADQS7N DDR3ADQS8N DDR3ADQS0P DDR3ADQS1P DDR3ADQS2P DDR3ADQS3P DDR3ADQS4P DDR3ADQS5P DDR3ADQS6P DDR3ADQS7P DDR3ADQS8P DDR3AA00 DDR3AA01 DDR3AA02 DDR3AA03 DDR3AA04 DDR3AA05 DDR3AA06 DDR3AA07 DDR3AA08 DDR3AA09 DDR3AA10 DDR3AA11 DDR3AA12 DDR3AA13 DDR3AA14 DDR3AA15 E8 G9 G8 G10 F9 F8 C9 D9 B9 D8 F10 A9 E10 A10 B10 D10 SOC_DDR3A_EA0 SOC_DDR3A_EA1 SOC_DDR3A_EA2 SOC_DDR3A_EA3 SOC_DDR3A_EA4 SOC_DDR3A_EA5 SOC_DDR3A_EA6 SOC_DDR3A_EA7 SOC_DDR3A_EA8 SOC_DDR3A_EA9 SOC_DDR3A_EA10 SOC_DDR3A_EA11 SOC_DDR3A_EA12 SOC_DDR3A_EA13 SOC_DDR3A_EA14 SOC_DDR3A_EA15 OUT SOC_DDR3A_EA[0..15] 30 U24J TI_TMS320TCI6638 30 30 SOC_DDR3A_EODT_0 SOC_DDR3A_EODT_1 30 30 SOC_DDR3A_ECAS# SOC_DDR3A_ERAS# OUT OUT 30 SOC_DDR3A_EWE# OUT 30 SOC_DDR3A_EMRESETN C13 A14 F12 R648 4.7K B14 OUT 30 30 SOC_DDR3A_ECKN_0 SOC_DDR3A_ECKP_0 OUT OUT 30 30 SOC_DDR3A_ECKN_1 SOC_DDR3A_ECKP_1 OUT OUT TP46 TP47 DDR3ABA0 DDR3ABA1 DDR3ABA2 E12 G13 OUT OUT B12 A12 B13 A13 A24 B24 DDR3APLLOBSCLKN DDR3APLLOBSCLKP DDR3AODT0 DDR3AODT1 DDR3ACAS DDR3ARAS DDR3AWE RSV029 DDR3ACKE0 DDR3ACKE1 DDR3ACE0 DDR3ACE1 DDR3ARESET DDR3ACLKOUTN0 DDR3ACLKOUTP0 DDR3ACLKOUTN1 DDR3ACLKOUTP1 RSV027 RSV028 DDR3ARZQ0 DDR3ARZQ1 DDR3ARZQ2 F13 DDR3AATO TP71 G12 A11 D11 F11 D12 D13 H16 H10 H22 OUT OUT SOC_DDR3A_ECKE_0 SOC_DDR3A_ECKE_1 30 30 OUT OUT SOC_DDR3A_ECS_0# SOC_DDR3A_ECS_1# 30 30 TP69 TP72 R657 R640 R684 240 1% 240 1% 240 1% DDR3APLLOBSCLKN DDR3APLLOBSCLKP 10 of 26 TI_TMS320TCI6638 <Characteristic> 11 65 TI_TMS320TCI6638 <Characteristic> C C SOC_DDR3A_EDQ[0..63] 30 U24L SOC_DDR3A_EDQ0 SOC_DDR3A_EDQ1 SOC_DDR3A_EDQ2 SOC_DDR3A_EDQ3 SOC_DDR3A_EDQ4 SOC_DDR3A_EDQ5 SOC_DDR3A_EDQ6 SOC_DDR3A_EDQ7 SOC_DDR3A_EDQ8 SOC_DDR3A_EDQ9 SOC_DDR3A_EDQ10 SOC_DDR3A_EDQ11 SOC_DDR3A_EDQ12 SOC_DDR3A_EDQ13 SOC_DDR3A_EDQ14 SOC_DDR3A_EDQ15 SOC_DDR3A_EDQ16 SOC_DDR3A_EDQ17 SOC_DDR3A_EDQ18 SOC_DDR3A_EDQ19 SOC_DDR3A_EDQ20 SOC_DDR3A_EDQ21 SOC_DDR3A_EDQ22 SOC_DDR3A_EDQ23 SOC_DDR3A_EDQ24 SOC_DDR3A_EDQ25 SOC_DDR3A_EDQ26 SOC_DDR3A_EDQ27 SOC_DDR3A_EDQ28 SOC_DDR3A_EDQ29 SOC_DDR3A_EDQ30 SOC_DDR3A_EDQ31 SOC_DDR3A_EDQ32 SOC_DDR3A_EDQ33 SOC_DDR3A_EDQ34 SOC_DDR3A_EDQ35 SOC_DDR3A_EDQ36 SOC_DDR3A_EDQ37 SOC_DDR3A_EDQ38 SOC_DDR3A_EDQ39 B G1 H2 F1 G2 H1 E2 F2 D2 E4 F4 G3 A4 B4 H3 D3 D4 G4 H5 D5 F5 G5 D6 C5 B6 C7 F7 F6 A8 B8 G6 G7 D7 E16 G16 F16 G17 D16 D17 F17 E18 DDR3AD00 DDR3AD01 DDR3AD02 DDR3AD03 DDR3AD04 DDR3AD05 DDR3AD06 DDR3AD07 DDR3AD08 DDR3AD09 DDR3AD10 DDR3AD11 DDR3AD12 DDR3AD13 DDR3AD14 DDR3AD15 DDR3AD16 DDR3AD17 DDR3AD18 DDR3AD19 DDR3AD20 DDR3AD21 DDR3AD22 DDR3AD23 DDR3AD24 DDR3AD25 DDR3AD26 DDR3AD27 DDR3AD28 DDR3AD29 DDR3AD30 DDR3AD31 DDR3AD32 DDR3AD33 DDR3AD34 DDR3AD35 DDR3AD36 DDR3AD37 DDR3AD38 DDR3AD39 TI_TMS320TCI6638 DDR3AD40 DDR3AD41 DDR3AD42 DDR3AD43 DDR3AD44 DDR3AD45 DDR3AD46 DDR3AD47 DDR3AD48 DDR3AD49 DDR3AD50 DDR3AD51 DDR3AD52 DDR3AD53 DDR3AD54 DDR3AD55 DDR3AD56 DDR3AD57 DDR3AD58 DDR3AD59 DDR3AD60 DDR3AD61 DDR3AD62 DDR3AD63 DDR3ADQM0 DDR3ADQM1 DDR3ADQM2 DDR3ADQM3 DDR3ADQM4 DDR3ADQM5 DDR3ADQM6 DDR3ADQM7 DDR3ADQM8 DDR3ACB00 DDR3ACB01 DDR3ACB02 DDR3ACB03 DDR3ACB04 DDR3ACB05 DDR3ACB06 DDR3ACB07 C19 D19 G18 F19 G19 B18 D18 F18 A20 B20 D20 G20 C21 E20 F20 G21 C23 G22 D23 F22 E22 B22 F21 D22 SOC_DDR3A_EDQ40 SOC_DDR3A_EDQ41 SOC_DDR3A_EDQ42 SOC_DDR3A_EDQ43 SOC_DDR3A_EDQ44 SOC_DDR3A_EDQ45 SOC_DDR3A_EDQ46 SOC_DDR3A_EDQ47 SOC_DDR3A_EDQ48 SOC_DDR3A_EDQ49 SOC_DDR3A_EDQ50 SOC_DDR3A_EDQ51 SOC_DDR3A_EDQ52 SOC_DDR3A_EDQ53 SOC_DDR3A_EDQ54 SOC_DDR3A_EDQ55 SOC_DDR3A_EDQ56 SOC_DDR3A_EDQ57 SOC_DDR3A_EDQ58 SOC_DDR3A_EDQ59 SOC_DDR3A_EDQ60 SOC_DDR3A_EDQ61 SOC_DDR3A_EDQ62 SOC_DDR3A_EDQ63 B C2 F3 A6 E6 C17 A18 D21 A22 E14 A16 C15 B16 F15 D15 F14 D14 G15 OUT OUT OUT OUT OUT OUT OUT OUT OUT SOC_DDR3A_ECC0 SOC_DDR3A_ECC1 SOC_DDR3A_ECC2 SOC_DDR3A_ECC3 SOC_DDR3A_ECC4 SOC_DDR3A_ECC5 SOC_DDR3A_ECC6 SOC_DDR3A_ECC7 SOC_DDR3A_EDM_0 SOC_DDR3A_EDM_1 SOC_DDR3A_EDM_2 SOC_DDR3A_EDM_3 SOC_DDR3A_EDM_4 SOC_DDR3A_EDM_5 SOC_DDR3A_EDM_6 SOC_DDR3A_EDM_7 SOC_DDR3A_EDM_8 BI 30 30 30 30 30 30 30 30 30 SOC_DDR3A_ECC[0..7] 30 12 of 26 TI_TMS320TCI6638 <Characteristic> A A DSPM-8305E Designed for TI by ADVANTECH Title SOC_DDR3A Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 16 of 43 5 4 3 2 1 U24V 28 28 28 28 28 28 28 28 29 28 28 28 28 28 28 28 28 29 D SOC_DDR3B_EDQSN_0 SOC_DDR3B_EDQSN_1 SOC_DDR3B_EDQSN_2 SOC_DDR3B_EDQSN_3 SOC_DDR3B_EDQSN_4 SOC_DDR3B_EDQSN_5 SOC_DDR3B_EDQSN_6 SOC_DDR3B_EDQSN_7 SOC_DDR3B_EDQSN_8 SOC_DDR3B_EDQSP_0 SOC_DDR3B_EDQSP_1 SOC_DDR3B_EDQSP_2 SOC_DDR3B_EDQSP_3 SOC_DDR3B_EDQSP_4 SOC_DDR3B_EDQSP_5 SOC_DDR3B_EDQSP_6 SOC_DDR3B_EDQSP_7 SOC_DDR3B_EDQSP_8 28,29 28,29 28,29 SOC_DDR3B_EBA_0 SOC_DDR3B_EBA_1 SOC_DDR3B_EBA_2 TI_TMS320TCI6638 M39 P38 T38 V38 AF39 AJ38 AL38 AN39 AE38 M38 P39 T39 V39 AF38 AJ39 AL39 AN38 AE39 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT DDR3BDQS0N DDR3BDQS1N DDR3BDQS2N DDR3BDQS3N DDR3BDQS4N DDR3BDQS5N DDR3BDQS6N DDR3BDQS7N DDR3BDQS8N DDR3BDQS0P DDR3BDQS1P DDR3BDQS2P DDR3BDQS3P DDR3BDQS4P DDR3BDQS5P DDR3BDQS6P DDR3BDQS7P DDR3BDQS8P AA37 AA34 AB35 OUT OUT OUT DDR3BA00 DDR3BA01 DDR3BA02 DDR3BA03 DDR3BA04 DDR3BA05 DDR3BA06 DDR3BA07 DDR3BA08 DDR3BA09 DDR3BA10 DDR3BA11 DDR3BA12 DDR3BA13 DDR3BA14 DDR3BA15 AA32 W33 W32 Y34 W34 V34 W36 W37 AA33 Y32 Y38 AA39 Y35 Y39 AA38 Y36 SOC_DDR3B_EA0 SOC_DDR3B_EA1 SOC_DDR3B_EA2 SOC_DDR3B_EA3 SOC_DDR3B_EA4 SOC_DDR3B_EA5 SOC_DDR3B_EA6 SOC_DDR3B_EA7 SOC_DDR3B_EA8 SOC_DDR3B_EA9 SOC_DDR3B_EA10 SOC_DDR3B_EA11 SOC_DDR3B_EA12 SOC_DDR3B_EA13 SOC_DDR3B_EA14 SOC_DDR3B_EA15 OUT SOC_DDR3B_EA[0..15] 28,29 U24U TI_TMS320TCI6638 28,29 SOC_DDR3B_EODT_0 OUT 28,29 28,29 SOC_DDR3B_ECAS# SOC_DDR3B_ERAS# OUT OUT 28,29 SOC_DDR3B_EWE# OUT 28,29 28,29 28,29 SOC_DDR3B_EMRESETN SOC_DDR3B_ECKN_0 SOC_DDR3B_ECKP_0 AC33 AD34 AC36 AD32 AC37 R470 4.7K AC32 OUT AD39 AD38 OUT OUT AC38 AC39 TP56 TP54 DDR3BBA0 DDR3BBA1 DDR3BBA2 TP55 TP53 DDR3BPLLOBSCLKN AP39 DDR3BPLLOBSCLKP AP38 DDR3BODT0 DDR3BODT1 RSV032 DDR3BCAS DDR3BRAS DDR3BCKE0 DDR3BCKE1 DDR3BWE DDR3BCE0 DDR3BCE1 DDR3BRESET RSV030 RSV031 DDR3BCLKOUTN0 DDR3BCLKOUTP0 DDR3BCLKOUTN1 DDR3BCLKOUTP1 DDR3BRZQ0 DDR3BRZQ1 DDR3BRZQ2 AB32 DDR3BATO D TP88 AB39 AB38 OUT SOC_DDR3B_ECKE_0 28,29 AB34 AA36 OUT SOC_DDR3B_ECS_0# 28,29 AD35 AC34 AA31 P32 AK32 TP91 TP89 R716 R719 RR1 240 1% 240 1% 240 1% DDR3BPLLOBSCLKN DDR3BPLLOBSCLKP 21 of 26 TI_TMS320TCI6638 <Characteristic> 22 of 26 TI_TMS320TCI6638 <Characteristic> C C U24W 28 28 SOC_DDR3B_EDQ[0..7] BI SOC_DDR3B_EDQ[8..15] BI 28 SOC_DDR3B_EDQ[16..23] BI 28 SOC_DDR3B_EDQ[24..31] BI B 28 SOC_DDR3B_EDQ[32..39] BI SOC_DDR3B_EDQ0 SOC_DDR3B_EDQ1 SOC_DDR3B_EDQ2 SOC_DDR3B_EDQ3 SOC_DDR3B_EDQ4 SOC_DDR3B_EDQ5 SOC_DDR3B_EDQ6 SOC_DDR3B_EDQ7 SOC_DDR3B_EDQ8 SOC_DDR3B_EDQ9 SOC_DDR3B_EDQ10 SOC_DDR3B_EDQ11 SOC_DDR3B_EDQ12 SOC_DDR3B_EDQ13 SOC_DDR3B_EDQ14 SOC_DDR3B_EDQ15 SOC_DDR3B_EDQ16 SOC_DDR3B_EDQ17 SOC_DDR3B_EDQ18 SOC_DDR3B_EDQ19 SOC_DDR3B_EDQ20 SOC_DDR3B_EDQ21 SOC_DDR3B_EDQ22 SOC_DDR3B_EDQ23 SOC_DDR3B_EDQ24 SOC_DDR3B_EDQ25 SOC_DDR3B_EDQ26 SOC_DDR3B_EDQ27 SOC_DDR3B_EDQ28 SOC_DDR3B_EDQ29 SOC_DDR3B_EDQ30 SOC_DDR3B_EDQ31 SOC_DDR3B_EDQ32 SOC_DDR3B_EDQ33 SOC_DDR3B_EDQ34 SOC_DDR3B_EDQ35 SOC_DDR3B_EDQ36 SOC_DDR3B_EDQ37 SOC_DDR3B_EDQ38 SOC_DDR3B_EDQ39 L38 N34 M37 L39 N33 N37 N36 N38 T32 R32 P35 R39 R38 N32 R33 P36 T34 R34 T35 R37 R36 U37 T36 U38 V35 U36 U34 W38 W39 U33 V32 V36 AG37 AF36 AG38 AG34 AG36 AH34 AH35 AG32 TI_TMS320TCI6638 DDR3BD00 DDR3BD01 DDR3BD02 DDR3BD03 DDR3BD04 DDR3BD05 DDR3BD06 DDR3BD07 DDR3BD08 DDR3BD09 DDR3BD10 DDR3BD11 DDR3BD12 DDR3BD13 DDR3BD14 DDR3BD15 DDR3BD16 DDR3BD17 DDR3BD18 DDR3BD19 DDR3BD20 DDR3BD21 DDR3BD22 DDR3BD23 DDR3BD24 DDR3BD25 DDR3BD26 DDR3BD27 DDR3BD28 DDR3BD29 DDR3BD30 DDR3BD31 DDR3BD32 DDR3BD33 DDR3BD34 DDR3BD35 DDR3BD36 DDR3BD37 DDR3BD38 DDR3BD39 DDR3BD40 DDR3BD41 DDR3BD42 DDR3BD43 DDR3BD44 DDR3BD45 DDR3BD46 DDR3BD47 DDR3BD48 DDR3BD49 DDR3BD50 DDR3BD51 DDR3BD52 DDR3BD53 DDR3BD54 DDR3BD55 DDR3BD56 DDR3BD57 DDR3BD58 DDR3BD59 DDR3BD60 DDR3BD61 DDR3BD62 DDR3BD63 DDR3BDQM0 DDR3BDQM1 DDR3BDQM2 DDR3BDQM3 DDR3BDQM4 DDR3BDQM5 DDR3BDQM6 DDR3BDQM7 DDR3BDQM8 23 of 26 DDR3BCB00 DDR3BCB01 DDR3BCB02 DDR3BCB03 DDR3BCB04 DDR3BCB05 DDR3BCB06 DDR3BCB07 AH32 AJ33 AH36 AJ34 AJ36 AH39 AH38 AJ37 AK39 AK38 AK36 AK35 AL34 AL36 AL37 AL33 AN34 AN36 AN33 AM34 AM35 AM38 AM36 AN37 N39 P34 U39 U32 AG33 AG39 AK34 AM39 AE37 AF32 AF34 AE32 AF35 AE33 AE36 AD36 AE34 BI SOC_DDR3B_EDQ40 SOC_DDR3B_EDQ41 SOC_DDR3B_EDQ42 SOC_DDR3B_EDQ43 SOC_DDR3B_EDQ44 SOC_DDR3B_EDQ45 SOC_DDR3B_EDQ46 SOC_DDR3B_EDQ47 SOC_DDR3B_EDQ48 SOC_DDR3B_EDQ49 SOC_DDR3B_EDQ50 SOC_DDR3B_EDQ51 SOC_DDR3B_EDQ52 SOC_DDR3B_EDQ53 SOC_DDR3B_EDQ54 SOC_DDR3B_EDQ55 SOC_DDR3B_EDQ56 SOC_DDR3B_EDQ57 SOC_DDR3B_EDQ58 SOC_DDR3B_EDQ59 SOC_DDR3B_EDQ60 SOC_DDR3B_EDQ61 SOC_DDR3B_EDQ62 SOC_DDR3B_EDQ63 28 BI SOC_DDR3B_EDQ[48..55] 28 BI SOC_DDR3B_EDQ[56..63] 28 SOC_DDR3B_ECKP_0 R445 39.2 1% SOC_DDR3B_ECKN_0 R443 39.2 1% C364 0.1uF 16V VCC1V5 Place these resistors at the end of the trace. VCCB0V75 OUT OUT OUT OUT OUT OUT OUT OUT OUT SOC_DDR3B_ECC0 SOC_DDR3B_ECC1 SOC_DDR3B_ECC2 SOC_DDR3B_ECC3 SOC_DDR3B_ECC4 SOC_DDR3B_ECC5 SOC_DDR3B_ECC6 SOC_DDR3B_ECC7 SOC_DDR3B_EDQ[40..47] SOC_DDR3B_EDM_0 SOC_DDR3B_EDM_1 SOC_DDR3B_EDM_2 SOC_DDR3B_EDM_3 SOC_DDR3B_EDM_4 SOC_DDR3B_EDM_5 SOC_DDR3B_EDM_6 SOC_DDR3B_EDM_7 SOC_DDR3B_EDM_8 BI SOC_DDR3B_ECC[0..7] TI_TMS320TCI6638 <Characteristic> 28 28 28 28 28 28 28 28 29 29 SOC_DDR3B_EA0 R464 39.2 1% C794 SOC_DDR3B_EA1 R790 39.2 1% C374 SOC_DDR3B_EA2 R782 39.2 1% SOC_DDR3B_EA3 R462 39.2 1% SOC_DDR3B_EA4 R781 39.2 SOC_DDR3B_EA5 R792 SOC_DDR3B_EA6 VCCB0V75 0.01uF 16V SOC_DDR3B_EBA_0 R775 39.2 1% C757 0.01uF 16V 0.1uF 16V SOC_DDR3B_EBA_1 R465 39.2 1% C356 0.1uF 16V C756 0.01uF 16V SOC_DDR3B_EBA_2 R454 39.2 1% C784 0.01uF 16V C361 0.1uF 16V SOC_DDR3B_EODT_0 R765 39.2 1% C793 0.1uF 16V 1% C766 0.01uF 16V SOC_DDR3B_EWE# R779 39.2 1% C761 0.01uF 16V 39.2 1% C379 0.1uF 16V SOC_DDR3B_ERAS# R763 39.2 1% C378 0.1uF 16V R463 39.2 1% SOC_DDR3B_ECAS# R457 39.2 1% SOC_DDR3B_EA7 R467 39.2 1% SOC_DDR3B_ECKE_0 R772 39.2 1% SOC_DDR3B_EA8 R788 39.2 1% SOC_DDR3B_ECS_0# R786 39.2 1% SOC_DDR3B_EA9 R795 39.2 1% SOC_DDR3B_EA10 R455 39.2 1% SOC_DDR3B_EA11 R789 39.2 1% SOC_DDR3B_EA12 R458 39.2 1% SOC_DDR3B_EA13 R794 39.2 1% SOC_DDR3B_EA14 R466 39.2 1% SOC_DDR3B_EA15 R444 39.2 1% A B A DSPM-8305E Designed for TI by ADVANTECH Title SOC_DDR3B Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 17 of 43 5 4 TIMER0,1, SPI, UART,I2C 3 2 VCC1V8 SOC_SIM_IO 4.7K VCC1V8 1 VCC3V3_AUX 1M-bit I2C EEPROM 0x50h/0x51h R714 VCC1V8 U24R C494 0.1uF 16V TI_TMS320TCI6638 NOR_SSPCS TP80 TP82 TP81 SOC_SSP0_MOSI R368 R363 VCC1V8 D SOC_SSP0_CLK 25 10 SOC_SSPMOSI_R 4.7K SOC_SSP0_MISO 25 OUT OUT OUT OUT OUT IN OUT SOC_SSP2_CS0 SOC_SSP2_CS1 SOC_SSP2_CS2 SOC_SSP2_CS3 SOC_SSP2_MOSI SOC_SSP2_MISO SOC_SSP2_CLK SOC_SSPCK_R R367 10 10 OUT SPI1DIN OUT R372 R691 R373 R690 R692 22 22 22 22 22 R369 22 SPI0SCS0 SPI0SCS1 SPI0SCS2 SPI0SCS3 SPI0DOUT SPI0DIN SPI0CLK B27 C27 D27 E27 A28 F27 C28 OUT SOC_SSP1_CS0 TP84 TP85 TP87 SOC_SSP1_MOSI TP83 SOC_SSP1_CLK 25 39 39 39 39 39 39 39 R364 F25 C25 E26 D26 A27 A26 B26 UART0CTS UART0RTS UART0RXD UART0TXD UART1CTS UART1RTS UART1RXD UART1TXD SPI1SCS0 SPI1SCS1 SPI1SCS2 SPI1SCS3 SPI1DOUT SPI1DIN SPI1CLK B28 D28 A29 E25 G28 F28 D25 USIMIO USIMCLK USIMRST TIMI0 TIMI1 TIMO0 TIMO1 SPI2SCS0 SPI2SCS1 SPI2SCS2 SPI2SCS3 SPI2DOUT SPI2DIN SPI2CLK L1 L4 K4 K2 K1 M5 L2 K3 R315 UART1_RTS_R UART1_RXD_M UART1_TXD_R SOC_UART1_CTS_V1P8 SOC_UART1_RTS_V1P8 10 SOC_UART1_TXD_1V8 BI OUT OUT SOC_TIMI0 SOC_TIMI1 SOC_TIMO0_R SOC_TIMO1_R M2 M1 M3 M4 10 R316 SOC_SIM_IO AP33 AN32 AP32 SOC_UART1_RTS_V1P8 SOC_UART0_TXD_V1P8 SOC_UART1_CTS_V1P8 SOC_UART0_RXD_V1P8 SOC_SIM_IO SOC_SIM_CLK SOC_SIM_RST VCCB 1OE 2OE 1B1 1B2 2B1 2B2 GND2 VCC1V8 1 2 3 4 OUT 5 OUT 6 IN 7SOC_UART0_RXD_3V3 8 VCCA 1DIR 2DIR 1A1 1A2 2A1 2A2 GND1 TI_SN74AVC4T245PWR 35 R326 NL/0 SOC_UART1_RTS_3V3 SOC_UART0_TXD_3V3 SOC_UART1_CTS_3V3 1 2 3 4 OUT OUT SOC_TIMO0 SOC_TIMO1 12,39 35,39 VCC3V3_AUX 31 FTDI_SOC_U0RX A B Y GND 8 7 6 5 20 39 SOC_GPIO_10 SOC_TIMI0_B EXT_TIMO1 EXP_TIMO1 EXT_TIMO1 EXP_TIMO1 IN IN 1 2 3 4 TI_SN74LVC2G157DCUT <Characteristic> C 1 2 3 4 A B Y GND 8 7 6 5 VCC G A/B Y A B Y GND VCC G A/B Y 8 7 6 5 SOC_UART1_RXD_1V8 GPS_UARTRXD SOC_UART1_RXD_1V8 1 GPS_UARTRXD 2 3 4 IN IN SOC_GPIO_09 SOC_TIMI1_B 8 SOC_TIMI1_B U28B 3 5 4 7 8 4 1 SOC_TIMI0 IN TIMI_MUX_OEz 13,18 EEPROM_WPz 13 8 7 6 5 VCC G A/B Y R604 4.7K 1% R610 4.7K 1% VCCA SCLA SDAA GND 1 SOC_UART1_TXD_1V8 MCU_EXP_SCL MCU_EXP_SDA SOC_I2C_EN 36 36 36 SOC_GPIO_08 UART1_RXD_M VCC3V3_MP 3 6 Y0 GND E OUT 5 VCC 4 Y1 EXP_UARTTXD 13 VCC3V3_MP C394 0.1uF 16V 3.3V I2C isolator OUT GPS_UARTTXD 1 2 3 4 MCU_EXP_SCL MCU_EXP_SDA VCC1V8 35 VCC3V3_MP TI_SN74LVC1G19DCKR <Characteristic> TIMI_MUX_OEz OUT BI IN R317 0 C U22 A SOC_TIMI1 IN 8 7 6 5 VCCB SCLB SDAB EN TI_PCA9517DR <Characteristic> U26 TI_SN74LVC2G125DCUR <Characteristic> TIMI_MUX_OEz R611 0 U58 1 2 3 4 SOC_SCL0 SOC_SDA0 C180 0.1uF 16V 2 TI_SN74LVC2G125DCUR <Characteristic> TIMI_MUX_OEz A B Y GND C398 0.1uF 16V SCL/SDA TI_SN74LVC2G157DCUT <Characteristic> SOC_GPIO_11 2 IN TI_SN74LVC2G157DCUT <Characteristic> VCC1V8 SOC_TIMI0_B R324 4.7K VCC3V3_MP C495 0.1uF 16V SOC_UART0_Detect SOC_UART0_RXD_3V3 U21 35 VCC1V8 U28A 6 D U55 SOC_URX_3V3 FTDI_SOC_U0RX IN VCC1V8 U17 VCC G A/B Y ST_M24M01-RMN6TP <Characteristic> VCC1V8 13 1 2 3 4 EEPROM_WPz SOC_SCL0 SOC_SDA0 VCC1V8 TI_SN74LVC2G157DCUT <Characteristic> VCC1V8 AMC_TIMO0 EXP_TIMO0 R323 0 8 7 6 5 VCC WC SCL SDA R312 R313 U30 IN IN DU E1 E2 VSS VCC1V8 R311SOC_TIMO0 R314SOC_TIMO1 10 10 VCC1V8 AMC_TIMO0 EXP_TIMO0 C205 0.1uF 16V EEPROM1 R325 0 18 of 26 TI_TMS320TCI6638 <Characteristic> 12 39 R322 NL/0 39 31,36 39 R587 4.7K 35 35 SOC_SDA0 SOC_SCL0 SOC_SDA1 SOC_SCL1 SOC_SDA2 SOC_SCL2 P3 N1 N2 N4 N3 P4 16 15 14 13 12 11 10 9 SOC_UART0_RXD_V1P8 SOC_UART0_TXD_V1P8 10 R619 4.7K 4.7K SDA0 SCL0 SDA1 SCL1 SDA2 SCL2 U57 TP44 TP66 UART0_TXD_R C487 0.1uF 16V R297 4.7K 1% R306 4.7K 1% VCCA SCLA SDAA GND VCCB SCLB SDAB EN 8 7 6 5 OUT BI IN PW_SEQ_SCL PW_SEQ_SDA PW_SEQ_I2C_EN OUT BI DIMM_SCL DIMM_SDA 37 37 36 TI_PCA9517DR <Characteristic> 13,18 VCC1V8 VCC3V3_AUX SCL/SDA GPIO C347 0.1uF 16V VCC3V3_AUX C334 0.1uF 16V U24I TI_TMS320TCI6638 B 13,39 13,39 13,39 13,39 13,39 13,39 13,39 13,39 13,39 13,39 13,39 13,39 13,39 13,39 13,39 13,39 13,39 SOC_GPIO_00 SOC_GPIO_01 SOC_GPIO_02 SOC_GPIO_03 SOC_GPIO_04 SOC_GPIO_05 SOC_GPIO_06 SOC_GPIO_07 SOC_GPIO_08 SOC_GPIO_09 SOC_GPIO_10 SOC_GPIO_11 SOC_GPIO_12 SOC_GPIO_13 SOC_GPIO_14 SOC_GPIO_15 SOC_GPIO_16 R374 R388 R703 R396 R383 R697 R712 R387 R384 R708 R724 R718 R722 R391 R732 R393 R398 BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI SOC_GPIO_R00 SOC_GPIO_R01 SOC_GPIO_R02 SOC_GPIO_R03 SOC_GPIO_R04 SOC_GPIO_R05 SOC_GPIO_R06 SOC_GPIO_R07 SOC_GPIO_R08 SOC_GPIO_R09 SOC_GPIO_R10 SOC_GPIO_R11 SOC_GPIO_R12 SOC_GPIO_R13 SOC_GPIO_R14 SOC_GPIO_R15 SOC_GPIO_R16 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 F29 B30 D29 A35 B29 E29 D30 C30 A30 G30 F31 E30 F30 A31 E32 B31 A36 GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 R291 4.7K VCC1V8 SOC_GPIO_R00 SOC_GPIO_R01 SOC_GPIO_R02 SOC_GPIO_R03 SOC_GPIO_R04 SOC_GPIO_R05 SOC_GPIO_R06 SOC_GPIO_R07 SOC_GPIO_R08 SOC_GPIO_R09 SOC_GPIO_R10 SOC_GPIO_R11 SOC_GPIO_R12 SOC_GPIO_R13 SOC_GPIO_R14 SOC_GPIO_R15 SOC_GPIO_R16 9 of 26 TI_TMS320TCI6638 <Characteristic> R701 R713 R702 R734 R707 R696 R389 R711 R706 R385 R723 R720 R721 R390 R731 R394 R739 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K SOC_PORZ R629 SOC_PORZ C802 0.1uF 16V C803 0.01uF C129 C130 0.1uF 16V 0.1uF 16V C128 0.1uF 16V C127 0.1uF 16V SOC_RS232_RX C804 4.7K SOC_RESETFULLZ R625 1K SOC_RESETZ R620 1K 1000pF 1 2 3 4 5 6 7 8 EN C1+ V+ C1C2+ C2VRIN FORCEOFF VCC GND DOUT FORCEON DIN INVALID ROUT SOC_RESETZ C808 0.1uF 16V C809 0.01uF 50V C810 C164 0.1uF 16V U34 13 13 1 2 3 4 SOC_SCL1 OUT SOC_SDA1 BI SOC_SCL1 SOC_SDA1 VCC1V8 16 15 14 13 12 11 10 9 R422 4.7K 1% R429 4.7K 1% VCCA SCLA SDAA GND TI_PCA9517DR <Characteristic> C474 0.1uF 16V SOC_RS232_RX SOC_RS232_TX 4 3 2 1 1 2 3 4 SOC_SCL2 SOC_SDA2 R220 4.7K VCC1V8 R572 4.7K 1% R570 1000pF 50V TI_PCA9517DR <Characteristic> 4.7K 1% 3 SOC_BOOTCOMPLETE 13 SOC_GPIO_12 13 13 13 13,36 13 SOC_PORZ SOC_RESETZ SOC_LRESETZ SOC_RESETFULLZ SOC_RESETSTATZ SOC_LRESETNMIENZ 13 TP41 SOC_PLLLOCK IN IN IN IN OUT IN OUT SOCCLKSEL_R AL4 AN30 AK1 AK4 AD2 AE4 AD3 AC5 AD4 P1 AK5 R522 510 1 1% G 1R70 56 0.2A CORECLKSEL PACLKSEL NMI HOUT SYSCLKOUT RSV000 AD5 AE5 P2 IN SOC_NMIZ OUT R510 13 1 510 1% SOC Debug LED0 Note: SOC_HOUT 13 0.2A RED GPIO12 GPIO13 R534 10 GREEN VCC3V3_AUX R SOC_GPIO_14 RSV013 RSV014 DBG_D2 2 1 TP62 F23 E23 COLOR Q4 MMBT3904LT1G POR RESET LRESET RESETFULL RESETSTAT RSV001 RSV012 R525 510 1 1% TP77 TP78 R569 4.7K 1% 12,39 12,39 VCC3V3_AUX 128Mb SPI NOR Flash KPA-1606QBC-D <Characteristic> SOC Debug LED1 36 Note:LED Color is BLUE Q16 MMBT3904LT1G 0.1uF 16V NOR1 2 NOR_HD# 1 NOR_SSPCS 7 SOC_SSP0_CLK 16 SOC_SSP0_MOSI 15 SOC_SSP0_MISO R558 8 10 NOR_WPz 9 R530 4.7K 10 NOR_WPz IN VCC HOLD/DQ3 S SCK DQ0 DQ1 W/Vpp/DQ2 VSS DU/NC8 DU/NC7 DU/NC6 DU/NC5 DU/NC4 DU/NC3 DU/NC2 DU/NC1 14 13 12 11 6 5 4 3 A NUMONYX_N25Q128A11ESF40F <Characteristic> 0.2A C812 DBG_D3 2 1 0.1uF 16V DSPM-8305E Designed for TI by ADVANTECH R111 10 VCC3V3_AUX R C811 C813 0.01uF 1000pF 16V 50V SOC_GPIO_15 R76 14 of 26 TI_TMS320TCI6638 <Characteristic> 510 1 1% KPA-1606QBC-D <Characteristic> Q5 MMBT3904LT1G SOC Debug LED2 Note:LED Color is BLUE Title SOC_MISC Size 0.2A C Date: 5 4.7K 1% C720 R733 4.7K LRESETNMIEN SOC_RESETFULLZ R571 VCC1V8 5% VCC3V3_AUX R Q14 KPBA-3010ESGC <Characteristic> MMBT3904LT1G 2 R622 TP42 13 A 3 2 3 0 EXP_SCL2_3V3 EXP_SDA2_3V3 2 IN IN SWAP OUT BI SOC_UART0_Detect 3 SOC_CORECLKSEL SOC_PACLKSEL 8 7 6 5 VCCB SCLB SDAB EN W_4V_2.54mm <Characteristic> SOC_GPIO_13 13 13 VCCA SCLA SDAA GND 16V 2 BOOTCOMPLETE OUT R586 0 U54 3 CORESEL0 CORESEL1 CORESEL2 CORESEL3 AF5 VCC3V3_AUX B C456 0.1uF 16V 2 F24 E24 D24 G24 4.7K 1% VCC3V3_AUX DBG_D1 IN IN IN IN 4.7K 1% R424 30 30 SCL/SDA VCC3V3_AUX TI_TMS320TCI6638 SOC_CORESEL0 SOC_CORESEL1 SOC_CORESEL2 SOC_CORESEL3 R420 VCC1V8 SOC_UART0_TXD_3V3 R289 4.7K TI_MAX3221ECPWR U24N 13 13 13 13 8 7 6 5 VCCB SCLB SDAB EN SOC_RS232_TX SOC_URX_3V3 H1 SOC 16V C165 1uF 6.3V U18 NPTH Core Control R290 4.7K R409 0 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 18 of 43 5 4 SOC_TCK R798 100 1% SOC EMIF C796 20pF 50V C797 20pF 50V D AA2 AB2 Y3 Y4 W3 W4 V4 U4 U3 T3 AB4 AA3 U5 T4 AB3 R3 T5 R4 AA4 SOC_TMS SOC_TDI SOC_TDO SOC_TCK AE2 AG1 AF1 AE1 SOC_TRST# A32 C31 B32 A33 D33 D31 B35 B33 E31 A34 D32 C33 C34 B36 B34 EMIFWAIT0 R25 470 EMIFA00 EMIFA01 EMIFA02 EMIFA03 EMIFA04 EMIFA05 EMIFA06 EMIFA07 EMIFA08 EMIFA09 EMIFA10 EMIFA11 EMIFA12 EMIFA13 EMIFA14 EMIFA15 EMIFA16 EMIFA17 EMIFA18 EMIFA19 EMIFA20 EMIFA21 EMIFA22 EMIFA23 EMU00 EMU01 EMU02 EMU03 EMU04 EMU05 EMU06 EMU07 EMU08 EMU09 EMU10 EMU11 EMU12 EMU13 EMU14 EMU15 EMU16 EMU17 EMU18 TMS TDI TDO TCK EMIFBE0 EMIFBE1 TRST EMIFCE0 EMIFCE1 EMIFCE2 EMIFCE3 EMIFD00 EMIFD01 EMIFD02 EMIFD03 EMIFD04 EMIFD05 EMIFD06 EMIFD07 EMIFD08 EMIFD09 EMIFD10 EMIFD11 EMIFD12 EMIFD13 EMIFD14 EMIFD15 GPIO17/EMU19 GPIO18/EMU20 GPIO19/EMU21 GPIO20/EMU22 GPIO21/EMU23 GPIO22/EMU24 GPIO23/EMU25 GPIO24/EMU26 GPIO25/EMU27 GPIO26/EMU28 GPIO27/EMU29 GPIO28/EMU30 GPIO29/EMU31 GPIO30/EMU32 GPIO31/EMU33 EMIFOE EMIFRNW EMIFWAIT0 EMIFWAIT1 EMIFWE F34 F37 G36 E39 E34 J34 H35 K33 C35 G37 F38 D35 H36 E35 G38 F39 K34 F35 J35 G39 C36 J36 H38 D36 EMIFA00 EMIFA01 EMIFA02 EMIFA03 EMIFA04 EMIFA05 EMIFA06 EMIFA07 EMIFA08 EMIFA09 EMIFA10 EMIFA11 EMIFA12 EMIFA13 EMIFA14 EMIFA15 EMIFA16 EMIFA17 EMIFA18 EMIFA19 EMIFA20 EMIFA21 EMIFA22 EMIFA23 EMIFA00 EMIFA01 EMIFA02 EMIFA03 H34 H33 EMIFBE0Z EMIFBE1Z G33 G32 G34 E36 EMIFCE0Z R27 EMIFCE1Z EMIFCE2Z EMIFCE3Z M32 J37 L33 L34 H39 J38 K37 J39 K39 K38 K36 L36 L35 M34 M36 M35 EMIFD0 EMIFD1 EMIFD2 EMIFD3 EMIFD4 EMIFD5 EMIFD6 EMIFD7 EMIFD8 EMIFD9 EMIFD10 EMIFD11 EMIFD12 EMIFD13 EMIFD14 EMIFD15 E37 EMIFOEZ F33 EMIFRNW EMIFA04 EMIFA05 EMIFA06 EMIFA07 41 40 38 37 EMIFA08 EMIFA09 EMIFA10 EMIFA11 36 35 33 32 EMIFA12 EMIFA13 EMIFA14 EMIFA15 30 29 27 26 1 48 25 24 4 10 15 21 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 1OE 2OE 3OE 4OE VCC_1 VCC_2 VCC_3 VCC_4 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 OUT OUT OUT OUT SOC_EMIFA00 SOC_EMIFA01 SOC_EMIFA02 SOC_EMIFA03 39 39 39 39 OUT OUT OUT OUT SOC_EMIFA04 SOC_EMIFA05 SOC_EMIFA06 SOC_EMIFA07 39 39 39 39 OUT OUT OUT OUT SOC_EMIFA08 SOC_EMIFA09 SOC_EMIFA10 SOC_EMIFA11 39 39 39 39 OUT OUT OUT OUT SOC_EMIFA12 SOC_EMIFA13 SOC_EMIFA14 SOC_EMIFA15 39 39 39 39 7 18 31 42 C841 1uF 6.3V 28 34 39 45 H1 R33 R37 R43 EMU_TCK EMU_TDI VCC1V8 C835 0.1uF 16V EMU1 VCC1V8 22 SOC_EMIFCE0Z SOC_TVD EMU_TCK_R EMU_TDI_R EMU_TCKRTN 100 10 10 SOC_EMU_02 R47 10 SOC_EMU_03 EMU_EMU_00 EMU_EMU_01 SOC_EMU_04 SOC_EMU_05 SOC_EMU_06 SOC_EMU_07 SOC_EMU_08 SOC_EMU_09 SOC_EMU_10 SOC_EMU_11 SOC_EMU_12 SOC_EMU_13 SOC_EMU_14 SOC_EMU_15 SOC_EMU_16 SOC_EMU_17 SOC_EMU_18 SOC_EMU_19 SOC_EMU_20 R53 R62 R516 R520 R66 R523 R527 R71 R78 R529 R532 R535 R87 R539 R94 R103 R109 R542 R157 R158 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 SOC_EMU_02_R R54 0 T_TDIS SOC_EMU_03_R EMU_EMU_00_R EMU_EMU_01_R SOC_EMU_04_R SOC_EMU_05_R SOC_EMU_06_R SOC_EMU_07_R SOC_EMU_08_R SOC_EMU_09_R SOC_EMU_10_R SOC_EMU_11_R SOC_EMU_12_R SOC_EMU_13_R SOC_EMU_14_R SOC_EMU_15_R SOC_EMU_16_R SOC_EMU_17_R SOC_EMU_18_R SOC_EMU_19_R SOC_EMU_20_R TI_SN74AUCH16244DGGR 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 EMU_TMS_R EMU_TDO_R 10 10 EMU_TRST#_R SOC_TVD 4.7K 10 SOC_EMU_21_R SOC_EMU_22_R SOC_EMU_23_R SOC_EMU_24_R SOC_EMU_25_R SOC_EMU_26_R SOC_EMU_27_R SOC_EMU_28_R SOC_EMU_29_R SOC_EMU_30_R SOC_EMU_31_R SOC_EMU_32_R SOC_EMU_33_R 10 10 10 10 10 10 10 10 10 10 10 10 10 1% 4.75K EMU_TMS EMU_TDO R44 R49 D OUT VCC1V8 EMU_TRST# R56 R57 R63 R64 R67 R68 R72 R73 R79 R80 R89 R90 R96 R97 R104 R112 TRGRSTZ 36 SOC_EMU_21 SOC_EMU_22 SOC_EMU_23 SOC_EMU_24 SOC_EMU_25 SOC_EMU_26 SOC_EMU_27 SOC_EMU_28 SOC_EMU_29 SOC_EMU_30 SOC_EMU_31 SOC_EMU_32 SOC_EMU_33 VCC3V3_AUX EXT_EMU_DET E38 D39 EMIFWAIT0 EMIFWAIT1 F36 EMIFWEZ U64 EMIFA16 EMIFA17 EMIFA18 EMIFA19 47 46 44 43 EMIFA20 EMIFA21 EMIFA22 EMIFA23 41 40 38 37 EMIFBE0Z EMIFBE1Z EMIFCE1Z EMIFCE2Z 36 35 33 32 EMIFCE3Z EMIFRNW EMIFOEZ EMIFWEZ 30 29 27 26 1 48 25 24 26 of 26 TI_TMS320TCI6638 <Characteristic> 15 of 26 TI_TMS320TCI6638 <Characteristic> 47 46 44 43 16V 0.1uF 4 10 15 21 C843 U67 5 VCC1V8 EMIFWAIT1 1 2 3 VCC 4 IN SOC_EMIFWAIT1 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 1OE 2OE 3OE 4OE VCC_1 VCC_2 VCC_3 VCC_4 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 7 18 31 42 OUT OUT OUT OUT SOC_EMIFA16 SOC_EMIFA17 SOC_EMIFA18 SOC_EMIFA19 39 39 39 39 OUT OUT OUT OUT SOC_EMIFA20 SOC_EMIFA21 SOC_EMIFA22 SOC_EMIFA23 39 39 39 39 OUT OUT OUT OUT SOC_EMIFBE0Z SOC_EMIFBE1Z SOC_EMIFCE1Z SOC_EMIFCE2Z 39 39 39 39 OUT OUT OUT OUT SOC_EMIFCE3Z SOC_EMIFRNW SOC_EMIFOEZ SOC_EMIFWEZ 39 39 39 39 EMU_EMU_00 R61 4.75K EMU_EMU_01 R517 4.75K EMU_TCK BB_60V_S0.5mm <Characteristic> R215 EMU_TCK_R SOC_TCK_R R780 C VCC1V8 VCC3V3_AUX U11 VCC1V8 C837 0.1uF 16V H2 VCC1V8 60-pin Header C SOC_EMU_19 SOC_EMU_20 SOC_EMU_21 SOC_EMU_22 SOC_EMU_23 SOC_EMU_24 SOC_EMU_25 SOC_EMU_26 SOC_EMU_27 SOC_EMU_28 SOC_EMU_29 SOC_EMU_30 SOC_EMU_31 SOC_EMU_32 SOC_EMU_33 AD1 1K U63 TI_TMS320TCI6638 SOC_EMU_00 SOC_EMU_01 SOC_EMU_02 SOC_EMU_03 SOC_EMU_04 SOC_EMU_05 SOC_EMU_06 SOC_EMU_07 SOC_EMU_08 SOC_EMU_09 SOC_EMU_10 SOC_EMU_11 SOC_EMU_12 SOC_EMU_13 SOC_EMU_14 SOC_EMU_15 SOC_EMU_16 SOC_EMU_17 SOC_EMU_18 R69 TI_TMS320TCI6638 U24O 1 VCC1V8 EMIFWAIT1 U24Z Close to SOC 2 EMU CONN. H3 H4 H5 H6 EMU & JTAG 3 13 MCU_EMU_DET EXT_EMU_DET MCU_EMU_DET IN 1 2 3 C842 1uF 6.3V VCC EMU_TMS R38 4.7K EMU_TDI R42 4.7K EMU_TDO R50 4.7K EMU_TCK R36 4.7K 5 4 EXT_EMU_DET_C GND TI_SN74LVC1G32DCK <Characteristic> R32 28 34 39 45 100 1% EMU_TRST# C32 R58 10pF 4.75K 50V 1% 39 GND C805 0.1uF 16V C806 0.01uF TI_SN74AUCH16244DGGR 16V R29 4.7K EMIFOEZ EMIFWAIT0 D4 C8 SOC_EMIFCE0Z EMIFA12 C6 D5 EMIFA11 C4 VCC1V8 G3 G8 G5 R804 NL/4.7K R805 NL/4.7K A F7 K8 K3 C5 RE R/B CE CLE ALE DNU1 DNU2 LOCK G4 VSS1 VCC1 D3 VSS2 VCC2 H8 VSS3 VCC3 J6 VSS4 VCC4 MICRON_MT29F4G08ABBDAHC:D <Characteristic> 21 22 23 24 25 26 27 VCC1V8 1 2 3 VCC 5 4 20 1 DIR U69 SOC_EMIFCE0Z EMIF_OEz SOC_EMIFD0 SOC_EMIFD1 SOC_EMIFD2 SOC_EMIFD3 SOC_EMIFD4 SOC_EMIFD5 SOC_EMIFD6 13 EMU_TDO_B R472 1K 39 39 39 39 39 39 39 1% 0 R9 1 19 TI_SN74AUCH245RGYR <Characteristic> BI SOC_EMIFD7 39 U5 VCC1V8 C397 10uF 6.3V 21 22 23 24 25 26 27 A1 A2 A3 A4 A5 A6 A7 A8 EMU_EMU_00 EMU_EMU_01 48 47 42 41 35 34 29 28 C836 VCC1V8 12 12 12 12 12 OE B1 B2 B3 B4 B5 B6 B7 19 18 17 16 15 14 13 12 EMIF_OEz BI BI BI BI BI BI BI SOC_EMIFD8 SOC_EMIFD9 SOC_EMIFD10 SOC_EMIFD11 SOC_EMIFD12 SOC_EMIFD13 SOC_EMIFD14 39 39 39 39 39 39 39 AMC_JTAG_TDI AMC_JTAG_TMS AMC_JTAG_RST# AMC_JTAG_TCK AMC_JTAG_TDO IN IN IN IN OUT 45 44 39 38 32 31 26 25 C34 0.1uF 16V C401 0.1uF 16V 16V 0.1uF 2 3 4 5 6 7 8 9 VCC GND C389 0.1uF 16V 24 1.8V signal EMIF_DIR_R EMIFD8 EMIFD9 EMIFD10 EMIFD11 EMIFD12 EMIFD13 EMIFD14 EMIFD15 C396 0.1uF 16V 1OE 2OE EXT_EMU_DET_C VCC1V8 20 10 U49 3.3V control 22 22 EMU_TCKRTN EMU_TDO VCC1V8 GND U68 18 16 14 12 R480 9 R12 7 5 3 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC3V3_AUX EMIF_OEz TI_SN74LVC1G04DBVR <Characteristic> C395 0.1uF 16V 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 TI_SN74LVC244APWR <Characteristic> E-PAD_1 E-PAD_2 E-PAD_3 E-PAD_4 E-PAD_5 E-PAD_6 E-PAD_7 GND IN A1 A10 A2 A9 B1 B10 B9 D6 D7 D8 E3 E4 E5 E6 E7 E8 F3 F4 F5 F6 F8 G6 G7 H3 H5 H6 H7 J3 J5 L1 L10 L2 L9 M1 M10 M2 M9 10 NAND_WPz WE WP NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 IN BI BI BI BI BI BI BI 20 13 C7 C3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 1 EMIFWEZ H4 J4 K4 K5 K6 J7 K7 J8 DIR EMIFD0 EMIFD1 EMIFD2 EMIFD3 EMIFD4 EMIFD5 EMIFD6 EMIFD7 OE B1 B2 B3 B4 B5 B6 B7 19 18 17 16 15 14 13 12 2 4 6 8 11 13 15 17 20 18 17 16 15 14 13 12 B1 B2 B3 B4 B5 B6 B7 B8 1.8V signal 1.8V to SOC SEL NC 0B1 1B1 2B1 3B1 4B1 5B1 6B1 7B1 A0 A1 A2 A3 A4 A5 A6 A7 VDD1 VDD2 VDD3 VDD4 VDD5 0B2 1B2 2B2 3B2 4B2 5B2 6B2 7B2 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 2 NAND1 VCC NAND FLASH Note: NAND FLASH Device size is 4Gb. A1 A2 A3 A4 A5 A6 A7 A8 EMU_TDI EMU_TMS EMU_TRST# EMU_TCK OE A1 A2 A3 A4 A5 A6 A7 A8 10 1 3 4 5 6 7 8 9 R48 4.7K R490 22 TI_TXS0108EPWR E-PAD_1 E-PAD_2 E-PAD_3 E-PAD_4 E-PAD_5 E-PAD_6 E-PAD_7 VCC1V8 46 43 40 37 33 30 VCC1V8 R511 R519 GND17 GND16 GND15 GND14 GND13 GND12 4.75K 1% 4.75K 1% 1 6 12 19 36 VCC3V3_AUX C393 0.1uF 16V 3 5 7 9 11 13 16 18 20 22 27 C402 0.1uF 16V C30 10uF 6.3V Switch for JTAG emulation EXT_EMU_DET = 0 --> XDS200 Mezzanine Emulator EXT_EMU_DET = 1 --> JTAG connection from AMC edge fingers. A DSPM-8305E Designed for TI by ADVANTECH TI_SN74AUCH245RGYR <Characteristic> BI SOC_EMIFD15 Title 39 SOC_JTAG_EMU Document Number Custom Date: 4 B SOC_TDI SOC_TMS SOC_TRST# SOC_TCK SOC_TDO SOC_EMU_00 SOC_EMU_01 2 4 8 10 15 17 21 23 TI_TS3L301DGG Size 5 14 B8 B 2 3 4 5 6 7 8 9 U45 VCC1V8 VCC U65 EMIFD0 EMIFD1 EMIFD2 EMIFD3 EMIFD4 EMIFD5 EMIFD6 EMIFD7 C838 EMIF_DIR_R 19 R810 B8 IN 11 EMIF_DIR VCCA NL/0 16V 0.1uF 13 VCCB R811 GND 0 11 EMIFOEZ 50V GND 1000pF 11 C807 TI_SN74AUC1G125DCKR <Characteristic> 10 SOC_TRST# 3 2 Rev A104 K2EVM-HK Tuesday, November 04, 2014 1 Sheet 19 of 43 5 4 3 2 1 D D SOC AIF Note: AIF is only supported on K2H devices U24M TI_TMS320TCI6638 30.72MHz 12 12 12 12 AMC_RP1FBN AMC_RP1FBP AMC_RP1CLKN AMC_RP1CLKP IN IN IN IN AT1 AR1 C184 C170 0.1uF 16V RP1FBN 0.1uF 16V RP1FBP C499 C500 0.1uF 16V RP1CLKN_C AP2 0.1uF 16V RP1CLKP_C AR2 RP1FBN RP1FBP AIFRXN0 AIFRXP0 AIFRXN1 AIFRXP1 AIFRXN2 AIFRXP2 AIFRXN3 AIFRXP3 AIFRXN4 AIFRXP4 AIFRXN5 AIFRXP5 RP1CLKN RP1CLKP note: keep the signal of RP1CLKP/N_C stubs very short C VCC1V8 R321 R308 10K NL/10K RP1FBN R319 RP1FBP R307 R617 R616 10K 10K PHYSYNC RADSYNC TP73 AM16 TP70 AM14 RSV024 RSV025 AIFTXN0 AIFTXP0 AIFTXN1 AIFTXP1 AIFTXN2 AIFTXP2 AIFTXN3 AIFTXP3 AIFTXN4 AIFTXP4 AIFTXN5 AIFTXP5 NL/10K 10K 1% 3K R649 AM15 1% 3K R638 AM11 AIFREFRES0 AIFREFRES1 AW16 AW17 AU16 AU17 AV15 AV16 AW13 AW14 AU13 AU14 AV12 AV13 AIF0_RXN_C AIF0_RXP_C AIF1_RXN_C AIF1_RXP_C AIF2_RXN_C AIF2_RXP_C AIF3_RXN_C AIF3_RXP_C AIF4_RXN_C AIF4_RXP_C AIF5_RXN_C AIF5_RXP_C AP17 AP18 AR16 AR17 AT15 AT16 AP14 AP15 AR13 AR14 AT12 AT13 ZD3_AIF0_TXN ZD3_AIF0_TXP ZD3_AIF1_TXN ZD3_AIF1_TXP ZD3_AIF2_TXN ZD3_AIF2_TXP ZD3_AIF3_TXN ZD3_AIF3_TXP C233 C235 C577 C589 C590 C596 C227 C229 C568 C579 C219 C224 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V IN IN IN IN IN IN IN IN IN IN IN IN ZD3_AIF0_RXN ZD3_AIF0_RXP ZD3_AIF1_RXN ZD3_AIF1_RXP ZD3_AIF2_RXN ZD3_AIF2_RXP ZD3_AIF3_RXN ZD3_AIF3_RXP AMCC_P17_AIF4_RXN AMCC_P17_AIF4_RXP AMCC_P18_AIF5_RXN AMCC_P18_AIF5_RXP OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT R623 EXTFRAMEEVENT PHYSYNC RADSYNC 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF AC4 EXTFRAMEEVENT AP34 PHYSYNC AM30 RADSYNC 39 39 39 39 39 39 39 39 ZD3_AIF0_TXN ZD3_AIF0_TXP ZD3_AIF1_TXN ZD3_AIF1_TXP ZD3_AIF2_TXN ZD3_AIF2_TXP ZD3_AIF3_TXN ZD3_AIF3_TXP AMCC_P17_AIF4_TXN AMCC_P17_AIF4_TXP AMCC_P18_AIF5_TXN AMCC_P18_AIF5_TXP 12 12 12 12 C 39 39 39 39 39 39 39 39 12 12 12 12 10K IN IN PHYSYNC RADSYNC 12,35 12,35 13 of 26 TI_TMS320TCI6638 <Characteristic> CN15 18 EXT_TIMO1 OUT EXT_TIMO1 EXTFRAMEEVENT 1 2 PH_2x1V_2.00mm <Characteristic> B B A A DSPM-8305E Designed for TI by ADVANTECH Title SOC_AIF Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 20 of 43 5 4 3 2 1 SOC CLOCK / RESET All blocking capacitors should be placed near SOC to keep connecting routes short and minimize vias SEL I/P PAIR SEL LOW DIF_IN2/IN2# HIGH DIF_IN1/IN1# U24H TI_TMS320TCI6638 VCC3V3_PCIE VCC3V3_AUX VCC3V3_AUX D VCC3V3_PCIE 1 R292 10K R276 NL/10K PCIE_CLKP_R 3 B23 2200pF 0.7A C151 10uF 6.3V 2 PCIECLK_MUX_SEL PCIE_CLKN_R R275 10K R296 1.3K 1% 27 27 ALT_CORE_CLKN ALT_CORE_CLKP IN IN 27 27 DDR3A_CLKN DDR3A_CLKP IN IN 27 27 DDR3B_CLKN DDR3B_CLKP IN IN 27 27 HYPER0_LINK_CLKN HYPER0_LINK_CLKP IN IN 27 27 HYPER1_LINK_CLKN HYPER1_LINK_CLKP IN IN 25 25 IN IN 26 26 SRIO_SGMII_CLKN SRIO_SGMII_CLKP VCC3V3_PCIE IN U20 R282 (HCSL) 12 12 36 (LVDS) 36 PCIe_REF_CLK_P PCIe_REF_CLK_N PCIECLK_MCU_PD 27 PCIE_CLKP 27 PCIE_CLKN PCIECLK_OE IN IN IN IN IN IN C166 C167 100 PCIE_CLKP_R PCIE_CLKN_R 0.1uF 16V 0.1uF 16V R295 1 2 3 4 5 6 7 8 100 R304 R274 10K 10K 27 27 PCIECLK_MUX_SEL 36 PCIECLKP_M 16 VDDIN SEL 15 PCIECLKP_MR R278 33 5% DIF_IN1 DIF_0 14 PCIECLKN_MR R286 33 5% DIF_IN1 DIF_0 13 PD GND_3 12 DIF_IN2 GND_2 11 VCC3V3_PCIE DIF_IN2 VDD_2 10 OE VDD_1 9 R287 GND_1 IREF 150 IDT_5V41068APGGI R298 475 1% 5% <Characteristic> PCIECLKN_M SYS_CLKN SYS_CLKP ARM_CLKN ARM_CLKP IN IN PCIECLKN_M PCIECLKP_M IN IN C175 C174 0.1uF 16V 0.1uF 16V ALTCORECLKN_C ALTCORECLKP_C C670 C671 0.1uF 16V 0.1uF 16V DDR3ACLKN_C DDR3ACLKP_C A25 B25 C324 C323 0.1uF 16V 0.1uF 16V DDR3BCLKN_C DDR3BCLKP_C AR39 AR38 C534 C524 0.1uF 0.1uF HYPER0LINKCLKN_C HYPER0LINKCLKP_C AT10 AT9 C191 C187 0.1uF 16V 0.1uF 16V HYPER1LINKCLKN_C HYPER1LINKCLKP_C AW5 AW4 C179 C178 0.1uF 16V 0.1uF 16V SYSCLKN_C SYSCLKP_C C319 C317 0.1uF 16V 0.1uF 16V SRIOSGMIICLKN_C SRIOSGMIICLKP_C AW35 AW34 C307 C302 0.1uF 16V 0.1uF 16V PCIECLKN_C PCIECLKP_C AW32 AW31 C725 C726 0.1uF 16V 0.1uF 16V ARMCLKN_C ARMCLKP_C B37 C37 R288 100 25 25 R279 150 5% PASS_CLKN PASS_CLKP C312 C309 IN IN 16V 16V AL2 AM2 AK3 AL3 TP51 TP52 TETRISPLLOBSCLKN TETRISPLLOBSCLKP D38 C38 TP64 TP65 COREPLLOBSCLKN COREPLLOBSCLKP AM4 AN4 0.1uF 16V 0.1uF 16V PASSCLKN_C PASSCLKP_C AV34 AV33 ALTCORECLKN ALTCORECLKP DDR3ACLKN DDR3ACLKP D DDR3BCLKN DDR3BCLKP HYPLNK0CLKN HYPLNK0CLKP HYPLNK1CLKN HYPLNK1CLKP SYSCLKN SYSCLKP SRIOSGMIICLKN SRIOSGMIICLKP PCIECLKN PCIECLKP CN20 ARMCLKN ARMCLKP RSV015 RSV017 ARMPLLOBSCLKN ARMPLLOBSCLKP E33 F26 1 2 3 4 RSV016 RSV018 F32 G26 PH_4x1V_2.0mm <Characteristic> COREPLLOBSCLKN COREPLLOBSCLKP PASSCLKN PASSCLKP PAPLLOBSCLKN PAPLLOBSCLKP AT34 PAPLLOBSCLKN AU34 PAPLLOBSCLKP TP92 TP90 8 of 26 TI_TMS320TCI6638 <Characteristic> Stuff C C Smart Reflex CN19 DSP_VCL_R 1 ARM0_VCL_R 3 2 DSP_VD_R 4 ARM0_VD_R PH_4x1V_2.0mm <Characteristic> U24Q TI_TMS320TCI6638 ARM0_VCL_R ARM0_VD_R AT37 AT35 AU36 AV37 AU37 AV36 AU35 AW36 B VCLT VDT VCNTL0T VCNTL1T VCNTL2T VCNTL3T VCNTL4T VCNTL5T VCL VD VCNTL0 VCNTL1 VCNTL2 VCNTL3 VCNTL4 VCNTL5 AP36 AP35 DSP_VCL_R DSP_VD_R AT39 AR37 AR36 AT38 AU38 AR35 17 of 26 TI_TMS320TCI6638 <Characteristic> VCC1V8 B VCC1V8 VCC3V3_AUX C732 0.1uF 16V R415 4.7K R416 4.7K R417 4.7K VID_OEZ IN R407 R450 4.7K U37 16 15 14 13 12 11 10 9 DSP_VIDA DSP_VIDB DSP_VIDC DSP_VIDS VID_OEZ C367 0.1uF 16V R418 4.7K VID_OEZ 37 VCC3V3_AUX 10K VCCB 1OE 2OE 1B1 1B2 2B1 2B2 GND2 VCCA 1DIR 2DIR 1A1 1A2 2A1 2A2 GND1 1 2 3 4 5 6 7 8 R451 4.7K R452 4.7K R453 4.7K DSP_UCD9244_VID1A DSP_UCD9244_VID1B DSP_UCD9244_VID1C DSP_UCD9244_VID1S OUT OUT OUT OUT DSP_UCD9244_VID1A DSP_UCD9244_VID1B DSP_UCD9244_VID1C DSP_UCD9244_VID1S 40 40 40 40 TI_SN74AVC4T245PWR VCC3V3_AUX VCC1V8 VCC1V8 VCC3V3_AUX C340 0.1uF 16V R411 4.7K A R412 4.7K R413 4.7K IN AVID_OEZ R406 10K R446 4.7K U35 ARM_VIDA ARM_VIDB ARM_VIDC ARM_VIDS AVID_OEZ C366 0.1uF 16V R414 4.7K AVID_OEZ 37 VCC3V3_AUX VCC3V3_AUX 16 15 14 13 12 11 10 9 VCCB 1OE 2OE 1B1 1B2 2B1 2B2 GND2 VCCA 1DIR 2DIR 1A1 1A2 2A1 2A2 GND1 1 2 3 4 5 6 7 8 ARM_UCD9244_VID2A ARM_UCD9244_VID2B ARM_UCD9244_VID2C ARM_UCD9244_VID2S R447 4.7K R448 4.7K R449 4.7K A OUT OUT OUT OUT ARM_UCD9244_VID2A ARM_UCD9244_VID2B ARM_UCD9244_VID2C ARM_UCD9244_VID2S 40 40 40 40 TI_SN74AVC4T245PWR Title SOC_CLOCK & Smart-Reflex VID Size C Date: 5 4 DSPM-8305E Designed for TI by ADVANTECH 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 21 of 43 5 4 3 2 1 1.8V_1A VCC1V8 VCC1V8 VCC1V8 U24D Place near to SOC TI_TMS320TCI6638 AA6 AB5 AB7 AC6 AD7 AE6 AF7 AG6 D DVDD18_01 DVDD18_02 DVDD18_03 DVDD18_04 DVDD18_05 DVDD18_06 DVDD18_07 DVDD18_08 AJ26 AK27 AL26 AL28 AM27 AM29 DVDD18_09 DVDD18_10 DVDD18_11 DVDD18_12 DVDD18_13 DVDD18_14 G14 AC31 VCCA0V75REF VCCB0V75REF C592 0.1uF 16V DVDD18_15 DVDD18_16 DVDD18_17 DVDD18_18 DVDD18_19 DVDD18_20 DVDD18_21 DVDD18_22 DVDD18_23 DVDD18_24 DVDD18_25 DVDD18_26 DVDD18_27 DVDD18_28 DVDD18_29 DVDD18_30 DVDD18_31 DVDD18_32 DVDD18_33 DVDD18_34 DVDD18_35 DDR3AVREFSSTL DDR3BVREFSSTL C715 0.1uF 16V H25 H27 J26 J28 J32 K25 K27 K31 L24 L26 L30 M29 N30 R6 T7 U6 C727 100uF 6.3V C654 10uF 6.3V C333 10uF 6.3V C328 4.7uF 6.3V D VCC1V8 Place near to SOC pins C672 0.1uF 16V V5 V7 W6 Y5 Y7 4 of 26 TI_TMS320TCI6638 <Characteristic> C687 0.1uF 16V C702 0.1uF 16V C514 0.01uF 16V C685 0.01uF 16V C529 0.01uF 16V C536 1000pF 50V C528 1000pF 50V C516 560pF 50V C515 560pF 50V C665 560pF 50V C708 1000pF 50V VCC1V8 Place near to SOC pins C711 560pF 50V C518 560pF 50V C530 560pF 50V C535 560pF 50V C519 560pF 50V C350 560pF 50V C C VCC1V8 Close to SOC AVDDA1 C816 0.01uF 16V VDD33 Place near to SOC AVDDA2 TI_TMS320TCI6638 C560 0.1uF 16V C561 0.1uF 16V C207 10uF 6.3V VPP1V8 AA14 L22 M21 C632 0.1uF 16V B AVDDA1 AVDDA2 AVDDA3 AVDDA4 AVDDA5 AVDDA6 AVDDA7 AVDDA8 AVDDA9 AVDDA10 AVDDA11 AVDDA12 AVDDA13 AVDDA14 AVDDA15 DVDD33 VPP_01 VPP_02 VCC1V5 AA28 AA30 AB29 AB31 AC30 AD29 AD31 AE30 AF29 AF31 AG30 AH31 AJ30 AK31 AL32 H11 H13 H15 H17 H19 H21 H23 H7 H9 J10 J12 J14 J16 J18 J20 J22 J6 J8 K11 K13 K15 K17 470_100MHz 1.5A C171 0.1uF 16V DVDD15_01 DVDD15_02 DVDD15_03 DVDD15_04 DVDD15_05 DVDD15_06 DVDD15_07 DVDD15_08 DVDD15_09 DVDD15_10 DVDD15_11 DVDD15_12 DVDD15_13 DVDD15_14 DVDD15_15 DVDD15_16 DVDD15_17 DVDD15_18 DVDD15_19 DVDD15_20 DVDD15_21 DVDD15_22 DVDD15_23 DVDD15_24 DVDD15_25 DVDD15_26 DVDD15_27 DVDD15_28 DVDD15_29 DVDD15_30 DVDD15_31 DVDD15_32 DVDD15_33 DVDD15_34 DVDD15_35 DVDD15_36 DVDD15_37 DVDD15_38 DVDD15_39 DVDD15_40 DVDD15_41 DVDD15_42 DVDD15_43 DVDD15_44 DVDD15_45 DVDD15_46 DVDD15_47 DVDD15_48 DVDD15_49 DVDD15_50 DVDD15_51 DVDD15_52 DVDD15_53 DVDD15_54 DVDD15_55 DVDD15_56 DVDD15_57 DVDD15_58 DVDD15_59 DVDD15_60 DVDD15_61 DVDD15_62 DVDD15_63 DVDD15_64 DVDD15_65 DVDD15_66 DVDD15_67 DVDD15_68 AF11 AVDDA1 N20 AVDDA2 N28 AVDDA3 AH29 AVDDA4 AG26 AVDDA5 P11 VDDPLL0 M13 M15 M18 M20 Y28 VDDPLL1 AB28 AC28 AD28 AE28 K19 K21 K23 K7 K9 L10 L12 L14 L16 L18 L20 L32 L8 M11 M17 M19 M31 P29 P31 R28 R30 T29 T31 U28 U30 V29 V31 W28 W30 Y29 Y31 C817 0.01uF 16V AVDDA5 C249 10uF 6.3V B38 C820 0.01uF 16V VCC1V8 Close to SOC 470_100MHz 1.5A VDDPLL0 C303 0.1uF 16V C823 0.01uF 16V B17 C157 0.1uF 16V C822 0.01uF 16V C156 0.1uF 16V C821 0.01uF 16V C155 0.1uF 16V B16 470_100MHz 1.5A C152 0.1uF 16V VCC1V8 Close to SOC VDDPLL1 AVDDA3 C818 0.01uF 16V C826 0.01uF 16V VCC1V8 Close to SOC VCC1V5 100_100MHz 2A VCC1V8 Close to SOC U24B VDD33 VCC1V8 Close to SOC B45 B32 B20 C272 0.1uF 16V C825 0.01uF 16V 100_100MHz 2A C153 0.1uF 16V 470_100MHz 1.5A C259 0.1uF 16V B VCC1V8 Close to SOC AVDDA4 C819 0.01uF 16V VCC1V5 B41 470_100MHz 1.5A C316 0.1uF 16V VCC1V5 VCC1V5 Place near to SOC C593 4.7uF 6.3V C618 4.7uF 6.3V C712 0.1uF 16V C695 0.1uF 16V C710 0.1uF 16V C703 0.1uF 16V Place near to SOC pins C567 0.1uF 16V C531 0.1uF 16V C538 0.1uF 16V C543 0.1uF 16V C525 0.1uF 16V C521 0.1uF 16V C707 0.01uF 16V C602 0.01uF 16V C565 0.01uF 16V C607 0.01uF 16V C581 0.01uF 16V C694 560pF 50V C692 560pF 50V C696 560pF 50V C691 560pF 50V C690 560pF 50V C706 560pF 50V C693 560pF 50V C704 560pF 50V C554 560pF 50V C638 560pF 50V VCC1V5 2 of 26 TI_TMS320TCI6638 <Characteristic> Place near to SOC pins A A C713 0.01uF 16V C678 0.01uF 16V C709 0.01uF 16V C676 0.01uF 16V C705 0.01uF 16V C650 0.01uF 16V C631 0.01uF 16V C620 0.01uF 16V C612 0.01uF 16V DSPM-8305E Designed for TI by ADVANTECH Title SOC_POWERA Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 22 of 43 5 4 3 2 1 0.85V - 1.05V (CVDD) (Smart Reflex) Fix_0.95V(VCC0V95) CVDD CVDD CVDD U24A TI_TMS320TCI6638 AA10 AA16 AA18 AA20 AA22 AA24 AA26 AA8 AB11 AB15 AB17 AB19 AB21 AB23 AB25 AB27 AB9 AC10 AC12 AC14 AC16 AC20 AC22 AC24 AC26 AC8 AD13 AD15 AD21 AD23 AD25 AD27 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE22 AE24 AE26 AE8 AF25 AF27 AF9 AG10 AG28 AG8 AH27 AH9 AJ10 AJ28 AJ8 AK29 AK7 AK9 AL30 AL6 AL8 AM31 AM5 L6 M25 M7 M9 N10 N12 N14 N16 N18 N22 N6 N8 P13 P15 P17 P19 P21 P27 P7 P9 R10 R12 R14 R16 R18 D C B CVDD_88 CVDD_89 CVDD_90 CVDD_91 CVDD_92 CVDD_93 CVDD_94 CVDD_95 CVDD_96 CVDD_97 CVDD_98 CVDD_99 CVDD_100 CVDD_101 CVDD_102 CVDD_103 CVDD_104 CVDD_105 CVDD_106 CVDD_107 CVDD_108 CVDD_109 CVDD_110 CVDD_111 CVDD_112 CVDD_113 CVDD_114 CVDD_115 CVDD_116 CVDD_117 CVDD_01 CVDD_02 CVDD_03 CVDD_04 CVDD_05 CVDD_06 CVDD_07 CVDD_08 CVDD_09 CVDD_10 CVDD_11 CVDD_12 CVDD_13 CVDD_14 CVDD_15 CVDD_16 CVDD_17 CVDD_18 CVDD_19 CVDD_20 CVDD_21 CVDD_22 CVDD_23 CVDD_24 CVDD_25 CVDD_26 CVDD_27 CVDD_28 CVDD_29 CVDD_30 CVDD_31 CVDD_32 CVDD_33 CVDD_34 CVDD_35 CVDD_36 CVDD_37 CVDD_38 CVDD_39 CVDD_40 CVDD_41 CVDD_42 CVDD_43 CVDD_44 CVDD_45 CVDD_46 CVDD_47 CVDD_48 CVDD_49 CVDD_50 CVDD_51 CVDD_52 CVDD_53 CVDD_54 CVDD_55 CVDD_56 CVDD_57 CVDD_58 CVDD_59 CVDD_60 CVDD_61 CVDD_62 CVDD_63 CVDD_64 CVDD_65 CVDD_66 CVDD_67 CVDD_68 CVDD_69 CVDD_70 CVDD_71 CVDD_72 CVDD_73 CVDD_74 CVDD_75 CVDD_76 CVDD_77 CVDD_78 CVDD_79 CVDD_80 CVDD_81 CVDD_82 CVDD_83 CVDD_84 CVDD_85 CVDD_86 CVDD_87 Place near to SOC R20 R8 T11 T15 T17 T19 T27 T9 U10 U12 U18 U8 V15 V19 V27 V9 W10 W12 W14 W18 W20 W8 Y15 Y17 Y19 Y21 Y23 Y25 Y27 Y9 C433 100uF 6.3V C532 100uF 6.3V C551 100uF 6.3V C66 100uF 6.3V C576 47uF 6.3V C595 47uF 6.3V C591 10uF 6.3V C614 47uF 6.3V C578 10uF 6.3V CVDD1 C610 0.01uF 16V C604 560pF 50V C621 560pF 50V C115 0.1uF 16V C584 0.01uF 16V C630 0.1uF 16V C640 0.01uF 16V C116 560pF 50V C461 560pF 50V C105 4.7uF 6.3V C642 100uF 6.3V C546 0.01uF 16V C520 0.01uF 16V C545 0.01uF 16V C583 560pF 50V C605 560pF 50V C104 4.7uF 6.3V C498 100uF 6.3V D CVDD Place near to SOC pins C555 0.1uF 16V C571 0.1uF 16V C681 0.1uF 16V C609 0.1uF 16V C659 0.1uF 16V C648 0.1uF 16V C684 0.1uF 16V C619 0.1uF 16V C623 0.1uF 16V C682 0.1uF 16V C641 0.1uF 16V C658 0.1uF 16V C679 0.1uF 16V C677 0.1uF 16V C661 0.1uF 16V C647 0.1uF 16V C547 0.01uF 16V C603 0.01uF 16V CVDD1T CVDD Place near to SOC pins CVDD1_01 CVDD1_02 CVDD1_03 CVDD1_04 CVDD1_05 CVDD1_06 CVDD1_07 CVDD1_08 CVDD1_09 CVDD1_10 CVDD1_11 CVDD1_12 C457 0.1uF 16V AC18 AD17 AD19 T13 T21 U14 U16 U20 V13 V17 V21 W16 CVDD1 C527 0.01uF 16V C549 0.01uF 16V C608 0.01uF 16V C635 0.01uF 16V Place near to SOC pins C526 0.01uF 16V C550 0.01uF 16V C542 0.01uF 16V C698 0.01uF 16V C662 0.01uF 16V C559 C611 0.01uF 16V C606 0.01uF 16V C615 0.01uF 16V C585 0.01uF 16V C622 0.01uF 16V C CVDD Place near to SOC pins CVDDT_01 CVDDT_02 CVDDT_03 CVDDT_04 CVDDT_05 CVDDT_06 CVDDT_07 CVDDT_08 CVDDT_09 CVDDT_10 CVDDT_11 CVDDT_12 CVDDT_13 CVDDT_14 CVDDT_15 CVDDT_16 CVDDT_17 CVDDT_18 CVDDT_19 CVDDT1_01 CVDDT1_02 CVDDT1_03 H31 J30 K29 L28 M27 N24 N26 P23 P25 R24 R26 T23 T25 U24 U26 V23 V25 W24 W26 CVDD C617 1uF 6.3V C634 560pF 50V C587 560pF 50V C563 560pF 50V C556 560pF 50V C680 560pF 50V C657 1uF 6.3V C697 1uF 6.3V C683 560pF 50V C649 47nF 10%_25V C586 560pF 50V CVDD C633 560pF 50V C548 560pF 50V C539 560pF 50V C552 560pF 50V C533 560pF 50V C562 560pF 50V CVDD CVDD Place near to SOC C368 100uF 6.3V R22 U22 W22 C600 1uF 6.3V C765 100uF 6.3V CVDD1T C656 47uF 6.3V C669 10uF 6.3V Place near to SOC pins C639 1uF 6.3V C667 47nF 10%_25V C651 47nF 10%_25V C673 0.01uF 16V Place near to SOC pins C701 0.01uF 16V C645 47nF 10%_25V C597 560pF 50V C541 560pF 50V C575 47nF 10%_25V C540 560pF 50V C660 47nF 10%_25V CVDD B VNWA1 VNWA2 VNWA3 VNWA4 AG24 AD11 M23 V11 Place near to SOC pins CVDD1 C689 0.1uF 16V 1 of 26 C646 0.1uF 16V C700 0.1uF 16V C674 0.1uF 16V TI_TMS320TCI6638 <Characteristic> AVDDAHV VCC0V85 U24C C655 560pF 50V TI_TMS320TCI6638 B46 1212_BEAD_0 AVDDALV <Characteristic> C627 C628 0.1uF 0.01uF 16V 16V AF13 AF15 AF17 AF19 AF21 AF23 AG12 AG14 AG16 AG18 AG20 AG22 AH11 AH13 AH15 AH17 AH19 AH21 AH23 AH25 AJ12 AJ14 AJ16 AJ18 AJ20 AJ22 AJ24 C629 560pF 50V AVDDALV Place near to SOC pins A C613 0.1uF 16V C601 0.1uF 16V C588 0.1uF 16V C643 0.1uF 16V C636 0.1uF 16V C594 0.1uF 16V C574 0.1uF 16V C564 0.1uF 16V C598 560pF 50V C573 560pF 50V C624 560pF 50V VDDALV_01 VDDALV_02 VDDALV_03 VDDALV_04 VDDALV_05 VDDALV_06 VDDALV_07 VDDALV_08 VDDALV_09 VDDALV_10 VDDALV_11 VDDALV_12 VDDALV_13 VDDALV_14 VDDALV_15 VDDALV_16 VDDALV_17 VDDALV_18 VDDALV_19 VDDALV_20 VDDALV_21 VDDALV_22 VDDALV_23 VDDALV_24 VDDALV_25 VDDALV_26 VDDALV_27 VDDAHV_01 VDDAHV_02 VDDAHV_03 VDDAHV_04 VDDAHV_05 VDDAHV_06 VDDAHV_07 VDDAHV_08 VDDAHV_09 VDDAHV_10 VDDAHV_11 VDDAHV_12 VDDAHV_13 VDDAHV_14 VDDAHV_15 VDDAHV_16 AK11 AK13 AK15 AK17 AK19 AK21 AK23 AK25 AL10 AL12 AL14 AL16 AL18 AL20 AL22 AL24 C664 560pF 50V C553 560pF 50V C699 560pF 50V AVDDAHV VCC1V8 Place near to SOC pins A VCC1V8 AVDDAHV B43 C599 0.1uF 16V C580 0.1uF 16V C566 0.1uF 16V C616 0.1uF 16V C637 0.1uF 16V C626 0.1uF 16V C326 100uF 6.3V 1212_BEAD_0 <Characteristic> Title 3 of 26 TI_TMS320TCI6638 <Characteristic> Title = SOC_POWERB Size C Date: 5 4 DSPM-8305E Designed for TI by ADVANTECH 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 23 of 43 B 5 4 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 Size C Date: 3 2 20 of 26 AJ7 AM32 H29 J24 Y8 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AA27 AA29 AA35 AA5 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AB26 AB30 AB33 AB36 AB37 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AC25 AC27 AC29 AC35 AC7 AC9 AD10 AD12 AD14 AD16 AD18 AD20 AD22 AD24 AD26 AD30 AD33 AD37 AD6 AD8 AE11 AE13 AE15 AE17 AE19 AE21 AE23 AE25 AE27 AE29 AE3 AE31 AE35 AE7 AE9 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AF30 AF33 AF37 AF6 AF8 AG11 AG13 AG15 AG17 AG19 AG21 AG23 AG25 AG27 AG29 AG31 AG35 AG4 AG7 AG9 AH10 AH12 AH14 A2 A3 A37 A38 VSS_05 VSS_06 VSS_07 VSS_08 VSS_09 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 5 of 26 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 TI_TMS320TCI6638 VSS_01 VSS_02 VSS_03 VSS_04 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AH33 AH37 AH6 AH7 AH8 AJ11 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ32 AJ35 AJ6 AJ9 AK10 AK12 AK14 AK16 AK18 AK2 AK20 AK22 AK24 AK26 AK28 AK30 AK33 AK37 AK6 AK8 AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL35 AL5 AL7 AL9 AM10 AM12 AM13 AM17 AM18 AM20 AM22 AM3 AM33 AM37 AM8 AN11 AN12 AN13 AN14 AN15 AN17 AN18 AN2 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN31 AN35 AN5 AN6 AN7 AN8 AN9 AP10 AP13 AP16 AP19 AP20 AP21 AP24 AP27 AP28 AP29 AP30 AP37 AP4 AP7 AR12 AR15 AR18 3 VSS_520 VSS_521 VSS_522 VSS_523 VSS_524 L15 L17 L19 L21 L23 L25 L27 L29 L31 L37 L5 L7 L9 M10 M12 M14 M16 M22 M24 M26 M28 M30 M33 M6 M8 N11 N13 N15 N17 N19 N21 N23 N25 N27 N29 N31 N35 N5 N7 N9 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 P30 P33 P37 P5 P6 P8 R11 R13 R15 R17 R19 R2 R21 R23 R25 R27 R29 R31 R35 R5 R7 R9 T10 T12 T14 T16 T18 T20 T22 T24 T26 T28 T30 T33 T37 T6 T8 U11 U13 U15 U17 U19 U21 U23 U25 U27 U29 U31 U35 U7 U9 V10 V12 V14 V16 V18 V20 V22 V24 V26 V28 V3 V30 V33 V37 V6 V8 W11 W13 W15 W17 W19 W21 W23 W25 W27 W29 W31 W35 W5 W7 W9 Y10 Y12 Y14 Y16 Y18 Y2 Y20 Y22 Y24 Y26 Y30 Y33 Y37 Y6 4 AW9 B1 B2 B38 B39 C1 C10 C12 C14 C16 C18 C20 C22 C24 C26 C29 C32 C39 C4 C6 C8 D34 D37 E11 E13 E15 E17 E19 E21 E28 E3 E5 E7 E9 G23 G25 G27 G29 G31 G35 H12 H14 H18 H20 H24 H26 H28 H30 H32 H37 H4 H6 H8 J1 J11 J13 J15 J17 J19 J2 J21 J23 J25 J27 J29 J3 J31 J33 J4 J5 J7 J9 K10 K12 K14 K16 K18 K20 K22 K24 K26 K28 K30 K32 K35 K5 K6 K8 L11 L13 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_403 VSS_404 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427 VSS_428 VSS_429 VSS_430 VSS_431 VSS_432 VSS_433 VSS_434 VSS_435 VSS_436 VSS_437 VSS_438 VSS_439 VSS_440 VSS_441 VSS_442 VSS_443 VSS_444 VSS_445 VSS_446 VSS_447 VSS_448 VSS_449 VSS_450 VSS_451 VSS_452 VSS_453 VSS_454 VSS_455 VSS_456 VSS_457 VSS_458 VSS_459 VSS_460 VSS_461 VSS_462 VSS_463 VSS_464 VSS_465 VSS_466 VSS_467 VSS_468 VSS_469 VSS_470 VSS_471 VSS_472 VSS_473 VSS_474 VSS_475 VSS_476 VSS_477 VSS_478 VSS_479 VSS_480 VSS_481 VSS_482 VSS_483 VSS_484 VSS_485 VSS_486 VSS_487 VSS_488 VSS_489 VSS_490 VSS_491 VSS_492 VSS_493 VSS_494 VSS_495 VSS_496 VSS_497 VSS_498 VSS_499 VSS_500 VSS_501 VSS_502 VSS_503 VSS_504 VSS_505 VSS_506 VSS_507 VSS_508 VSS_509 VSS_510 VSS_511 VSS_512 VSS_513 VSS_514 VSS_515 VSS_516 VSS_517 VSS_518 VSS_519 TI_TMS320TCI6638 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 D AV8 AW12 AW15 AW18 AW2 AW21 AW24 AW27 AW3 AW30 AW33 AW37 AW38 AW6 AR21 AR22 AR25 AR28 AR3 AR31 AR33 AR6 AR9 AT11 AT14 AT17 AT2 AT20 AT23 AT26 AT29 AT32 AT36 AT5 AT8 AU1 AU12 AU15 AU18 AU2 AU21 AU24 AU27 AU3 AU30 AU33 AU39 AU6 AU9 AV1 AV11 AV14 AV17 AV2 AV20 AV23 AV26 AV29 AV32 AV35 AV38 AV39 AV5 5 2 1 D U24E TI_TMS320TCI6638 <Characteristic> C C U24T TI_TMS320TCI6638 Tuesday, November 04, 2014 1 B <Characteristic> A A Designed for TI by ADVANTECH Sheet 24 DSPM-8305E Title Document Number SOC_GND K2EVM-HK of Rev A104 43 5 4 3 2 1 CLOCK GEN1 TCLKD_P_C TCLKD_N_C R256 49.9 1% R258 R257 49.9 1% VCC3V3_AUX 1% 5.6K R259 1 from VCTCXO19.2Mhz VCTCXO_19.2M_R 11 12 COAXIEL_4V <Characteristic> VCTCXO_19.2M_R TCLKD_P_C TCLKD_N_C 13 CLK1_REF_SEL IN R213 13,26,27 13 CLK_RSTz IN REFCLK1_PD# IN 36 13,26,27,36 13,26,27,36 13,26,27,36 R227//R221=530.303 CLK1_ELF 0 41 6 0 C113 10uF 40 44 6.3V 43 CLK1_ELF 42 4 5 3 2 IN IN OUT IN R252 R235 0 0 1 47 560 1% R221 10K C117 C118 2200pF 50V R815 STATUS0 STATUS1/PIN0 37 38 39 13 18 19 24 27 30 31 34 VCC3V3_AUX SEC_REFP SEC_REFN Y1_P Y1_N PRI_REFP PRI_REFN Y2_P Y2_N TI_CDCM6208V2RGZT <Characteristic> ELF REF_SEL Y4_P Y4_N PDN Y5_P Y5_N SI_MODE0 SI_MODE1 10K REFCLK1_PD# 17 16 20 21 23 22 Y3_P Y3_N REG_CAP RESETN/PWR SYNCN SCS/AD1/PIN3 SCL/PIN4 SDO/AD0/PIN2 SDI/SDA/PIN1 14 15 Y0_P Y0_N OUT OUT AT_CLKP AT_CLKN OUT OUT PASS_CLKP PASS_CLKN OUT OUT RSV_CLKP RSV_CLKN OUT OUT REFCK_P REFCK_N 21 21 122.88MHz Output 15 15 C449 0.1uF 16V 122.88MHz Output 21 21 C447 0.1uF 16V C472 0.1uF 16V C450 0.1uF 16V C473 0.1uF 16V C448 0.1uF 16V C446 0.1uF 16V C463 0.1uF 16V C459 0.1uF 16V C468 0.1uF 16V 122.88MHz Output 39 39 VCC3V3_AUX 29 28 Y7_P Y7_N SYS_CLKP SYS_CLKN 19.2M_TESTP 19.2M_TESTN 26 25 Y6_P Y6_N OUT OUT 32 33 R193 R190 0 0 TP26 TP16 35 36 R189 R188 0 0 TP23 TP22 26 26 19.2MHz Output C469 0.1uF 16V C 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 R227 MCU_SPI0_CS0z MCU_SPI0_CLK MCU_SPI0_MISO MCU_SPI0_MOSI 8 9 R253 CLK1_SYNC From MCU connect to this signal DVDD 46 45 PLL_LOCK1 OUT TP35 VDD_Y0_Y1_1 VDD_Y0_Y1_2 VDD_Y2_Y3_1 VDD_Y2_Y3_2 VDD_Y4 VDD_Y5 VDD_Y6 VDD_Y7 13 VCC3V3_AUX D VDD_PLL1 VDD_PLL2 H2 10 U14 STATUS0 outputs the PLL_LOCK signal STATUS1 the LOSS OF REFERENCE. H1 VCCPLLA1B VCC3V3_AUX TP37 2 CN13 VCCPLLA1B 48 VCTCXO_19.2M C VCCPLLA1A VCC3V3_AUX 3.16K 1% C134 1uF 6.3V D VDD_VCO 0.1uF 16V 0.1uF 16V 7 C141 C142 IN IN VDD_SEC_REF TCLKD_P TCLKD_N VDD_PRI_REF 12 12 THERMAL_VIA_16 THERMAL_VIA_15 THERMAL_VIA_14 THERMAL_VIA_13 THERMAL_VIA_12 THERMAL_VIA_11 THERMAL_VIA_10 THERMAL_VIA_9 THERMAL_VIA_8 THERMAL_VIA_7 THERMAL_VIA_6 THERMAL_VIA_5 THERMAL_VIA_4 THERMAL_VIA_3 THERMAL_VIA_2 THERMAL_VIA_1 GND_EPAD from AMC.0 care 30.72MHz 330pF 50V VCC3V3_AUX Synthesizer mode (high loop bandwidth) CDCM6208V1: With C1=100pF, R2=500O, C2=22nF and Internal components R3=100O, C3=242.5pF, fPFD=25MHz, and ICP=2.5mA: Loop bandwidth ~ (300kHz) CDCM6208V2: With C1=470pF, R2=560O, C2=100nF and Internal components R3=100O, C3=242.5pF, fPFD=30.72MHz, and ICP=2.5mA: Loop bandwidth ~ (300kHz) 1 3 VCCPLLA1A B10 2200pF 0.7A [Note]layout would place R213and C113 close to U14. C93 1uF 6.3V C107 0.1uF 16V C106 1uF 6.3V 2 Serial Interface Mode or Pin Mode Selection C94 0.1uF 16V pull-up resister MCU_SI_MODE[1:0] DESCRIPTION R228 VCC3V3_AUX 00 SPI MODE CLK1_SYNC 10K VCC3V3_AUX 1 3 VCCPLLA1B B12 2200pF 0.7A (Default) I2C MODE 10 PIN MODE (NO SERIAL PROGRAMMING) 11 RESEERVED 2 01 19.2M_TESTN <Characteristic> COAXIEL_3V 2 2 19.2M_TESTP <Characteristic> COAXIEL_3V B B 1 3 1 3 DAC_VOUT VCC1V8 VCC3V3_AUX CN5 VCC3V3_AUX C332 0.1uF 16V C126 0.1uF 16V R261 1K 1 OSC3 3 4 1 U32 SPI0 From SOC 18 18 18 SOC_SSP1_CS0 SOC_SSP1_CLK SOC_SSP1_MOSI IN IN IN R402 R401 10 10 VCCB 1OE 2OE 1B1 1B2 2B1 2B2 GND2 VCCA 1DIR 2DIR 1A1 1A2 2A1 2A2 GND1 1 2 3 4 5 6 7 8 B25 2200pF 0.7A 2 16 15 14 13 12 11 10 9 DAC_SSPCS2_3.3V DAC_SSPCK_3.3V SOC_SSPMOSI_3.3V C163 100pF 50V C162 0.1uF 16V CN6 C135 0.1uF 16V R260 NL/10K VCC VC OUT GND VCTCXO_19.2M 3 2 19.2MHz_15pF 3.3V TI_SN74AVC4T245PWR DAC_VOUT TP49 C301 0.1uF 16V VCC3V3_AUX U61 3 B47 2200pF 0.7A 2 A C799 0.1uF 16V C798 10uF 6.3V 8 7 6 5 DNC_0 DNC_1 VIN NC TEMP VOUT GND TRIM/NR C800 1uF 6.3V TI_REF5025AID <Characteristic> VCC3V3_AUX U29 C801 22uF 6.3V DAC_SSPCS2_3.3V DAC_SSPCK_3.3V SOC_SSPMOSI_3.3V 2 5 6 7 VREF SYNC SCLK DIN VDD VFB VOUT GND TI_DAC8550IBDGKT <Characteristic> 1 3 4 8 3 C318 0.1uF 16V C315 10uF 6.3V 1 B39 2200pF 0.7A A 2 1 1 2 3 4 Designed for TI by ADVANTECH Title CLOCK GEN1 Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 25 of 43 5 4 3 2 1 CLOCK GEN2 REFCK_P_C REFCK_N_C R241 VCCPLLA2A 3.16K 1% D C137 1uF 6.3V 13 MCU control from VCTCXO 25Mhz 3 DVDD 46 45 PLL_LOCK2 OUT TP32 25M_MMCX R242 0 CN10 SOC control 13 CLK2_REF_SEL R265 IN 13 From MCU connect to this signal CLK_RSTz IN REFCLK2_PD# IN 25M_MMCX_R 11 12 REFCK_P_C REFCK_N_C 8 9 CLK2_ELF 41 6 10uF 40 44 0 R207 13,25,27 0 C108 6.3V 43 CLK2_SYNC 36 13,25,27,36 13,25,27,36 13,25,27,36 MCU_SPI0_CS1z MCU_SPI0_CLK MCU_SPI0_MISO MCU_SPI0_MOSI 42 4 5 3 2 IN IN OUT IN R264 R225 C VCC3V3_AUX 0 0 1 47 STATUS0 STATUS1/PIN0 37 38 13 18 19 24 27 30 31 34 VCC3V3_AUX SEC_REFP SEC_REFN Y1_P Y1_N PRI_REFP PRI_REFN Y2_P Y2_N TI_CDCM6208V2RGZT <Characteristic> ELF REF_SEL Y4_P Y4_N PDN Y5_P Y5_N SI_MODE0 SI_MODE1 10K REFCLK2_PD# 17 16 Y3_P Y3_N REG_CAP RESETN/PWR SYNCN SCS/AD1/PIN3 SCL/PIN4 SDO/AD0/PIN2 SDI/SDA/PIN1 14 15 Y0_P Y0_N Y7_P Y7_N SRIO_SGMII_CLKP SRIO_SGMII_CLKN OUT OUT SOC_XFI_CLKP SOC_XFI_CLKN 20 21 R215 R210 33 33 5% 5% TP30 TP29 23 22 R200 R204 33 33 5% 5% TP27 TP28 156.25MHz Output 21 21 15 15 29 28 R184 R185 0 0 32 33 R183 R182 0 0 35 36 R181 R180 0 0 C445 0.1uF 16V 156.25MHz Output 10M_TESTP 10M_TESTN 26 25 Y6_P Y6_N OUT OUT C443 0.1uF 16V C444 0.1uF 16V C462 0.1uF 16V C464 0.1uF 16V C455 0.1uF 16V C467 0.1uF 16V C442 0.1uF 16V C471 0.1uF 16V C470 0.1uF 16V VCC3V3_AUX TP20 TP17 C466 0.1uF 16V TP19 TP18 TP12 TP24 C 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 R816 VCCPLLA2B VDD_Y0_Y1_1 VDD_Y0_Y1_2 VDD_Y2_Y3_1 VDD_Y2_Y3_2 VDD_Y4 VDD_Y5 VDD_Y6 VDD_Y7 U15 <Characteristic> COAXIEL_3V 1 VCCPLLA2B VCC3V3_AUX STATUS0 outputs the PLL_LOCK signal STATUS1 the LOSS OF REFERENCE. 25M_MMCX 2 VCC3V3_AUX 39 D VCC3V3_AUX 1% 5.6K VDD_PLL1 VDD_PLL2 1% 10 1% R584 49.9 VDD_VCO 49.9 R240 7 R239 VDD_SEC_REF 0.1uF 16V 0.1uF 16V 48 C138 C139 IN IN VDD_PRI_REF REFCK_P REFCK_N THERMAL_VIA_16 THERMAL_VIA_15 THERMAL_VIA_14 THERMAL_VIA_13 THERMAL_VIA_12 THERMAL_VIA_11 THERMAL_VIA_10 THERMAL_VIA_9 THERMAL_VIA_8 THERMAL_VIA_7 THERMAL_VIA_6 THERMAL_VIA_5 THERMAL_VIA_4 THERMAL_VIA_3 THERMAL_VIA_2 THERMAL_VIA_1 GND_EPAD 25 25 C123 1K 3.3uF 10V 1% C112 [Note]layout would place R207 and C108 close to U15. 33nF Synthesizer mode (high loop bandwidth) CDCM6208V1: With C1=100pF, R2=500O, C2=22nF and Internal components R3=100O, C3=242.5pF, fPFD=25MHz, and ICP=2.5mA: Loop bandwidth ~ (300kHz) CDCM6208V2: With C1=470pF, R2=560O, C2=100nF and Internal components R3=100O, C3=242.5pF, fPFD=30.72MHz, and ICP=2.5mA: Loop bandwidth ~ (300kHz) 16V Serial Interface Mode or Pin Mode Selection MCU_SI_MODE[1:0] DESCRIPTION VCC3V3_AUX R214 VCC3V3_AUX 00 SPI MODE 01 I2C MODE 1 3 B9 2200pF 0.7A pull-up resister 10K VCCPLLA2A C89 0.1uF 16V C88 1uF 6.3V C95 0.1uF 16V C96 1uF 6.3V 2 R219 CLK2_SYNC (Default) 10 PIN MODE (NO SERIAL PROGRAMMING) 11 RESEERVED VCC3V3_AUX 1 3 B11 2200pF 0.7A VCCPLLA2B 2 CLK2_ELF 1 3 CN23 10M_TESTN <Characteristic> COAXIEL_3V 2 2 10M_TESTP 1 <Characteristic> COAXIEL_3V 3 CN4 B B A A Designed for TI by ADVANTECH Title CLOCK GEN2 Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 26 of 43 5 4 3 2 CLOCK GEN3 12 12 TCLKB_P TCLKB_N C149 C147 IN IN 1 VCC3V3_AUX 0.1uF 16V 0.1uF 16V D C482 0.1uF 16V TCLKB_P_C TCLKB_N_C R273 49.9 1% R302 R272 49.9 1% R303 C479 0.1uF 16V C488 0.1uF 16V C478 0.1uF 16V TP36 3 VCCPLLA3A VCCPLLA3B VCCPLLA3B VCC3V3_AUX 1 VCTCXO_25M_CLKP_R VCTCXO_25M_CLKN_R 11 12 TCLKB_P_C TCLKB_N_C 13 CLK3_REF_SEL R277 IN R305 13,25,26 13 CLK_RSTz IN REFCLK3_PD# IN 0 C169 MCU_SPI0_CS2z MCU_SPI0_CLK MCU_SPI0_MISO MCU_SPI0_MOSI 41 6 10uF 40 44 6.3V 43 42 4 5 3 2 IN IN OUT IN R285 R301 3 0 0 1 47 VCCPLLA3B C103 1uF 6.3V C102 0.1uF 16V C101 0.1uF 16V VDD_Y0_Y1_1 VDD_Y0_Y1_2 VDD_Y2_Y3_1 VDD_Y2_Y3_2 VDD_Y4 VDD_Y5 VDD_Y6 VDD_Y7 VDD_PLL1 VDD_PLL2 STATUS0 STATUS1/PIN0 VDD_VCO 2 13 18 19 24 27 30 31 34 37 38 39 10 B14 2200pF 0.7A Y0_P Y0_N SEC_REFP SEC_REFN Y1_P Y1_N PRI_REFP PRI_REFN Y2_P Y2_N TI_CDCM6208V2RGZT <Characteristic> ELF REF_SEL Y3_P Y3_N REG_CAP RESETN/PWR Y4_P Y4_N PDN Y5_P Y5_N SYNCN SCS/AD1/PIN3 SCL/PIN4 SDO/AD0/PIN2 SDI/SDA/PIN1 SI_MODE0 SI_MODE1 10K REFCLK3_PD# Y6_P Y6_N Y7_P Y7_N 14 15 17 16 20 21 23 22 26 25 29 28 32 33 35 36 OUT OUT HYPER0_LINK_CLKP HYPER0_LINK_CLKN 21 21 312.5MHz Output OUT OUT HYPER1_LINK_CLKP HYPER1_LINK_CLKN 21 21 312.5MHz Output OUT OUT ARM_CLKP ARM_CLKN OUT OUT ALT_CORE_CLKP ALT_CORE_CLKN OUT OUT PCIE_CLKP PCIE_CLKN OUT OUT USB_CLKP USB_CLKN OUT OUT DDR3A_CLKP DDR3A_CLKN 21 21 100MHz Output OUT OUT DDR3B_CLKP DDR3B_CLKN 21 21 100MHz Output 21 21 125MHz Output 21 21 21 21 15 15 125MHz Output C 100MHz Output 100MHz Output 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 R817 8 9 CLK3_ELF 0 CLK3_SYNC 36 13,25,26,36 13,25,26,36 13,25,26,36 7 48 DVDD 46 45 OUT VDD_SEC_REF PLL_LOCK3 TP40 VDD_PRI_REF 13 THERMAL_VIA_16 THERMAL_VIA_15 THERMAL_VIA_14 THERMAL_VIA_13 THERMAL_VIA_12 THERMAL_VIA_11 THERMAL_VIA_10 THERMAL_VIA_9 THERMAL_VIA_8 THERMAL_VIA_7 THERMAL_VIA_6 THERMAL_VIA_5 THERMAL_VIA_4 THERMAL_VIA_3 THERMAL_VIA_2 THERMAL_VIA_1 GND_EPAD 1 U19 COAXIEL_4V <Characteristic> VCTCXO_25M_CLKN_R From MCU connect to this signal C486 0.1uF 16V H2 VCTCXO_25M_CLKP_R C C484 1uF 6.3V VCC3V3_AUX VCC3V3_AUX H1 COAXIEL_4V <Characteristic> C477 0.1uF 16V VCCPLLA3A 2 2 1 H2 C485 0.1uF 16V D VCC3V3_AUX H1 C481 0.1uF 16V 2 VCTCXO_25M_CLKN CN11 C489 0.1uF 16V VCC3V3_AUX B44 2200pF 0.7A TP34 C480 0.1uF 16V 3.16K 1% 1 VCTCXO_25M_CLKP C483 0.1uF 16V VCC3V3_AUX 1% 5.6K C168 1uF 6.3V CN12 C496 0.1uF 16V CLK3_ELF R299 510 1% C172 C497 B 0.022uF 16V [Note]layout would place R305 and C169 close to U19. pull-up resister 100pF 50V Synthesizer mode (high loop bandwidth) CDCM6208V1: With C1=100pF, R2=500O, C2=22nF and Internal components R3=100O, C3=242.5pF, fPFD=25MHz, and ICP=2.5mA: Loop bandwidth ~ (300kHz) CDCM6208V2: With C1=470pF, R2=560O, C2=100nF and Internal components R3=100O, C3=242.5pF, fPFD=30.72MHz, and ICP=2.5mA: Loop bandwidth ~ (300kHz) R300 VCC3V3_AUX 10K CLK3_SYNC VCC3V3_AUX R229 100 B OSC2 1 3 2 B15 2200pF 0.7A 1 2 3 C140 100pF 50V C146 0.1uF 16V OE NC GND VCC OUT OUT 6 5 4 VCTCXO_25M_CLKN_C VCTCXO_25M_CLKP_C C121 C122 0.01uF 16V VCTCXO_25M_CLKN 0.01uF 16V VCTCXO_25M_CLKP 25MHz 3.3V A A Designed for TI by ADVANTECH Title CLOCK GEN3 Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 27 of 43 5 4 3 2 1 VCC1V5 17,28,29 SOC_DDR3B_EA[0..15] SOC_DDR3B_EA0 SOC_DDR3B_EA1 SOC_DDR3B_EA2 SOC_DDR3B_EA3 SOC_DDR3B_EA4 SOC_DDR3B_EA5 SOC_DDR3B_EA6 SOC_DDR3B_EA7 SOC_DDR3B_EA8 SOC_DDR3B_EA9 SOC_DDR3B_EA10 SOC_DDR3B_EA11 SOC_DDR3B_EA12 SOC_DDR3B_EA13 SOC_DDR3B_EA14 D 17,28,29 17,28,29 17,28,29 SOC_DDR3B_EBA_0 SOC_DDR3B_EBA_1 SOC_DDR3B_EBA_2 IN IN IN 17,28,29 17,28,29 17,28,29 17,28,29 SOC_DDR3B_EWE# SOC_DDR3B_ECAS# SOC_DDR3B_ERAS# SOC_DDR3B_ECS_0# IN IN IN IN 17 17 17 17 SOC_DDR3B_EDQSP_0 SOC_DDR3B_EDQSN_0 SOC_DDR3B_EDQSP_1 SOC_DDR3B_EDQSN_1 IN IN IN IN 17 17 SOC_DDR3B_EDM_0 SOC_DDR3B_EDM_1 IN IN 17,28,29 17,28,29 17,28,29 SOC_DDR3B_ECKP_0 SOC_DDR3B_ECKN_0 SOC_DDR3B_ECKE_0 IN IN IN 17,28,29 SOC_DDR3B_EODT_0 IN 17,28,29 SOC_DDR3B_EMRESETN IN SOC_DDR3B_EA[0..15] L3 K3 J3 L2 F3 G3 C7 B7 E7 D3 J7 K7 K9 K1 T2 240 1% IN C N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M2 N8 M3 R777 17,28,29 VCC1V5 U43 IN SOC_DDR3B_EA15 L8 J1 J9 L1 L9 M7 * Data bits can be swapped within the byte lane to ease routing. * Address/Command/Control/Clock routing must be Fly-By in byte order 0, 1, 2, 3 ECC, 4, 5, 6, 7. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 BA0 BA1 BA2 WE CAS RAS CS DQSL DQSL DQSU DQSU DML DMU CK CK CKE ODT RESET ZQ NC_1 NC_2 NC_3 NC_4 NC_5 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 17,28,29 B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9 C742 0.1uF 16V C750 0.1uF 16V C743 0.1uF 16V C751 0.1uF 16V U40 IN SOC_DDR3B_EA0 SOC_DDR3B_EA1 SOC_DDR3B_EA2 SOC_DDR3B_EA3 SOC_DDR3B_EA4 SOC_DDR3B_EA5 SOC_DDR3B_EA6 SOC_DDR3B_EA7 SOC_DDR3B_EA8 SOC_DDR3B_EA9 SOC_DDR3B_EA10 SOC_DDR3B_EA11 SOC_DDR3B_EA12 SOC_DDR3B_EA13 SOC_DDR3B_EA14 C780 22uF 6.3V VCCB0V75REF Trace need 20 mil. C772 0.1uF 16V M8 H1 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 C790 0.1uF 16V SOC_DDR3B_EA[0..15] BI SOC_DDR3B_EDQ0 SOC_DDR3B_EDQ1 SOC_DDR3B_EDQ2 SOC_DDR3B_EDQ3 SOC_DDR3B_EDQ4 SOC_DDR3B_EDQ5 SOC_DDR3B_EDQ6 SOC_DDR3B_EDQ7 SOC_DDR3B_EDQ8 SOC_DDR3B_EDQ9 SOC_DDR3B_EDQ10 SOC_DDR3B_EDQ11 SOC_DDR3B_EDQ12 SOC_DDR3B_EDQ13 SOC_DDR3B_EDQ14 SOC_DDR3B_EDQ15 SOC_DDR3B_EDQ[0..7] BI 17 SOC_DDR3B_EDQ[8..15] 17,28,29 17,28,29 17,28,29 SOC_DDR3B_EBA_0 SOC_DDR3B_EBA_1 SOC_DDR3B_EBA_2 IN IN IN 17,28,29 17,28,29 17,28,29 17,28,29 SOC_DDR3B_EWE# SOC_DDR3B_ECAS# SOC_DDR3B_ERAS# SOC_DDR3B_ECS_0# IN IN IN IN 17 17 17 17 SOC_DDR3B_EDQSP_4 SOC_DDR3B_EDQSN_4 SOC_DDR3B_EDQSP_5 SOC_DDR3B_EDQSN_5 IN IN IN IN 17 17 SOC_DDR3B_EDM_4 SOC_DDR3B_EDM_5 IN IN M2 N8 M3 L3 K3 J3 L2 F3 G3 C7 B7 17 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 B9 D1 D8 E2 E8 F9 G1 G9 E7 D3 17,28,29 17,28,29 17,28,29 SOC_DDR3B_ECKP_0 SOC_DDR3B_ECKN_0 SOC_DDR3B_ECKE_0 IN IN IN 17,28,29 SOC_DDR3B_EODT_0 IN 17,28,29 SOC_DDR3B_EMRESETN IN J7 K7 K9 K1 T2 R784 17,28,29 SOC_DDR3B_EA[0..15] N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 240 1% IN SOC_DDR3B_EA15 L8 J1 J9 L1 L9 M7 Samsung_K4B4G1646D-BCK0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 BA0 BA1 BA2 WE CAS RAS CS DQSL DQSL DQSU DQSU DML DMU CK CK CKE ODT RESET ZQ NC_1 NC_2 NC_3 NC_4 NC_5 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9 C759 0.1uF 16V C774 0.1uF 16V C740 0.1uF 16V SOC_DDR3B_EA[0..15] Trace need 20 mil. C760 0.1uF 16V SOC_DDR3B_EDQ32 SOC_DDR3B_EDQ33 SOC_DDR3B_EDQ34 SOC_DDR3B_EDQ35 SOC_DDR3B_EDQ36 SOC_DDR3B_EDQ37 SOC_DDR3B_EDQ38 SOC_DDR3B_EDQ39 SOC_DDR3B_EDQ40 SOC_DDR3B_EDQ41 SOC_DDR3B_EDQ42 SOC_DDR3B_EDQ43 SOC_DDR3B_EDQ44 SOC_DDR3B_EDQ45 SOC_DDR3B_EDQ46 SOC_DDR3B_EDQ47 BI SOC_DDR3B_EDQ[32..39] 17 BI SOC_DDR3B_EDQ[40..47] 17 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 B9 D1 D8 E2 E8 F9 G1 G9 C Samsung_K4B4G1646D-BCK0 SOC_DDR3B_EA0 SOC_DDR3B_EA1 SOC_DDR3B_EA2 SOC_DDR3B_EA3 SOC_DDR3B_EA4 SOC_DDR3B_EA5 SOC_DDR3B_EA6 SOC_DDR3B_EA7 SOC_DDR3B_EA8 SOC_DDR3B_EA9 SOC_DDR3B_EA10 SOC_DDR3B_EA11 SOC_DDR3B_EA12 SOC_DDR3B_EA13 SOC_DDR3B_EA14 B 17,28,29 17,28,29 17,28,29 SOC_DDR3B_EBA_0 SOC_DDR3B_EBA_1 SOC_DDR3B_EBA_2 IN IN IN 17,28,29 17,28,29 17,28,29 17,28,29 SOC_DDR3B_EWE# SOC_DDR3B_ECAS# SOC_DDR3B_ERAS# SOC_DDR3B_ECS_0# IN IN IN IN 17 17 17 17 SOC_DDR3B_EDQSP_2 SOC_DDR3B_EDQSN_2 SOC_DDR3B_EDQSP_3 SOC_DDR3B_EDQSN_3 IN IN IN IN 17 17 SOC_DDR3B_EDM_2 SOC_DDR3B_EDM_3 IN IN 17,28,29 17,28,29 17,28,29 SOC_DDR3B_ECKP_0 SOC_DDR3B_ECKN_0 SOC_DDR3B_ECKE_0 IN IN IN 17,28,29 SOC_DDR3B_EODT_0 IN 17,28,29 SOC_DDR3B_EMRESETN IN SOC_DDR3B_EA[0..15] L3 K3 J3 L2 F3 G3 C7 B7 E7 D3 J7 K7 K9 K1 T2 240 1% IN SOC_DDR3B_EA15 A N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M2 N8 M3 R776 17,28,29 VCC1V5 U42 IN L8 J1 J9 L1 L9 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 BA0 BA1 BA2 WE CAS RAS CS DQSL DQSL DQSU DQSU DML DMU CK CK CKE ODT RESET ZQ NC_1 NC_2 NC_3 NC_4 NC_5 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 17,28,29 B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9 C746 0.1uF 16V C782 0.1uF 16V C744 0.1uF 16V C758 0.1uF 16V U39 IN SOC_DDR3B_EA0 SOC_DDR3B_EA1 SOC_DDR3B_EA2 SOC_DDR3B_EA3 SOC_DDR3B_EA4 SOC_DDR3B_EA5 SOC_DDR3B_EA6 SOC_DDR3B_EA7 SOC_DDR3B_EA8 SOC_DDR3B_EA9 SOC_DDR3B_EA10 SOC_DDR3B_EA11 SOC_DDR3B_EA12 SOC_DDR3B_EA13 SOC_DDR3B_EA14 C781 22uF 6.3V VCCB0V75REF Trace need 20 mil. C770 0.1uF 16V M8 H1 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 C752 0.1uF 16V SOC_DDR3B_EA[0..15] SOC_DDR3B_EDQ16 SOC_DDR3B_EDQ17 SOC_DDR3B_EDQ18 SOC_DDR3B_EDQ19 SOC_DDR3B_EDQ20 SOC_DDR3B_EDQ21 SOC_DDR3B_EDQ22 SOC_DDR3B_EDQ23 SOC_DDR3B_EDQ24 SOC_DDR3B_EDQ25 SOC_DDR3B_EDQ26 SOC_DDR3B_EDQ27 SOC_DDR3B_EDQ28 SOC_DDR3B_EDQ29 SOC_DDR3B_EDQ30 SOC_DDR3B_EDQ31 BI BI SOC_DDR3B_EDQ[16..23] SOC_DDR3B_EDQ[24..31] 17 17,28,29 17,28,29 17,28,29 SOC_DDR3B_EBA_0 SOC_DDR3B_EBA_1 SOC_DDR3B_EBA_2 IN IN IN 17,28,29 17,28,29 17,28,29 17,28,29 SOC_DDR3B_EWE# SOC_DDR3B_ECAS# SOC_DDR3B_ERAS# SOC_DDR3B_ECS_0# IN IN IN IN 17 17 17 17 SOC_DDR3B_EDQSP_6 SOC_DDR3B_EDQSN_6 SOC_DDR3B_EDQSP_7 SOC_DDR3B_EDQSN_7 IN IN IN IN 17 17 SOC_DDR3B_EDM_6 SOC_DDR3B_EDM_7 IN IN M2 N8 M3 L3 K3 J3 L2 F3 G3 C7 B7 17 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 B9 D1 D8 E2 E8 F9 G1 G9 E7 D3 17,28,29 17,28,29 17,28,29 SOC_DDR3B_ECKP_0 SOC_DDR3B_ECKN_0 SOC_DDR3B_ECKE_0 IN IN IN 17,28,29 SOC_DDR3B_EODT_0 IN 17,28,29 SOC_DDR3B_EMRESETN IN J7 K7 K9 K1 T2 R771 17,28,29 SOC_DDR3B_EA[0..15] N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 240 1% IN SOC_DDR3B_EA15 L8 J1 J9 L1 L9 M7 Samsung_K4B4G1646D-BCK0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 BA0 BA1 BA2 WE CAS RAS CS DQSL DQSL DQSU DQSU DML DMU CK CK CKE ODT RESET ZQ NC_1 NC_2 NC_3 NC_4 NC_5 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9 C739 0.1uF 16V SOC_DDR3B_EDQ48 SOC_DDR3B_EDQ49 SOC_DDR3B_EDQ50 SOC_DDR3B_EDQ51 SOC_DDR3B_EDQ52 SOC_DDR3B_EDQ53 SOC_DDR3B_EDQ54 SOC_DDR3B_EDQ55 SOC_DDR3B_EDQ56 SOC_DDR3B_EDQ57 SOC_DDR3B_EDQ58 SOC_DDR3B_EDQ59 SOC_DDR3B_EDQ60 SOC_DDR3B_EDQ61 SOC_DDR3B_EDQ62 SOC_DDR3B_EDQ63 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 B9 D1 D8 E2 E8 F9 G1 G9 C786 22uF 6.3V B BI SOC_DDR3B_EDQ[48..55] 17 BI SOC_DDR3B_EDQ[56..63] 17 DSPM-8305E Designed for TI by ADVANTECH Title DDR3 Date: 2 C748 0.1uF 16V A C 3 C738 0.1uF 16V Trace need 20 mil. Samsung_K4B4G1646D-BCK0 4 C331 0.1uF 16V C754 0.1uF 16V M8 H1 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 C763 0.1uF 16V VCCB0V75REF Size 5 C785 22uF 6.3V D VCC1V5 17,28,29 C747 0.1uF 16V VCCB0V75REF M8 H1 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 C735 0.1uF 16V Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 28 of 43 5 4 3 2 1 D D FOR ECC USE VCC1V5 17,28,29 C SOC_DDR3B_EA[0..15] U41 IN SOC_DDR3B_EA0 SOC_DDR3B_EA1 SOC_DDR3B_EA2 SOC_DDR3B_EA3 SOC_DDR3B_EA4 SOC_DDR3B_EA5 SOC_DDR3B_EA6 SOC_DDR3B_EA7 SOC_DDR3B_EA8 SOC_DDR3B_EA9 SOC_DDR3B_EA10 SOC_DDR3B_EA11 SOC_DDR3B_EA12 SOC_DDR3B_EA13 SOC_DDR3B_EA14 17,28 17,28 17,28 SOC_DDR3B_EBA_0 SOC_DDR3B_EBA_1 SOC_DDR3B_EBA_2 IN IN IN 17,28 17,28 17,28 17,28 SOC_DDR3B_EWE# SOC_DDR3B_ECAS# SOC_DDR3B_ERAS# SOC_DDR3B_ECS_0# IN IN IN IN 17 17 SOC_DDR3B_EDQSP_8 SOC_DDR3B_EDQSN_8 17 17,28 17,28 17,28 SOC_DDR3B_EDM_8 IN IN VCC1V5 IN SOC_DDR3B_ECKP_0 SOC_DDR3B_ECKN_0 SOC_DDR3B_ECKE_0 M2 N8 M3 L3 K3 J3 L2 R758 R745 4.7K 4.7K F3 G3 C7 B7 R754 4.7K E7 D3 J7 K7 K9 IN IN IN 17,28 SOC_DDR3B_EODT_0 IN 17,28 SOC_DDR3B_EMRESETN IN K1 T2 R778 17,28,29 SOC_DDR3B_EA[0..15] 240 1% IN SOC_DDR3B_EA15 B N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 L8 J1 J9 L1 L9 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 BA0 BA1 BA2 WE CAS RAS CS VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSL DQSL DQSU DQSU DML DMU CK CK CKE ODT RESET ZQ NC_1 NC_2 NC_3 NC_4 NC_5 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9 C788 0.1uF 16V C737 0.1uF 16V C755 0.1uF 16V C736 0.1uF 16V C777 0.1uF 16V C789 22uF 6.3V VCCB0V75REF M8 H1 SOC_DDR3B_ECC0 E3 SOC_DDR3B_ECC1 F7 SOC_DDR3B_ECC2 F2 SOC_DDR3B_ECC3 F8 SOC_DDR3B_ECC4 H3 SOC_DDR3B_ECC5 H8 SOC_DDR3B_ECC6 G2 SOC_DDR3B_ECC7 H7 D7 ECC_NU R751 4.7K C3 R749 4.7K C8 R752 4.7K C2 R753 4.7K A7 R747 4.7K A2 R744 4.7K B8 R748 4.7K A3 R746 4.7K Trace need 20 mil. C771 0.1uF 16V BI SOC_DDR3B_ECC[0..7] C 17 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 B9 D1 D8 E2 E8 F9 G1 G9 B Samsung_K4B4G1646D-BCK0 A A DSPM-8305E Designed for TI by ADVANTECH Title DDR3_ECC Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 29 of 43 5 4 3 SOC_DDR3A_EDQ[0..63] SOC_DDR3A_ECC[0..7] 2 1 16 16 DIMM1B 16 SOC_DDR3A_EA[0..15] IN D 16 16 16 16 16 16 16 16 16 16 16 16 16 16 VCC3V3_AUX R421 4.7K R428 4.7K DIMM_SA0 DIMM_SA1 R410 NL/0 SOC_DDR3A_EBA_0 SOC_DDR3A_EBA_1 SOC_DDR3A_EBA_2 SOC_DDR3A_ECS_0# SOC_DDR3A_ECS_1# SOC_DDR3A_ECKP_0 SOC_DDR3A_ECKN_0 SOC_DDR3A_ECKP_1 SOC_DDR3A_ECKN_1 SOC_DDR3A_ECKE_0 SOC_DDR3A_ECKE_1 SOC_DDR3A_ECAS# SOC_DDR3A_ERAS# SOC_DDR3A_EWE# 18 18 R432 NL/0 16 16 C GND 16 16 DIMM_SCL DIMM_SDA SOC_DDR3A_EODT_0 SOC_DDR3A_EODT_1 16 SOC_DDR3A_EDM_0 16 SOC_DDR3A_EDM_1 16 SOC_DDR3A_EDM_2 16 SOC_DDR3A_EDM_3 16 SOC_DDR3A_EDM_4 16 SOC_DDR3A_EDM_5 16 SOC_DDR3A_EDM_6 16 SOC_DDR3A_EDM_7 SOC_DDR3A_EDQSP_[0..7] SOC_DDR3A_EDQSN_[0..7] 16 16 16 IN IN IN IN IN IN IN IN IN IN IN IN IN IN DIMM1A SOC_DDR3A_EA0 SOC_DDR3A_EA1 SOC_DDR3A_EA2 SOC_DDR3A_EA3 SOC_DDR3A_EA4 SOC_DDR3A_EA5 SOC_DDR3A_EA6 SOC_DDR3A_EA7 SOC_DDR3A_EA8 SOC_DDR3A_EA9 SOC_DDR3A_EA10 SOC_DDR3A_EA11 SOC_DDR3A_EA12 SOC_DDR3A_EA13 SOC_DDR3A_EA14 SOC_DDR3A_EA15 107 105 106 103 104 99 100 98 97 92 117 96 95 130 90 88 DIMM_SA0 DIMM_SA1 DIMM_SCL DIMM_SDA 119 108 91 127 129 111 113 112 114 87 89 125 122 121 197 201 202 200 126 128 IN IN 11 28 44 59 140 157 172 189 IN IN IN IN IN IN IN IN IN IN SOC_DDR3A_EDQSP_8 SOC_DDR3A_EDQSN_8 IN IN SOC_DDR3A_EDM_8 IN SOC_DDR3A_EDQSP_0 SOC_DDR3A_EDQSP_1 SOC_DDR3A_EDQSP_2 SOC_DDR3A_EDQSP_3 SOC_DDR3A_EDQSP_4 SOC_DDR3A_EDQSP_5 SOC_DDR3A_EDQSP_6 SOC_DDR3A_EDQSP_7 SOC_DDR3A_EDQSN_0 SOC_DDR3A_EDQSN_1 SOC_DDR3A_EDQSN_2 SOC_DDR3A_EDQSN_3 SOC_DDR3A_EDQSN_4 SOC_DDR3A_EDQSN_5 SOC_DDR3A_EDQSN_6 SOC_DDR3A_EDQSN_7 12 27 45 62 141 156 173 188 10 25 43 60 139 154 171 186 SOC_DDR3A_EDQSP_8 SOC_DDR3A_EDQSN_8 77 75 76 120 118 DDR3-SODIMM-DDRSK-ECC A0 A1 SODIMM204 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2 CS0 CS1 CK0 CK0 CK1 CK1 CKE0 CKE1 CAS RAS WE SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DQS8 DM8 CS2 CS3 1of2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 5 7 13 15 4 6 16 18 19 21 31 33 22 24 34 36 37 39 49 51 40 42 48 50 55 57 63 65 54 56 66 68 133 135 145 147 134 136 142 144 151 153 159 161 148 150 160 162 165 167 177 179 166 168 174 176 183 185 191 193 180 182 192 194 69 71 81 83 72 74 80 82 SOC_DDR3A_EDQ0 SOC_DDR3A_EDQ1 SOC_DDR3A_EDQ2 SOC_DDR3A_EDQ3 SOC_DDR3A_EDQ4 SOC_DDR3A_EDQ5 SOC_DDR3A_EDQ6 SOC_DDR3A_EDQ7 SOC_DDR3A_EDQ8 SOC_DDR3A_EDQ9 SOC_DDR3A_EDQ10 SOC_DDR3A_EDQ11 SOC_DDR3A_EDQ12 SOC_DDR3A_EDQ13 SOC_DDR3A_EDQ14 SOC_DDR3A_EDQ15 SOC_DDR3A_EDQ16 SOC_DDR3A_EDQ17 SOC_DDR3A_EDQ18 SOC_DDR3A_EDQ19 SOC_DDR3A_EDQ20 SOC_DDR3A_EDQ21 SOC_DDR3A_EDQ22 SOC_DDR3A_EDQ23 SOC_DDR3A_EDQ24 SOC_DDR3A_EDQ25 SOC_DDR3A_EDQ26 SOC_DDR3A_EDQ27 SOC_DDR3A_EDQ28 SOC_DDR3A_EDQ29 SOC_DDR3A_EDQ30 SOC_DDR3A_EDQ31 SOC_DDR3A_EDQ32 SOC_DDR3A_EDQ33 SOC_DDR3A_EDQ34 SOC_DDR3A_EDQ35 SOC_DDR3A_EDQ36 SOC_DDR3A_EDQ37 SOC_DDR3A_EDQ38 SOC_DDR3A_EDQ39 SOC_DDR3A_EDQ40 SOC_DDR3A_EDQ41 SOC_DDR3A_EDQ42 SOC_DDR3A_EDQ43 SOC_DDR3A_EDQ44 SOC_DDR3A_EDQ45 SOC_DDR3A_EDQ46 SOC_DDR3A_EDQ47 SOC_DDR3A_EDQ48 SOC_DDR3A_EDQ49 SOC_DDR3A_EDQ50 SOC_DDR3A_EDQ51 SOC_DDR3A_EDQ52 SOC_DDR3A_EDQ53 SOC_DDR3A_EDQ54 SOC_DDR3A_EDQ55 SOC_DDR3A_EDQ56 SOC_DDR3A_EDQ57 SOC_DDR3A_EDQ58 SOC_DDR3A_EDQ59 SOC_DDR3A_EDQ60 SOC_DDR3A_EDQ61 SOC_DDR3A_EDQ62 SOC_DDR3A_EDQ63 VCC1V5 85 86 93 94 101 102 109 110 115 116 123 124 131 132 VCC3V3_AUX C734 0.1uF 16V C733 2.2uF 199 DDR3-SODIMM-DDRSK-ECC VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 SODIMM204 VDDSPD 10V GND 16 GND SOC_DDR3A_EMRESETN 198 30 1 84 VCCA0V75REF C160 2.2uF 6.3V C161 0.1uF 16V C625 2.2uF 6.3V C247 0.1uF 16V VCCA0V75REF 2 3 8 9 14 17 20 23 26 29 32 35 38 41 46 EVENT RESET VREF_DQ VREF_CA VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VTT1 VTT2 NPTH_1 NPTH_2 SMDFIX_1 SMDFIX_2 2of2 47 52 53 58 61 64 67 70 73 78 79 137 138 143 146 149 152 155 158 163 164 169 170 175 178 181 184 187 190 195 196 D 203 204 VCCA0V75 C H1 H2 H3 H4 SODIMMDDR3_204 <Characteristic> VCC1V5 C289 22uF 6.3V SOC_DDR3A_ECC0 SOC_DDR3A_ECC1 SOC_DDR3A_ECC2 SOC_DDR3A_ECC3 SOC_DDR3A_ECC4 SOC_DDR3A_ECC5 SOC_DDR3A_ECC6 SOC_DDR3A_ECC7 C299 22uF 6.3V VCCA0V75 C256 22uF 6.3V C242 22uF 6.3V C264 22uF 6.3V C352 0.1uF 16V C353 0.1uF 16V VCCA0V75 C741 0.1uF 16V C359 1uF 6.3V C357 1uF 6.3V C358 1uF 6.3V VCC1V5 SODIMMDDR3_204 <Characteristic> C304 1uF 6.3V B C275 1uF 6.3V C266 1uF 6.3V C305 1uF 6.3V C285 1uF 6.3V C250 1uF 6.3V B A A Designed for TI by ADVANTECH Title DDR3 SODIMM Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 30 of 43 5 4 3 2 1 SoC UART1 TO USB 3.3V @0.65A 5 C1 0.1uF 16V R3 1K D VIN EN NC1 NC2 NC3 C7 10uF 6.3V VOUT FB 1 R19 17.4K 1% R20 10K 1% R4 10K VCC18_U C21 0.1uF 16V C12 10uF 6.3V C19 0.1uF 16V C37 0.1uF 16V C25 0.1uF 16V C17 0.1uF 16V C36 0.1uF 16V VPHY VPLL 0.1uF 16V GND_USB1 3 90 OHM DIFF. IMPEDANCE CONTROL R483 1 NPH_1 NPH_2 GND_2 49 USB_DM1 7 USB_DP1 8 5 D1 TPD4S012DRYR VCC3V3_U R16 12.1K 1% 1K FT2232HL_RESET#1 1% 6 14 6 VCC5_VBUS 62 10KV VCC3V3_U 31 C388 0.1uF 16V 5 4 63 FOR EMI VREGIN ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 VREGOUT 0.1uF 16V 2 4 VCC18_U DM DP ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 REF RESET 10 11 MINIUSB_5H GND_1 C27 2 Mini-AB DATADATA+ 1 50 VCC3V3_U 3 PTH_1 PTH_2 PTH_3 PTH_4 6 7 8 9 R26 0 5% +5V R477 4.7K 61 EECS EECLK BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4 BCBUS5 BCBUS6 BCBUS7 EEDATA GND_USB1 C33 8 7 6 5 VCC NC ORG GND CS SK DI DO 1 2 3 4 2 33pF 50V OSCI Y1 12MHz_20pF C28 R482 2.2K R484 10K 33pF 50V 3 13 U46 ATMEL_AT93C46DN-SH-T BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 OSCO TEST VCC3V3_U B4 0.5A 120_100MHz PWREN SUSPEND C3 0.1uF 16V C384 0.1uF 16V 16 17 18 19 21 22 23 24 OUT IN FTDI_SOC_U0RX SOC_UART0_TXD_3V3 OUT IN FTDI_MCU_U0RX MCU_PA1_U0TX 18 C 18,36 26 27 28 29 30 32 33 34 48 52 53 54 55 57 58 59 38 39 40 41 43 44 45 46 60 36 36 36,37 TP6 TP1 B GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 AGND 10 GND_USB1 1 5 11 15 25 35 47 51 B 31 C24 0.1uF 16V Vout=(R1+R2)/R2*1.204 3.298V = (17.4k+10k)/10k*1.204 VCC3V3_U 20 31 42 56 U3 C35 FTDI_USB R2 VPLL1 VPHY1 VCC5_VBUS C D R1 VPHY1 C26 0.01uF 16V 31 150mA VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_4 1K_100MHz 0.4A 500mA 12 37 64 B6 VCC3V3_U C15 10uF 6.3V VPLL1 C20 0.01uF 16V VCORE_1 VCORE_2 VCORE_3 1K_100MHz 0.4A 4 9 B5 VCC3V3_U VCC3V3_U 3 4 9 8 VCC5_VBUS GND EPAD 2 6 7 Q1 TI_TPS73701DRBT FTDI_FT2232HL A A DSPM-8305E Designed for TI by ADVANTECH Title SoC UART1 TO USB Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 31 of 43 4 3 14,33,39 14,33,39 13 SOC_MDC_3V3 SOC_MDIO_3V3 PHY1_INT# VCC2V5 IN BI OUT 4.7K P0_COL_PD E2 D1 E1 F2 F1 G2 G3 H2 H1 H3 J1 J2 C1 B1 D2 B2 D3 C3 B3 C4 A1 A2 C5 B5 B6 L3 M1 L1 R679 10K TP75 C P0_CONFIG0 P0_CONFIG1 P0_CONFIG2 P0_CONFIG3 P0_CONFIG4 P0_CONFIG5 P0_CONFIG6 P0_CLKSEL K2 D8 E9 F8 G7 F9 G9 G8 H8 C6 C7 D7 E3 E7 F3 J3 J7 M3 M4 M7 M8 N5 B7 AVDD_1 AVDD_2 AVDD_3 AVDD_4 AVDD_5 AVDD_6 K9 L2 B4 C2 K1 R726 GTX_CLK TX_CLK TX_EN TX_ER TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 RX_CLK RX_DV RX_ER RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS COL MDI3+ MDI3MDI2+ MDI2MDI1+ MDI1MDI0+ MDI0S_IN+ S_INS_OUT+ S_OUTS_CLK+ S_CLK- 88E1111-BAB LED_LINK10 LED_LINK100 LED_LINK1000 LED_DUPLEX LED_RX LED_TX MARVELL_88E1111-B2-BAB1C000 TDI TMS TCK TRST TDO MDC MDIO INT 125CLK CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 SEL_FREQ HSDAC+ HSDACRSET RESET COMA XTAL1 XTAL2 NC_1 NC_2 D4 G6 J5 J6 K4 K5 K6 L5 L6 D5 D6 E4 E5 E6 F4 F5 F6 G4 G5 H4 H5 H6 J4 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 G1 K7 VCC1V2 N8 N9 N6 N7 N3 N4 N1 N2 A3 A4 A7 A8 A5 A6 BI BI BI BI BI BI BI BI LAN0_TRD2_3P LAN0_TRD2_3N LAN0_TRD2_2P LAN0_TRD2_2N LAN0_TRD2_1P LAN0_TRD2_1N LAN0_TRD2_0P LAN0_TRD2_0N SOC_SGMII0_TXP_C C666 SOC_SGMII0_TXN_C C675 SOC_SGMII0_RXP SOC_SGMII0_RXN R704 4.99K 1% R715 4.99K 1% 34 34 34 34 34 34 34 34 0.1uF 16V 0.1uF 16V P0_CONFIG2 P0_CONFIG5 LED0_TX D 10K R728 0 R736 0 LAN0_LED_LINK10 R738 0 LAN0_LED_LINK1000 R737 0 R729 0 R730 0 R727 0 VCC2V5 VCC2V5 110 P0_CONFIG1 100 IN IN OUT OUT SOC_SGMII0_TXP SOC_SGMII0_TXN SOC_SGMII0_RXP SOC_SGMII0_RXN P0_CONFIG4 14 14 14 14 100 P0_CONFIG3 LED0_DUPLEX 011 000 LAN0_LED_LINK10 LED0_DUPLEX R735 111 P0_CONFIG0 C8 B8 A9 E8 C9 D9 P0_CLKSEL NL/10K OUT OUT LAN0_LED_LINK100 LAN0_LED_LINK1000 OUT LAN0_LED_RX P0_CONFIG6 34 34 000 34 TP93 L7 L8 L9 M9 K8 R796 4.7K M5 M6 *R373 close to chip M2 P0_RSET K3 L4 R_P0_LAN_RSTz H9 J9 PHY_P0_XTAL1 PHY_P0_XTAL2 R678 R660 C 4.99K 1% 0 PHY_RSTz IN PHY_RSTz 33,36 R659 4.99K 1% VSSC R709 4.7K NL/4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 1 H7 R663 R677 R676 R662 R675 R674 R666 R664 R673 R665 R672 R661 GTX_CLK_0 TX_CLK_0 TX_EN_0 TX_ER_0 TXD0_0 TXD1_0 TXD2_0 TXD3_0 TXD4_0 TXD5_0 TXD6_0 TXD7_0 VDDO_1 VDDO_2 VDDO_3 D AVCC2V5A VDDOX_1 VDDOX_2 VDDOH_1 VDDOH_2 VDDOH_3 PHY1 B9 F7 J8 VCC2V5 2 DVDD_1 DVDD_2 DVDD_3 DVDD_4 DVDD_5 DVDD_6 DVDD_7 DVDD_8 5 PHY_P0_XTAL1_R R725 0 Y4 25MHz_20pF PHY_P0_XTAL1 5% PHY_P0_XTAL2 C719 27pF 50V 88E1111 Device Pin to Configuration Bit Mapping B Pin CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 Bit[2] Bit[1] PHYADR[2] ENA_PAUSE ANEG[3] ANEG[0] HWCFG_MODE[2] DIS_FC SEL_TWSI PHYADR[1] PHYADR[4] ANEG[2] ENA_XC HWCFG_MODE[1] DIS_SLEEP INT_POL Pin A CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 000 100 111 011 100 110 000 1 Pin to Constant Mapping Pin Bit[0] Bit[2:0] B VDDO LED_LINK10 LED_LINK100 LED_LINK1000 LED_DUPLEX LED_RX LED_TX VSS PHYADR[0] PHYADR[3] ANEG[1] DIS_125 HWCFG_MODE[0] HWCFG_MODE[3] 75/50 OHM 111 110 101 100 011 010 001 000 AVCC2V5A VCC2V5 B33 0.5A 120_100MHz C278 0.01uF 16V C296 0.1uF 16V C271 4.7uF 6.3V C270 0.1uF 16V C297 4.7uF 6.3V C273 0.01uF 16V C262 0.1uF 16V C287 0.1uF 16V C261 4.7uF 6.3V C254 4.7uF 6.3V VCC1V2 CONFIG Pin Connection LED Pin Connection C718 27pF 50V PHY Address = 0x00 Hardware Configuration Bit Setting PHY Configuration C268 0.01uF 16V LED_TX LED_LINK1000 VDDO LED_DUPLEX PHY Address bit[2:0] 000 LED_LINK1000 LED_LINK10 VSS SGMII without Clock with SGMII Auto-Neg to copper C290 0.01uF 16V C274 0.1uF 16V C295 4.7uF 6.3V Enable Pause ,PHY Address bit[4:3] = 00 A Auto-Neg advertise all capabilities ,prefer Master Enable MDI crossover, disable 125CLK DSPM-8305E Designed for TI by ADVANTECH Disable fiber /copper Auto-detect, Disable sleep Select MDIO interface, INT signal active high, 50 ohm SERDES Title Gigabit Ethernet PHY1 Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 32 of 43 4 3 SOC_MDC_3V3 SOC_MDIO_3V3 13 PHY2_INT# VCC2V5 IN BI OUT 4.7K P1_COL_PD E2 D1 E1 F2 F1 G2 G3 H2 H1 H3 J1 J2 C1 B1 D2 B2 D3 C3 B3 C4 A1 A2 C5 B5 B6 L3 M1 L1 R603 10K TP61 C P1_CONFIG0 P1_CONFIG1 P1_CONFIG2 P1_CONFIG3 P1_CONFIG4 P1_CONFIG5 P1_CONFIG6 P1_CLKSEL K2 D8 E9 F8 G7 F9 G9 G8 H8 C6 C7 D7 E3 E7 F3 J3 J7 M3 M4 M7 M8 N5 B7 AVDD_1 AVDD_2 AVDD_3 AVDD_4 AVDD_5 AVDD_6 K9 L2 B4 C2 K1 R643 GTX_CLK TX_CLK TX_EN TX_ER TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 RX_CLK RX_DV RX_ER RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS COL MDI3+ MDI3MDI2+ MDI2MDI1+ MDI1MDI0+ MDI0S_IN+ S_INS_OUT+ S_OUTS_CLK+ S_CLK- 88E1111-BAB LED_LINK10 LED_LINK100 LED_LINK1000 LED_DUPLEX LED_RX LED_TX MARVELL_88E1111-B2-BAB1C000 TDI TMS TCK TRST TDO MDC MDIO INT 125CLK CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 SEL_FREQ HSDAC+ HSDACRSET RESET COMA XTAL1 XTAL2 NC_1 NC_2 D4 G6 J5 J6 K4 K5 K6 L5 L6 D5 D6 E4 E5 E6 F4 F5 F6 G4 G5 H4 H5 H6 J4 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 G1 K7 VCC1V2 N8 N9 N6 N7 N3 N4 N1 N2 A3 A4 A7 A8 A5 A6 BI BI BI BI BI BI BI BI LAN1_TRD2_3P LAN1_TRD2_3N LAN1_TRD2_2P LAN1_TRD2_2N LAN1_TRD2_1P LAN1_TRD2_1N LAN1_TRD2_0P LAN1_TRD2_0N SOC_SGMII1_TXP_C C507 SOC_SGMII1_TXN_C C512 SOC_SGMII1_RXP SOC_SGMII1_RXN R627 4.99K 1% R634 4.99K 1% 34 34 34 34 34 34 34 34 P1_CONFIG2 P1_CONFIG5 L7 L8 L9 M9 K8 R797 D 10K R645 0 R653 0 LAN1_LED_LINK10 R655 0 LAN1_LED_LINK1000 R654 0 R646 0 LED_DUPLEX R647 0 LED_TX R644 0 VCC2V5 VCC2V5 110 P1_CONFIG1 100 0.1uF 16V 0.1uF 16V IN IN OUT OUT LAN1_LED_LINK10 LAN1_LED_LINK100 LAN1_LED_LINK100 OUT LAN1_LED_LINK1000 LAN1_LED_LINK1000 OUT LED_DUPLEX LAN1_LED_RX LAN1_LED_RX 34 OUT LED_TX R652 111 SOC_SGMII1_TXP SOC_SGMII1_TXN SOC_SGMII1_RXP SOC_SGMII1_RXN P1_CONFIG4 14 14 14 14 100 P1_CONFIG3 011 P1_CONFIG0 C8 B8 A9 E8 C9 D9 P1_CLKSEL NL/10K 001 P1_CONFIG6 34 34 000 4.7K M5 M6 *R405 close to chip M2 P1_RSET K3 L4 R_P1_LAN_RSTz H9 J9 PHY_P1_XTAL1 PHY_P1_XTAL2 R602 R589 C 4.99K 1% 0 PHY_RSTz IN PHY_RSTz 32,36 R588 4.99K 1% VSSC R631 14,32,39 14,32,39 4.7K NL/4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 1 H7 R592 R601 R600 R591 R599 R598 R595 R593 R597 R594 R596 R590 GTX_CLK TX_CLK TX_EN TX_ER TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 VDDO_1 VDDO_2 VDDO_3 D AVCC2V5B VDDOX_1 VDDOX_2 VDDOH_1 VDDOH_2 VDDOH_3 PHY2 B9 F7 J8 VCC2V5 2 DVDD_1 DVDD_2 DVDD_3 DVDD_4 DVDD_5 DVDD_6 DVDD_7 DVDD_8 5 PHY_P1_XTAL1_R R642 0 Y3 25MHz_20pF PHY_P1_XTAL1 5% PHY_P1_XTAL2 C570 27pF 50V 88E1111 Device Pin to Configuration Bit Mapping B Pin CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 Bit[2] Bit[1] PHYADR[2] ENA_PAUSE ANEG[3] ANEG[0] HWCFG_MODE[2] DIS_FC SEL_TWSI PHYADR[1] PHYADR[4] ANEG[2] ENA_XC HWCFG_MODE[1] DIS_SLEEP INT_POL Pin A CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 001 100 111 011 100 110 000 1 Pin to Constant Mapping Pin Bit[0] Bit[2:0] B VDDO LED_LINK10 LED_LINK100 LED_LINK1000 LED_DUPLEX LED_RX LED_TX VSS PHYADR[0] PHYADR[3] ANEG[1] DIS_125 HWCFG_MODE[0] HWCFG_MODE[3] 75/50 OHM 111 110 101 100 011 010 001 000 AVCC2V5B VCC2V5 B27 0.5A 120_100MHz C202 0.01uF 16V C211 0.1uF 16V C194 4.7uF 6.3V C198 0.1uF 16V C212 4.7uF 6.3V C195 0.01uF 16V C204 0.1uF 16V C189 0.1uF 16V C185 4.7uF 6.3V C188 4.7uF 6.3V VCC1V2 CONFIG Pin Connection LED Pin Connection C569 27pF 50V PHY Address = 0x01 Hardware Configuration Bit Setting PHY Configuration C206 0.01uF 16V LED_TX LED_LINK1000 VDDO LED_DUPLEX PHY Address bit[2:0] 001 LED_LINK1000 LED_LINK10 VSS SGMII without Clock with SGMII Auto-Neg to copper C192 0.01uF 16V C193 0.1uF 16V C213 4.7uF 6.3V Enable Pause ,PHY Address bit[4:3] = 00 A Auto-Neg advertise all capabilities ,prefer Master Enable MDI crossover, disable 125CLK DSPM-8305E Designed for TI by ADVANTECH Disable fiber /copper Auto-detect, Disable sleep Select MDIO interface, INT signal active high, 50 ohm SERDES Title Gigabit Ethernet PHY2 Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 33 of 43 5 4 3 2 1 Bi-Color LED's on RJ45 controls from PHY CN16 32 LAN0_LED_LINK100 IN 32 LAN0_LED_LINK1000 IN R371 220 5% 5482S_LAN1_SPEED2_R A13 R382 220 5% 5482S_LAN1_SPEED1_R A14 B34 120_100MHz 0.5A VCC2V5 LAN-BI[ 88E1111 Output Port0] D LED2 (GREEN) 1G LED1 (ORANGE) 0 100M 1 10M 0 NO LINK BLINKING 0 BLINKING 0 1 BLINKING 1 LAN0_TRD2_0P BI 32 LAN0_TRD2_0N BI 32 LAN0_TRD2_1P BI 32 LAN0_TRD2_1N BI 32 LAN0_TRD2_2P BI 32 LAN0_TRD2_2N BI 32 LAN0_TRD2_3P BI 5482S_RJ451_VCC A5 A1 TP0+ 1 D LED3 (GREEN) 1 32 O G 0 32 LAN0_TRD2_3N A2 0.1uF 75 0.1uF 75 A3 A4 TP1+ A7 A8 BI 0.1uF 75 0.1uF 75 32 LAN0_LED_RX IN 220 5% 5482S_LAN1_LINK_R 33 LAN1_LED_LINK100 IN 33 LAN1_LED_LINK1000 IN C LED2 (GREEN) 1G 100M 10M NO LINK 0 1 0 1 LED1 (ORANGE) LED3 (GREEN) 1 BLINKING 0 BLINKING 0 BLINKING 1 LAN1_TRD2_0P BI 33 LAN1_TRD2_0N BI 33 LAN1_TRD2_1P BI 33 LAN1_TRD2_1N BI 33 LAN1_TRD2_2P BI 33 LAN1_TRD2_2N BI 33 LAN1_TRD2_3P BI LAN1_TRD2_3N 33 LAN1_LED_RX TP3- 7 8 H1 H2 H3 H4 1000pF 2kV 220 5% G 5482S_LAN2_SPEED2_R B13 SHIELD GND 5482S_LAN2_SPEED1_R B14 5% 0 5% O 5482S_RJ452_VCC 120_100MHz 0.5A G B5 B1 B2 TP0+ 1 75 0.1uF B3 TP0TP1+ 2 3 C B4 75 0.1uF B7 B8 0.1uF 75 0.1uF 75 B9 B10 BI R327 IN 220 5% 5482S_LAN2_LINK_R 4 5 TP2- 6 TP3+ TP3- 7 8 1000pF 2kV B11 B12 VCC2V5 TP1TP2+ B6 0 5 GND_SHIELD 33 33 220 B30 VCC2V5 LAN-BI[ 88E1111 Output Port1] 4 R613 R333 R335 3 A11 A12 VCC2V5 2 TP2- 6 TP3+ A6 R350 TP1TP2+ A9 A10 TP0- G SHIELD GND RJ45_2x1_W/XFMR&LED <Characteristic> R618 49.9 1% R624 49.9 1% LAN1_TRD2_0P C201 0.01uF 16V C246 0.01uF 16V C209 0.01uF 16V 49.9 1% R630 49.9 1% LAN1_TRD2_1P 16V R633 49.9 1% R636 49.9 1% C644 0.01uF 16V R637 49.9 0.01uF 16V R641 49.9 SoC Socket 1% R695 49.9 1% R700 49.9 1% 0.01uF 16V R705 49.9 1% R710 49.9 1% R717 49.9 1% 1% LAN0_TRD2_0P 5482S_RJ452_VCC 5482S_RJ451_VCC C217 0.01uF 16V C220 0.01uF 16V C263 0.01uF 16V C255 0.01uF 16V LAN0_TRD2_2N Close to MAGNETICS less than 0.25 inches Close to MAGNETICS less than 0.25 inches LAN0_TRD2_3P 1% LAN1_TRD2_3P C572 49.9 LAN0_TRD2_2P C294 LAN1_TRD2_2N B 1% R689 LAN0_TRD2_1N LAN1_TRD2_2P 0.01uF 1% 49.9 LAN0_TRD2_1P LAN1_TRD2_1N C214 49.9 R681 LAN0_TRD2_0N LAN1_TRD2_0N R626 R680 C714 0.01uF 16V B LAN0_TRD2_3N LAN1_TRD2_3N AMC Hole On board Front panel and ESD Strip socket1 H3 H4 H6 H8 R6 NL/0 R5 NL/0 FM1 FM3 Fiducial Fiducial H7 1 R2 10M 1 5% R1 10M H5 H1 TRIP3 3 2 TRIP1 1 4 H107x17-NPTH <Characteristic> TRIP2 5% TRIP1 H27P35-MTH FM4 FM2 Fiducial Fiducial H2 ESD1 AMC-ESD-B TI_SOC_K2H_Socket <Characteristic> Key Zone A XDS200 Holes H1 2 H2 1 H35P7-MTH A (Bottom Side 3mm) Placed Capacitors CN1 1 Screw Hold Designed for TI by ADVANTECH NPTH 1 H35P7-MTH Title 88E1111 RJ45 POWER MODULE_5223957-3 <Characteristic> Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 34 of 43 5 4 3 2 1 VCC1V8 R471 USIM GPS C335 1uF 6.3V 0 C341 0.1uF 16V C382 0.1uF 16V D D GPS1 C776 VCC1V8 13 SOC_SIM_CLK SOC_SIM_RST SOC_SIM_IO R433 IN 0.1uF 16V GPS_ENABLE 0 R762 IN IN BI 10K GPS_RTC_CLK 18 18 NC4 I/O RST CLK U33 GPS_UARTRXD GPS_UARTTXD OUT IN R774 0 GPS_RF GPS_UARTRXD_R GPS_PPS SIM_VCC VCC1V8 SIM_EN SIM_SEL 1 2 3 4 C730 0.1uF 16V EN SEL VCC NC1 Exposed Thermal Pad NC3 SIM_CLK GND SIM_RST 12 11 10 9 SIM_CLK R408 4.7K 5% SIM_RST EPAD VBATT NC2 VSIM SIM_I/O 17 5 6 7 8 SIM_VCC B1 C3 B3 C1 A1 A2 B2 C329 1uF 6.3V Low (Default) C322 H2 1uF 6.3V VCC1V8 SIM_VCC VCC_SIM Value = 1.8V SIM_RST CN21(2-3) MINIJUMPER_2_2.54mm R419 1K SIM_CLK SIM_IO CN21 SIM_SEL SIM_EN 1 2 3 NU_19 NU_20 SMDFIX C1 C5 C2 C6 C3 C7 SW1 SW2 VCC1V8 OSC4 C338 0.1uF 16V PH_3x1V_2.54mm R430 10K 4 2 SMDFIX SIM_8H C337 0.1uF 16V H1 VCC1V8 C GNS_TC6000G <Characteristic> SIM CARD High VCC_SIM Value = 2.95V GPS NU_15 NU_16 NU_17 NU_18 D5 F4 SIM_SEL Clock GPS_RF GPS_TX GPS_RX GPS_PPS GPS_GND_1 GPS_GND_2 GPS_GND_3 NU_6 NU_7 NU_8 NU_9 NU_10 NU_11 NU_12 NU_13 NU_14 E4 F3 E5 E3 SIM1 TCXO_CLK RTC_CLK NU_1 NU_2 NU_3 NU_4 NU_5 GND_4 A5 A6 A3 A4 B6 C6 D6 B4 B5 TI_TXS4555RGTR <Characteristic> C C330 1uF 6.3V VDD VDD_IO GPS_ENABLE GND_3 Power GND_1 Management GND_2 F6 D1 D2 D3 D4 E6 SIM_IO VCC3V3_AUX E1 F1 C4 F5 E2 F2 C2 C5 TP95 16 15 14 13 18 18 18 MCU_GPS_ENABLE GPS-Module VCC GND OUT OE 32.768KHz <Characteristic> 3GPS_RTC_CLK_R 1 R423 22 GPS_RTC_CLK VCC1V8 B B FOR ANTENNA CIRCUIT VCC3V3_AUX CN17(4-6) MINIJUMPER_2_2.54mm CN17(7-8) MINIJUMPER_2_2.54mm CN17(1-2) MINIJUMPER_2_2.54mm L10 0.082uH 0.3A 1000pF 50V 1 C370 CN18 TSPUSHEVt0 TSCOMPOUT_E OUT IN CN17 1 3 5 7 2 4 6 8 IN OUT OUT SOC_TIMO1 RADSYNC PHYSYNC 3 18,39 12,20 12,20 4 PH_4x2V_2.54mm <Characteristic> RF_IN GPS_PPS 39 15,39 GND_2 GND_3 L11 3.6nH 0.3A GPS_RF C375 1.5pF 50V GND_1 GND_4 C369 NL/1.5pF 50V 2 5 RF_5H A A DSPM-8305E Designed for TI by ADVANTECH Title GPS & SIM CARD Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 35 of 43 5 4 3 2 1 MMC_GAPU VCC3V3_MP R501 3.3K SMB_SCL_IPMBL SMB_SDA_IPMBL R518 R526 33K 33K MMC_PS_N0 R528 10K MMC_GA0 5% 5% 5% R500 3.3K 5% R499 3.3K 5% MMC_GA1 MMC_GA2 U7 MCU_PA0_U0RX 31,37 13,25,26,27 25 13,25,26,27 13,25,26,27 18 18 MCU SPI0 I2C1 37 37 37 37 26 27 13 13 ICDI MCU SPI0 CS1~CS4 MCU_PA1_U0TX MCU_SPI0_CLK MCU_SPI0_CS0z MCU_SPI0_MISO MCU_SPI0_MOSI MCU_EXP_SCL MCU_EXP_SDA OUT OUT OUT IN OUT OUT BI MCU_JTAG_TCK MCU_JTAG_TMS MCU_JTAG_TDI MCU_JTAG_TDO MCU_SPI0_CS1z MCU_SPI0_CS2z MCU_SPI0_CS3z MCU_SPI0_CS4z IN BI IN OUT OUT OUT OUT OUT 38 38 SPI1 to LCD 38 18 18 37 32,33 12 NOR FLASH 21 21 GPIO to PMBUS MCU_SPI1_CLK MCU_SPI1_CS0z OUT OUT TP7 MCU_SPI1_MOSI SOC_I2C_EN PW_SEQ_I2C_EN PW_SEQ_RSTz PHY_RSTz OUT OUT OUT OUT OUT R98 MMC_ENABLE_N IN 18 NOR_WPz OUT R86 PCIECLK_MCU_PD OUT R75 PCIECLK_OE OUT 37 PMBUS_CTL OUT 37,40,41 PMBUS_ALERT OUT OUT 13 SPI_GPIO_RESET R131 R130 0 0 MCU_SPI0_CS3z MCU_SPI0_CS4z MCU_SPI1_MISO R515 0 0 0 0 SPI_GPIO_RESET MCU_BOOTSELECT WARM_RESETz FULL_RESETz RESET 19 C TRGRSTZ IN MCU_RESETz PA0/U0Rx PA1/U0Tx PA2/SSI0CLK PA3/SSI0Fss PA4/SSI0Rx PA5/SSI0Tx PA6 PA7 80 79 78 77 25 24 23 22 PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO PC4 PC5 PC6 PC7 74 75 95 96 6 5 2 1 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 19 18 17 16 41 40 37 36 4 2 C55 0.1uF 16V VCC GND OUT OE 3 1 MCUXOSC0_R R100 14 87 39 64 C70 Y2 16MHz MCUOSC0 48 MCUOSC1 49 10pF C71 10pF LM3S2D93-IQC80 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 LQFP 100P PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 12 12 86 85 84 83 76 MMC_PS_N0 63 62 MMC_RED_LED 15 MMC_BLUE_LED OUT IN 37 37 37 37 R487 NL/0 5% D VCC3V3_MP_ALT VCC3V3_MP U6 R502 NL/10K LCD Control 0 R514 LCD_A0 38 MCU_SPI0_CS5z OUT MCU_SPI0_CS6z OUT MCU_SPI0_CS5z OUT MCU_SPI0_CS6z SPI_GPIO_INT0 SPI_GPIO_INT0 IN SPI_GPIO_INT1 SPI_GPIO_INT1 IN SPI_GPIO_INT2 SPI_GPIO_INT2 IN SPI_GPIO_INT3 SPI_GPIO_INT3 IN DIP_SW_B0 DIP_SW_B1 DIP_SW_B2 DIP_SW_B3 R488 NL/0 5% AMC MMC 10 MAIN_POWER_START MAIN_POWER_START 11 MAIN_POWER_GOOD OUT IN MAIN_POWER_GOOD 12 SOC_POWER_START OUT SOC_POWER_START 13 SOC_POWER_GOOD IN SOC_POWER_GOOD 97 98 99 VCC3V3_MP_ALT_DET 100 LCD_RSTz 38 OUT 47 61 60 59 58 46 43 42 R489 NL/0 5% UART1 I2C0 13 13 13 13 13 13 37 MCU_SRSTN_R IN MCU_RESET_SWz MCU_SRSTN_R 1 2 3 5 VCC 4 VCC3V3_MP_ALT_DET MCU_RESETz GND C42 TI_SN74AHCT1G08DCKR <Characteristic> C827 0.1uF 16V R503 NL/0 5% MCU SPI0 2.2uF 6.3V R59 VCC3V3_MP 10K SOC Bootmode GPIO Close to U6.1 PCIECLK_MUX_SEL MMC_PS_N0 12 21 U12 37 WAKE OSC0 OSC1 VBAT 50 MCU_WAKEz 55 VBAT 31 MINIJUMPER_2_2.0mm <Characteristic> R83 10K CN2 1 2 3 MCU_U0RX FTDI_MCU_U0RX 1 2 3 4 IN IN CN2(1-2) C A B Y GND VCC G A/B Y 8 7 6 5 IN MCU_PA0_U0RX MCU_UART0_Detect 37 TI_SN74LVC2G157DCUT <Characteristic> PH_3x1V_2.00mm <Characteristic> 10K 51 73 HIB VCC3V3_MP NC_2 NC_1 VDDA GNDA 9 21 45 57 69 82 94 54 33 VCC3V3_MP_AMC VCC3V3_MP_ALT PMEG1020EH 2A VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 LDO VDDC_1 VDDC_2 VCC3V3_MP 71 70 8 20 32 44 56 68 81 93 C73 0.01uF 16V C69 0.01uF 16V C72 0.01uF 16V C414 0.1uF 16V C424 0.1uF 16V C416 0.1uF 16V Buget 150mA R498 R497 R496 R495 C38 2.2uF 6.3V DIP_SW_B0 DIP_SW_B1 DIP_SW_B2 DIP_SW_B3 SW1 ESD104EZ 1 ON 2 3 4 8 7 6 5 R476 R475 R474 R473 100 100 100 100 [Note]1.D3, D5 should be placed on edge of PCB. 2.D4, D6 should be placed inside of PCB. 7 38 88 10K 10K 10K 10K 2 KP-1608EC C415 2.2uF 6.3V R 1 R110 D6 120 5%_1/16W VCC3V3_AUX 14_TI_LM3S2D93-IQC80_0 <Characteristic> 13,18 SOC_RESETSTATZ IN R533 510 1 1% Q18 MMBT3904LT1G B Note:LED Color is RED 2 C362 0.1uF 16V TP9 SMB_SCL_IPMBL SMB_SDA_IPMBL MMC_GA0 12 MMC_GA1 12 MMC_GA2 12 18,31 VCC3V3_MP XOSC0 XOSC1 4 B OUT BI IN IN IN SOC_UART0_TXD_3V3 IN CN2(1-2) C417 0.1uF 16V VCC3V3_MP MMC_GAPU 0 RST 3 PMEG1020EH 2A Close to MCU D11 1 2 From SOC UART0 TX R524 VCC3V3_MP Power for MCU Close to MCU D9 1 2 MCU_U1RX MCU_U1TX VCC3V3_MP NC_3 R546 VCC3V3_MP 66 67 72 65 92 91 90 89 PJ0 PJ1 PJ2 MCUXOSC0 52 53 22 VBAT 32.768KHz <Characteristic> PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 VBAT OSC1 PB0 PB1 PB2/I2C0SCL PB3/I2C0SDA PB4 PB5 PB6 PB7 3 UART0 D 26 27 28 29 30 31 34 35 0.2A D4 2 1 R492 120 5%_1/16W VCC3V3_AUX 3 G 1 2 10K 13 PLLLOCK_LED IN PLLLOCK_LED R504 VCC3V3_MP 510 1 1% MCU_BOOTSELECT PH_2x1V_2.00mm <Characteristic> Q12 MMBT3904LT1G Note:LED Color is GREEN 2 R222 CN9 KP-1608MGC <Characteristic> 0.2A CN9(1-2) D3 1 MINIJUMPER_2_2.0mm <Characteristic> 2R30 56 5% VCC3V3_MP R 3 KPA-1606EC <Characteristic> MMC_RED_LED R31 510 1 1% VCC3V3_MP VCC3V3_MP Q11 MMBT3904LT1G Note:LED Color is RED 2 2012/09/12 ADD 2012/09/26 modify 0.2A VCC3V3_MP CN8(2-3) Power RESET R217 8.2K D5 WAKE R161 8.2K MINIJUMPER_2_2.0mm <Characteristic> 1 MCU_RESET R84 8.2K MMC_BLUE_LED CN8(2-3) SW7-P1 R233 WARM_RESETz 100 SW8-P1 R152 100 FULL_RESETz SW10-P1 R91 100 MCU_RESET_SWz C77 0.01uF 16V 1 2 3 <Characteristic> VCC3V3_MP 510 1 1% Q3 MMBT3904LT1G Note:LED Color is BLUE Designed for TI by ADVANTECH <Characteristic> [Note]RST_MCU1 should be placed inside of PCB Note:PUSH Buttons Color is RED Title Note:PUSH Buttons Color is BLACK MCU LM3S2D93 Size C Date: 5 10 0.2A C54 0.01uF 16V RST_MCU1 PT-004-E1 PH_3x1V_2.00mm <Characteristic> <Characteristic> Note:PUSH Buttons Color is BLACK R494 2 FULL_RESETz MCU_WAKEz 2 PWR DTSA-63R-V 4 3 1 1 C120 0.01uF 16V 1 2 ATT DTSA-63K-V 4 3 2 CN8 A 2 R507 R KPA-1606QBC-D <Characteristic> 3 Attention 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 36 of 43 A 5 4 3 2 MCU JTAG 1 MCU UART VCC3V3_MP D R40 10K 36 MCU_JTAG_TMS BI 36 MCU_JTAG_TDO IN 36 MCU_JTAG_TDI OUT 36 MCU_SRSTN_R OUT 31,36 CN22 R531 VCC3V3_MP R46 0 BSC_JTAG_TMS R51 0 BSC_JTAG_TDO R45 0 BSC_JTAG_TDI R52 0 BSC_JTAG_SRSTN 1 3 5 7 9 0 2 4 6 8 10 R485 R491 R493 R506 R513 27 27 27 27 27 BSC_JTAG_TMS BSC_JTAG_TCK BSC_JTAG_TDO BSC_JTAG_TDI BSC_JTAG_SRSTN 5% 5% 5% 5% 5% MCU_PA1_U0TX 36 MCU_U0RX IN OUT R129 0 MCU_UART_TX R123 0 MCU_UART_RX D VCC3V3_MP R576 4.7K PH_5x2V_S1.27mm <Characteristic> C476 1uF 6.3V R577 4.7K C475 0.1uF 16V U56 10 pos (50 mil pitch) connector C491 C490 0.1uF 16V 0.1uF 16V C492 0.1uF 16V C493 0.1uF 16V RS232_RX 1 2 3 4 5 6 7 8 VCC3V3_MP EN C1+ V+ C1C2+ C2VRIN FORCEOFF VCC GND DOUT FORCEON DIN INVALID ROUT 16 15 14 13 12 11 10 9 RS232_TX MCU_UART_TX R578 4.7K MCU_UART_RX 8 TI_MAX3221ECPWR BSC_JTAG_TCK C40 0.1uF 16V 4 1 2 C828 10pF VCC3V3_MP U4A 6 0 R39 IN MCU_JTAG_TCK 36 TI_SN74LVC2G125DCUR <Characteristic> H1 R232 4.7K MCU NPTH 50V 4 3 2 1 RS232_RX RS232_TX MCU_UART0_Detect OUT C Close to U4.2 VDD 2 GND C136 0.1uF 16V VOUT NC1 NC2 3 1 5 36 C Power Sequencing Q6 4 VCC3V3_AUX MCU_UART0_Detect W_4V_2.54mm <Characteristic> SOC_TEMP1 VCC3V3_MP B7 MICROCHIP_MCP9700AT-E/LT C439 0.1uF Close to SoC C441 4.7uF 6.3V 220_100MHz 0.58A C87 0.1uF 16V C76 4.7uF 6.3V 16V VCC3V3_MP BPCAP B POWER DETECT R243 R244 R560 R563 R566 R203 R206 R226 R234 R248 R249 VCC3V3_MP 18 18 PW_SEQ_SCL PW_SEQ_SDA IN BI R580 R579 R218 R212 Slave I2C Address = 0x65 ( Internal ADDR[7:5] = 0b110 36 36 MAIN_POWER_START SOC_POWER_START 0 5% 0 5% CVDD_PWR_MON 0 UCD_PWR_MON 0 VCC5_MON 3K 1% 1.3K 1% VCC3_AUX_MON VCC2V5_MON 499 1% VCC1V2_MON 0 VCCB0V75_MON 0 VCCA0V75_MON 0 VPP1V8_MON 0 SOC_TEMP1 4.7K 1% 4.7K 1% PMBUS_CLK PMBUS_DAT PMBUS_ALERT R179 PMBUS_CTL R162 0 5% 0 5% 90.9K 1% 90.9K 1% IN IN R564 R192 0 MAIN_POWER_START_R 0 SOC_POWER_START_R MON1 MON2 MON3 MON4 MON5 MON6 MON7 MON8 MON9 MON10 MON11 TCK/GPIO18 TDO/GPIO19 TDI/GPIO20 TMS/GPIO21 TRST GPIO1 GPIO2 GPIO3 GPIO4 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 TI_UCD9090RGZT <Characteristic> 8 9 19 20 44 43 22 23 C86 0.1uF 16V 35 34 33 U13 1 2 38 39 40 41 42 45 46 48 37 C85 0.01uF 16V BPCAP CVDD_PWR_OK IN UCD_PWR_OK IN VCC5 VCC3V3_AUX VCC2V5 VCC1V2 VCCB0V75 VCCA0V75 VPP1V8 VCC3V3_MP V33A 40 41 2K 2K 2K 2K 2K V33D R583 R582 R197 R191 R173 PMBUS_CLK PMBUS_DATA PMBUS_ALERT PMBUS_CNTRL PMBUS_ADDR0 PMBUS_ADDR1 FPWM1/GPIO5 FPWM2/GPIO6 FPWM3/GPIO7 FPWM4/GPIO8 FPWM5/GPIO9 FPWM6/GPIO10 FPWM7/GPIO11 FPWM8/GPIO12 PWM1/GPI1 PWM2/GPI2 PMBUS1 1 2 3 4 5 PMBUS_CLK PMBUS_DAT PMBUS_ALERT PMBUS_CTL OUT BI OUT OUT PMBUS_CLK PMBUS_DAT PMBUS_ALERT PMBUS_CTL 32 40,41 40,41 36,40,41 36 AVSS1 AVSS2 A THERMAL_VIA13 THERMAL_VIA14 THERMAL_VIA15 THERMAL_VIA16 THERMAL_VIA17 THERMAL_VIA18 THERMAL_VIA19 THERMAL_VIA20 THERMAL_VIA21 THERMAL_VIA22 THERMAL_VIA23 THERMAL_VIA24 THERMAL_VIA25 4 5 6 7 18 21 24 25 26 10 11 12 13 14 15 16 17 10K 10K 10K JTAG_TCK JTAG_TDO JTAG_TDI JTAG_TMS TP25 TP21 TP15 TP13 TP14 UCD9244_EN_R Farm1_UCD_EN_R VCC5_EN_R1 VCC3_AUX_EN_R VCC2V5_EN_R VCC1V2_EN_R MAIN_POWER_GOOD_R SOC_POWER_GOOD_R VCC0V75_EN_R POWER ENABLE B R245 R246 R247 R250 R178 R163 R166 R165 R164 R262 R263 0 0 0 0 0 0 0 0 0 0 0 OUT OUT OUT OUT OUT OUT OUT OUT OUT UCD9244_EN 40 Farm1_UCD_EN 41 VCC5_EN 43 VCC3V3_AUX_EN 43 VCC2V5_EN 42 VCC1V2_EN 42 MAIN_POWER_GOOD 36 SOC_POWER_GOOD 36 VCC0V75_EN 42 OUT OUT VID_OEZ AVID_OEZ 21 21 OUT FAN_PWM 12 9090FPWM4 R574 33 9090FPWM6 9090FPWM7 9090FPWM8 3 16V 10K 0.01uF R581 C131 62 63 64 65 66 67 68 69 70 71 72 73 74 5% IN PW_SEQ_RSTz VCC3V3_MP 36 PMBus Address Bins PMBus Address PMBus RESISTANCE ( K ohm ) OPEN 11 10 9 8 7 6 5 4 SHORT -200 154 118 90.9 69.8 53.6 41.2 31.6 -- CN7 9090FPWM4 9090FPWM6 9090FPWM7 9090FPWM8 MAIN_POWER_START_R SOC_POWER_START_R 36 47 PMBus Head THERMAL_PAD THERMAL_VIA1 THERMAL_VIA2 THERMAL_VIA3 THERMAL_VIA4 THERMAL_VIA5 THERMAL_VIA6 THERMAL_VIA7 THERMAL_VIA8 THERMAL_VIA9 THERMAL_VIA10 THERMAL_VIA11 THERMAL_VIA12 DVSS RESET 49 50 51 52 53 54 55 56 57 58 59 60 61 27 28 29 30 31 R176 R175 R174 1 2 3 4 5 6 A PH_6x1V_2.00mm <Characteristic> Designed for TI by ADVANTECH GND_3 PH_5x1V_2.54mm B8 0.5A 120_100MHz Title MCU MISC GND_3 Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 37 of 43 5 4 3 2 1 D D NHD-C12832A1Z-FSB-FBW-3V3 LCD1 VCC3V3_MP VCC3_LCD 2012.10.5 R512 100 3 REF APL431LBAI-TRG 0.12A C409 4.7uF 6.3V VCC3_LCDBK R508 6.98K 1% R2 C412 C408 0.47uF 10V C407 0.47uF 10V C406 0.47uF 10V C405 0.47uF 10V C404 0.47uF 10V 1uF 16V 3.018V =1.24 (1+10k/6.98k)+0.15u*10k LCD-Module_17P <Characteristic> C410 1uF 16V C411 VO = 1.24v(1+R1/R2)+0.15uA*R1 C K R1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 R505 10K Q13 2 A H4 H3 H2 H1 IN IN IN IN IN 1uF 16V MCU_SPI1_CS0z LCD_RSTz 36 LCD_A0 36 MCU_SPI1_CLK MCU_SPI1_MOSI 36 36 36 SPI1 CS0 LCD control C VCC3_LCD VCC3V3_AUX VCC3_LCDBK R509 220 1% B B A A DSPM-8305E Designed for TI by ADVANTECH Title MCU LCD Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 38 of 43 5 4 3 Note : J1 connector close to AMC Interface. Note : USB_D+ USB_DUSB_ID USB_VBUS GNDF1 GNDF2 GNDF3 GNDF4 GNDF5 GNDF6 GNDF7 GNDF8 GNDF9 GNDF10 USB_RXUSB_RX+ USB_TXUSB_TX+ USB_CLKUSB_CLK+ USB_RESREF USB_DRVVBUS PWRA1 PWRB1 PWRA2 PWRB2 GNDG1 GNDG2 GNDG3 GNDG4 GNDG5 GNDG6 GNDG7 GNDG8 GNDG9 GNDG10 PS# SDA MP SCL GNDH1 GNDH2 GNDH3 GNDH4 GNDH5 GNDH6 GNDH7 GNDH8 GNDH9 GNDH10 TCK TDO TDI TMS REF0CLKP REF0CLKN REF1CLKP REF1CLKN G9 H9 G10 H10 C3 D3 C4 D4 HyperLink0_RXFLCLK HyperLink0_RXFLDAT HyperLink0_TXFLCLK HyperLink0_TXFLDAT IN IN OUT OUT HyperLink0_RXPMCLK HyperLink0_RXPMDAT OUT HyperLink0_TXPMCLK OUT IN HyperLink0_TXPMDAT IN C7 HyperLink1_RXFLCLK IN D7 HyperLink1_RXFLDAT IN C8 HyperLink1_TXFLCLK OUT D8 HyperLink1_TXFLDAT OUT C9 HyperLink1_RXPMCLK D9 HyperLink1_RXPMDAT OUT OUT C10 HyperLink1_TXPMCLK IN D10 HyperLink1_TXPMDAT IN C5 D5 C6 D6 HyperLink0_TXP3 HyperLink0_TXN3 HyperLink0_RXP3 HyperLink0_RXN3 14 14 14 14 HyperLink1_TXP0 HyperLink1_TXN0 HyperLink1_RXP0 HyperLink1_RXN0 14 14 14 14 HyperLink1_TXP1 HyperLink1_TXN1 HyperLink1_RXP1 HyperLink1_RXN1 14 14 14 14 HyperLink1_TXP2 HyperLink1_TXN2 HyperLink1_RXP2 HyperLink1_RXN2 14 14 14 14 HyperLink1_TXP3 HyperLink1_TXN3 HyperLink1_RXP3 HyperLink1_RXN3 14 14 14 14 HyperLink0_RXFLCLK HyperLink0_RXFLDAT HyperLink0_TXFLCLK HyperLink0_TXFLDAT GA1 GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 GA10 GB1 GB2 GB3 GB4 GB5 GB6 GB7 GB8 GB9 GB10 14 14 14 14 HyperLink0_RXPMCLK HyperLink0_RXPMDAT HyperLink0_TXPMCLK HyperLink0_TXPMDAT 14 14 14 14 HyperLink1_RXFLCLK HyperLink1_RXFLDAT HyperLink1_TXFLCLK HyperLink1_TXFLDAT 14 14 14 14 HyperLink1_RXPMCLK HyperLink1_RXPMDAT HyperLink1_TXPMCLK HyperLink1_TXPMDAT 14 14 14 14 G3 H3 G4 H4 G5 H5 G6 H6 G7 H7 G8 H8 VCC3V3_AUX A1 B1 A2 B2 VCC12 C1 uRTM_PS#_R D1 SOC_SDA_RTM C2 D2 SOC_SCL_RTM R555 R541 R549 R536 uRTM_PS# R557 4.7K 1% 0 uRTM_PS# uRTM_PS# 13 OUT 0 EXP_SDA2_3V3 12,18,39 BI NL/0 VCC3V3_MP_AMC 0 5% EXP_SCL2_3V3 12,18,39 IN E1 F1 E2 F2 GC1 GC2 GC3 GC4 GC5 GC6 GC7 GC8 GC9 GC10 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 GE1 GE2 GE3 GE4 GE5 GE6 GE7 GE8 GE9 GE10 GF1 GF2 GF3 GF4 GF5 GF6 GF7 GF8 GF9 GF10 GG1 GG2 GG3 GG4 GG5 GG6 GG7 GG8 GG9 GG10 GH1 GH2 GH3 GH4 GH5 GH6 GH7 GH8 GH9 GH10 G1 H1 G2 H2 G9 H9 G10 H10 ATCA_160H <Characteristic> GNDA1 GNDA2 GNDA3 GNDA4 GNDA5 GNDA6 GNDA7 GNDA8 GNDA9 GNDA10 GNDF1 GNDF2 GNDF3 GNDF4 GNDF5 GNDF6 GNDF7 GNDF8 GNDF9 GNDF10 GNDG1 GNDG2 GNDG3 GNDG4 GNDG5 GNDG6 GNDG7 GNDG8 GNDG9 GNDG10 GNDH1 GNDH2 GNDH3 GNDH4 GNDH5 GNDH6 GNDH7 GNDH8 GNDH9 GNDH10 Tx3_3+ Tx3_3Rx3_3+ Rx3_3- Tx0_4+ Tx0_4Rx0_4+ Rx0_4- GNDC1 GNDC2 GNDC3 GNDC4 GNDC5 GNDC6 GNDC7 GNDC8 GNDC9 GNDC10 GNDE1 GNDE2 GNDE3 GNDE4 GNDE5 GNDE6 GNDE7 GNDE8 GNDE9 GNDE10 Tx2_3+ Tx2_3Rx2_3+ Rx2_3- MDIO MDCLK GNDB1 GNDB2 GNDB3 GNDB4 GNDB5 GNDB6 GNDB7 GNDB8 GNDB9 GNDB10 GNDD1 GNDD2 GNDD3 GNDD4 GNDD5 GNDD6 GNDD7 GNDD8 GNDD9 GNDD10 Channel 3 14 14 14 14 SGMII interface HyperLink0_TXP2 HyperLink0_TXN2 HyperLink0_RXP2 HyperLink0_RXN2 Tx1_4+ Tx1_4Rx1_4+ Rx1_4- Channel 4 E9 F9 E10 F10 Tx1_3+ Tx1_3Rx1_3+ Rx1_3- XFI interface E7 F7 E8 F8 14 14 14 14 Tx2_4+ Tx2_4Rx2_4+ Rx2_4Tx3_4+ Tx3_4Rx3_4+ Rx3_4XFIMDIO XFIMDCLK Tx0_5+ Tx0_5Rx0_5+ Rx0_5- Channel 5 RXPMCLK2 RXPMDAT2 TXPMCLK2 TXPMDAT2 E5 F5 E6 F6 HyperLink1_TXP0 IN HyperLink1_TXN0 IN HyperLink1_RXP0 HyperLink1_RXN0 OUT OUT HyperLink1_TXP1 IN HyperLink1_TXN1 IN HyperLink1_RXP1 HyperLink1_RXN1 OUT OUT HyperLink1_TXP2 IN HyperLink1_TXN2 IN HyperLink1_RXP2 HyperLink1_RXN2 OUT OUT HyperLink1_TXP3 IN HyperLink1_TXN3 IN HyperLink1_RXP3 HyperLink1_RXN3 OUT OUT HyperLink0_TXP1 HyperLink0_TXN1 HyperLink0_RXP1 HyperLink0_RXN1 AIF interface RXFCLK2 RXFLDAT2 TXFCLK2 TXFLDAT2 E3 F3 E4 F4 Tx0_3+ Tx0_3Rx0_3+ Rx0_3- Tx1_5+ Tx1_5Rx1_5+ Rx1_5Tx2_5+ Tx2_5Rx2_5+ Rx2_5Tx3_5+ Tx3_5Rx3_5+ Rx3_5Tx0_6+ Tx0_6Rx0_6+ Rx0_6- Channel 6 RXPMCLK1 RXPMDAT1 TXPMCLK1 TXPMDAT1 Channel 3 GNDE1 GNDE2 GNDE3 GNDE4 GNDE5 GNDE6 GNDE7 GNDE8 GNDE9 GNDE10 HyperLink interface RXFLCLK1 RXFLDAT1 TXFLCLK1 TXFLDAT1 A9 B9 A10 B10 14 14 14 14 PCIe interface Channel 1 Channel 2 HyperLink interface Tx3_2+ Tx3_2Rx3_2+ Rx3_2- A7 B7 A8 B8 HyperLink0_TXP0 HyperLink0_TXN0 HyperLink0_RXP0 HyperLink0_RXN0 Tx1_6+ Tx1_6Rx1_6+ Rx1_6Tx2_6+ Tx2_6Rx2_6+ Rx2_6Tx3_6+ Tx3_6Rx3_6+ Rx3_6- Channel 7 GH1 GH2 GH3 GH4 GH5 GH6 GH7 GH8 GH9 GH10 Tx2_2+ Tx2_2Rx2_2+ Rx2_2- A5 B5 A6 B6 HyperLink0_TXP0 IN HyperLink0_TXN0 IN HyperLink0_RXP0 HyperLink0_RXN0 OUT OUT HyperLink0_TXP1 IN HyperLink0_TXN1 IN HyperLink0_RXP1 HyperLink0_RXN1 OUT OUT HyperLink0_TXP2 IN HyperLink0_TXN2 IN HyperLink0_RXP2 HyperLink0_RXN2 OUT OUT HyperLink0_TXP3 IN HyperLink0_TXN3 IN HyperLink0_RXP3 HyperLink0_RXN3 OUT OUT Fabric interface GG1 GG2 GG3 GG4 GG5 GG6 GG7 GG8 GG9 GG10 Tx3_1+ Tx3_1Rx3_1+ Rx3_1- Tx1_2+ Tx1_2Rx1_2+ Rx1_2- Channel 1 B GF1 GF2 GF3 GF4 GF5 GF6 GF7 GF8 GF9 GF10 GNDC1 GNDC2 GNDC3 GNDC4 GNDC5 GNDC6 GNDC7 GNDC8 GNDC9 GNDC10 GNDD1 GNDD2 GNDD3 GNDD4 GNDD5 GNDD6 GNDD7 GNDD8 GNDD9 GNDD10 Tx2_1+ Tx2_1Rx2_1+ Rx2_1- A3 B3 A4 B4 SHIELD GND GE1 GE2 GE3 GE4 GE5 GE6 GE7 GE8 GE9 GE10 GNDB1 GNDB2 GNDB3 GNDB4 GNDB5 GNDB6 GNDB7 GNDB8 GNDB9 GNDB10 SHIELD GND GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 Tx1_1+ Tx1_1Rx1_1+ Rx1_1- Tx0_2+ Tx0_2Rx0_2+ Rx0_2- USB interface GC1 GC2 GC3 GC4 GC5 GC6 GC7 GC8 GC9 GC10 GNDA1 GNDA2 GNDA3 GNDA4 GNDA5 GNDA6 GNDA7 GNDA8 GNDA9 GNDA10 Other interface C HyperLink interface Tx0_1+ Tx0_1Rx0_1+ Rx0_1- GB1 GB2 GB3 GB4 GB5 GB6 GB7 GB8 GB9 GB10 J2 connector close to Key socket. J2 D GA1 GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 GA10 1 A10 B10 C10 D10 E9 F9 E10 F10 G9 H9 G10 H10 D 120-pin Expansion Header A1 B1 A2 B2 A3 B3 A4 B4 the interfaces on the 120-pin header are all 1.8V LVCMOS except for the UART which is 3.3V LVCMOS A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 BI OUT C1 D1 C2 D2 C3 D3 C4 D4 SOC_MDIO_3V3 SOC_MDC_3V3 14,32,33 14,32,33 IN IN OUT OUT SOC_XFI_TX_DP0 SOC_XFI_TX_DN0 SOC_XFI_RX_DP0 SOC_XFI_RX_DN0 15 15 15 15 IN IN OUT OUT SOC_XFI_TX_DP1 SOC_XFI_TX_DN1 SOC_XFI_RX_DP1 SOC_XFI_RX_DN1 15 15 15 15 CN3 H11 I2C C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 IN IN F2 E2 F1 E1 F4 E4 F3 E3 F6 E6 F5 E5 F8 E8 F7 E7 SOC_XFI_MDIO_3V3 SOC_XFIMD_CLK_3V3 15 15 IN IN OUT OUT ZD3_AIF0_TXP ZD3_AIF0_TXN ZD3_AIF0_RXP ZD3_AIF0_RXN 20 20 20 20 IN IN OUT OUT ZD3_AIF1_TXP ZD3_AIF1_TXN ZD3_AIF1_RXP ZD3_AIF1_RXN 20 20 20 20 IN IN OUT OUT ZD3_AIF2_TXP ZD3_AIF2_TXN ZD3_AIF2_RXP ZD3_AIF2_RXN 20 20 20 20 IN IN OUT OUT ZD3_AIF3_TXP ZD3_AIF3_TXN ZD3_AIF3_RXP ZD3_AIF3_RXN 20 20 20 20 EMIF UART SOC_UART(3.3V) 15 15 15,35,39 15 A10 B10 C10 D10 E9 F9 E10 F10 G9 H9 G10 H10 SOC_EMIFCE1Z SOC_EMIFCE2Z SOC_EMIFCE3Z SOC_EMIFBE0Z SOC_EMIFBE1Z SOC_EMIFOEZ SOC_EMIFWEZ BI OUT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI IN IN IN IN IN IN IN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 61 63 65 67 69 19 SOC_EMIFWAIT1 OUT 71 12,18 SOC_TIMO0 IN 73 18 EXP_TIMO0 OUT 75 18,35 SOC_TIMO1 IN 77 18 EXP_TIMO1 OUT 79 R60 10 18 SOC_SSP2_MOSI IN 81 R55 10 18 SOC_SSP2_MISO OUT 83 OUT 18 SOC_SSP2_CS0 85 18 SOC_SSP2_CS1 OUT 87 18 SOC_SSP2_CS2 OUT 89 18 SOC_SSP2_CS3 OUT 91 18 SOC_SSP2_CLK OUT 93 13 EXP_UART1_TXD_3V3 IN 95 13 EXP_UART1_RXD_3V3 OUT 97 OUT 18 SOC_UART1_RTS_3V3 99 18 SOC_UART1_CTS_3V3 IN TSRX_CLK0N 101 15 TSRX_CLK0N IN TSRX_CLK0P 103 15 TSRX_CLK0P IN TSRX_CLK1N 105 15 TSRX_CLK1N IN TSRX_CLK1P 107 15 TSRX_CLK1P IN TSPUSHEVt0_E 109 TSPUSHEVt0_E OUT TSPUSHEVt1_E 111 TSPUSHEVt1_E OUT TSCOMPOUT_E 113 TSCOMPOUT_E IN TSSYNCEVT_E 115 TSSYNCEVT_E IN 117 119 VCC3V3_AUX 19 SOC_EMIFRNW IN ATCA_160H <Characteristic> SOC_EMIFA00 SOC_EMIFA01 SOC_EMIFA02 SOC_EMIFA03 SOC_EMIFA04 SOC_EMIFA05 SOC_EMIFA06 SOC_EMIFA07 SOC_EMIFA08 SOC_EMIFA09 SOC_EMIFA10 SOC_EMIFA11 SOC_EMIFA12 SOC_EMIFA13 SOC_EMIFA14 SOC_EMIFA15 SOC_EMIFA16 SOC_EMIFA17 SOC_EMIFA18 SOC_EMIFA19 SOC_EMIFA20 SOC_EMIFA21 SOC_EMIFA22 SOC_EMIFA23 SOC_GPIO_00 SOC_GPIO_01 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 13,18 13,18 C EMIF VCC5 VCC3V3_AUX BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI SOC_GPIO_02 13,18 SOC_GPIO_03 13,18 SOC_GPIO_04 13,18 SOC_GPIO_05 13,18 SOC_GPIO_06 13,18 SOC_GPIO_07 13,18 SOC_GPIO_08 13,18 SOC_GPIO_09 13,18 SOC_GPIO_10 13,18 SOC_GPIO_11 13,18 SOC_GPIO_12 13,18 SOC_GPIO_13 13,18 SOC_GPIO_14 13,18 SOC_GPIO_15 13,18 SOC_GPIO_16 13,18 TP8 R41 0 MCU_RESETSTATz IN MCU_RESETSTATz 13 R35 0 EXT_PS# OUT EXT_PS# 13 BD_PRESENT 13 OUT OUT BD_ID0 13 OUT BD_ID1 13 OUT BD_ID2 13 IN RSV_CLKN 25 IN RSV_CLKP 25 IN TSPUSHEVt0 35 OUT TSCOMPOUT_E 15,35,39 GPIO B VCC3V3_AUX VCC3V3_AUX H2 NPTH Note: Timer Pins showing which pins go to Timer Inputs on the SOC, since all 4 signals here are labeled as outputs VCC1V8 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT BI BI 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 EXP_TP0 98 EXP_TP1 100EXP_TP2 102 104 106 108 110RSV_CLKN 112RSV_CLKP 114 116 118 120 VCC3V3_AUX SPI G7 H7 G8 H8 EXP_SDA2_3V3 EXP_SCL2_3V3 SOC_EMIFD0 SOC_EMIFD1 SOC_EMIFD2 SOC_EMIFD3 SOC_EMIFD4 SOC_EMIFD5 SOC_EMIFD6 SOC_EMIFD7 SOC_EMIFD8 SOC_EMIFD9 SOC_EMIFD10 SOC_EMIFD11 SOC_EMIFD12 SOC_EMIFD13 SOC_EMIFD14 SOC_EMIFD15 VCC5 EMIF TIMI G5 H5 G6 H6 12,18,39 12,18,39 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 G1 H1 G2 H2 G3 H3 G4 H4 H1 NPTH VCC1V8 EXT_PS# H12 H3 H4 H5 H6 H7 H8 H9 H10 J1 2 R34 4.7K 1% BB_60x2V_S0.5mm <Characteristic> A A DSPM-8305E Designed for TI by ADVANTECH Title mTCA_ZD3/120-pin Expansion Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 39 of 43 5 4 3 2 1 VCC3V3_AUX 7 44 R208 10.2K 1% D C91 1uF 6.3V R209 1.5K 1% Farm0_UCD_EAP1 C453 C458 C79 R140 1000pF 1000pF 1000pF C84 R150 R139 50V Farm0_UCD_TEMP1 5 50V Farm0_UCD_TEMP2 6 50V Farm0_UCD_TEMP3 62 63 VinMon 50 51 52 53 54 55 560pF 50V NL/2K 1% 56 57 560pF 50V NL/2K 1% VCC3V3_AUX R224 R271 1.3K 1% TP31 10 TP33 38 4.7K 1% 40 EAp2 EAn2 CVDD_PWR_OK R172 R151 IN BI OUT IN VCC3V3_AUX 100K 100K 1% 1% CVDD_PWR_OK OUT PMBUS_CLK PMBUS_DAT PMBUS_ALERT UCD9244_EN R159 4.99K 1% R201 EAp3 EAn3 EAp4 EAn4 JTAG_RCK SYNC_IN/JTAG_TDI JTAG_TRST HEAD_UCD_CNTRL_L 1K 10K 1% 1M 1% R267 1% R270 R268 R216 1K VCC3V3_AUX 61 60 24 15 16 27 28 9 1% Addr0 Addr1 Power_Good PMBUS_CLK PMBUS_DATA PMBUS_ALERT PMBUS_CNTRL RESET NL/0 Farm0_FF-1A 0 VCC12 Farm0_PWM-2A Q17 16V C124 NL/0.1uF Farm0_lsenes-2A R231 R808 NL/0 Farm0_FF-2A NL/0 R269 0 Farm0_FF-3A U10 Farm0_lsenes-3A NL/4.99K VCC3V3_AUX 1% Farm0_FF-4A_L Farm0_PWM-4A 100 1% R121 10K 0 Farm0_FF-4A R238 Farm0_lsenes-4A C125 NL/0.1uF 16V 0.01uF 16V R171 Farm0_PWM-1A C145 NL/0.1uF 16V 0.01uF 16V R170 VID3A VID3B VID3C VID3S VID4A/JTAG_TCK VID4B/JTAG_TDO VID4C/JTAG_TMS VID4S DGND1 DGND2 DGND3 AGND1 AGND2 AGND3 PowerPad Thermal_VIA1 Thermal_VIA2 Thermal_VIA3 Thermal_VIA4 Thermal_VIA5 Thermal_VIA6 Thermal_VIA7 Thermal_VIA8 Thermal_VIA9 Thermal_VIA10 Thermal_VIA11 Thermal_VIA12 Thermal_VIA13 Thermal_VIA14 Thermal_VIA15 Thermal_VIA16 Thermal_VIA17 Thermal_VIA18 Thermal_VIA19 Thermal_VIA20 Thermal_VIA21 Thermal_VIA22 Thermal_VIA23 Thermal_VIA24 Thermal_VIA25 38 Farm0_SRE_A1 31 Farm0_FF-1A 29 Farm0_lsenes-1A 33 PWM 41 42 18 12 20 22 29 14 IN IN IN IN DSP_UCD9244_VID1A DSP_UCD9244_VID1B DSP_UCD9244_VID1C DSP_UCD9244_VID1S 21 21 21 21 IN IN IN IN ARM_UCD9244_VID2A ARM_UCD9244_VID2B ARM_UCD9244_VID2C ARM_UCD9244_VID2S 21 21 21 21 30 31 32 33 R575 4.7K 1% VCC3V3_AUX 36 37 39 35 R573 4.7K 1% VCC3V3_AUX R128 0.01uF Farm0_ILIM1 32 8.06K Farm0_RDLY1 39 1% VCC3V3_AUX UA U62 1 2 3 VCC 5 4 Farm0_FF-1A_L GND R806 10 RC 37 10K 22.6K 1% C67 Farm0_FF-1A Farm0_FF-2A 16V R122 R136 Farm0_VGG1 8 26 43 49 48 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 30 1uF 16V C829 TI_SN74LVC1G32DCK <Characteristic> 0.1uF Farm0_AVGG140 16V 41 R550 2 42 1% 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 MICROCHIP_MCP9700AT-E/LT SRE HS_SNS FLT BOOT TI_UCD74120 IMON SW_1 SW_2 SW_3 SW_4 SW_5 SW_6 SRE_MD 27 28 R106 2K 5 R117 10 C49 0.1uF 16V 7 8 9 10 11 12 CSP CSN VGG R135 2.49K 1% 35 Farm0_CSN1 R134 2.49K 1% 3 AGND VGG_DIS CVDD TP11 L4 0.2uH 24A C75 470uF 4V C831 220uF 4V C437 1000uF 2.5V C428 220uF 4V C431 220uF 4V C64 47uF 6.3V C56 47uF 6.3V C422 47uF 6.3V C52 47uF 6.3V 10 ohm GND CVDD R551 1.3K 1% C434 0.1uF 16V R553 931 1% Farm0_VGG1 C429 4.7uF 16V UCD9244 750 ohm EAP1 EAN1 470 pF EAp1 EAn1 470 pF EAp2 EAn2 470 pF EAp2 EAn2 470 pF EAp2 EAn2 750 ohm EAP2 EAN2 10 ohm R77 1K 1% CVDD1 10 ohm GND 36 Farm0_CSP1 AVGG PGND_1 PGND_2 PGND_3 PGND_4 PGND_5 PGND_6 PGND_7 PGND_8 10 ohm GND 10 ohm 750 ohm EAP3 EAN3 R145 0 RDLY Thermal_PAD Thermal_via1 Thermal_via2 Thermal_via3 Thermal_via4 Thermal_via5 Thermal_via6 Thermal_via7 Thermal_via8 Thermal_via9 Thermal_via10 Thermal_via11 Thermal_via12 Thermal_via13 Thermal_via14 Thermal_via15 Thermal_via16 Thermal_via17 Thermal_via18 Thermal_via19 Thermal_via20 Thermal_via21 CVDD SOC DSP Vcore @20A R802 2.2 5%_1/8W BP3 ILIM 10 ohm C60 0.22uF 25V Farm0_SW_Shape1 C814 330pF 50V 10 ohm CVDD1T 10 ohm GND 13 14 15 16 17 18 19 20 750 ohm EAP4 EAN4 Series resistors on EA nets to be placed at the load for proper voltage feedback. 1 2 Farm0_UCD_EAP1 Farm0_UCD_EAN1 R614 R615 10 10 5% 5% CVDD Corresponding "EA" Pins MUST be routed as differential signals and connected next to DSP for specific rails C Series resistors on EA nets to be placed at the load for proper voltage feedback. TI_UCD74120RVF <Characteristic> 5% Farm0_UCD_TEMP1 3 1 5 VOUT NC1 NC2 D VDD NL/4.99K 1% C74 VID1A VID1B VID1C VID1S VDD C438 0.1uF 16V VCC12 0.01uF 16V R195 4 VCC3V3_AUX C48 22uF 16V RD 4.99K 1% Farm0_FF-3A_L Farm0_PWM-3A 100 1% R196 34 23 1 RE R223 R807 Farm0_lsenes-1A Farm0_FF-2A_L Farm0_PWM-2A_L 100 1% C90 VID2A VID2B VID2C VID2S PMBUS Address = 4Eh CVDD_PWR_OK 25 21 2 EAp1 EAn1 Close to UCD9244 37 0.01uF 16V C78 750 1% C81 R147 FLT3A DPWM3A CS3A FLT4A DPWM4A CS4A 560pF 50V NL/2K 1% C82 R148 R137 Farm0_UCD_EAN4 37,41 37,41 36,37,41 37 13 19 3 C80 C99 Temp1/AuxADC1 Temp2/AuxADC2 Temp3/AuxADC3 Temp4/AuxADC4 750 1% Farm0_UCD_EAN3 C FLT2A DPWM2A CS2A BPCAP 750 1% R138 Farm0_UCD_EAP4 4 560pF 50V NL/2K 1% C83 R149 Farm0_UCD_EAN2 Farm0_UCD_EAP3 V33DIO1 V33DIO2 750 1% Farm0_UCD_EAN1 Farm0_UCD_EAP2 V33A Farm0_FF-1A_L Farm0_PWM-1A 100 1% R146 R202 Farm0_UCD_VIN C109 1000pF 50V 47 11 17 59 GND VCC12 V33D 16V NL/0.1uF C119 FLT1A DPWM1A CS1A 26 25 24 23 22 21 46 V33FB VIN_6 VIN_5 VIN_4 VIN_3 VIN_2 VIN_1 45 2 U16 58 B13 C100 2200pF 2.2uF 0.7A 6.3V 34 6 4 1 C460 0.1uF 16V_X7R 16V 2 C454 0.1uF 16V_X7R 16V NC_3 NC_2 NC_1 3 C114 0.1uF 16V_X7R 16V TI_UCD9244RGCR 2 HEAD_UCD_CNTRL_L 1 D7 NL/SBU05U20LPS-7 0.5A CVDD_PWR_OK Note: Should be placed underneath inductor of associated power stage VCC12 Q21 4 VCC3V3_AUX C381 22uF 16V VDD GND C465 0.1uF 16V A Farm0_RDLY239 C371 0.1uF 16V FARM0_VGG2 R459 Farm0_AVGG240 2 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 2 26 25 24 23 22 21 SRE_MD 5 R468 10 C791 0.22uF 25V FARM0_SW_Shape2 7 8 9 10 11 12 ILIM CSP CSN TP59 0.47uH R803 2.2 5%_1/8W BP3 36 FARM0_CSP2 R767 2.49K 1% 35 FARM0_CSN2 R766 2.49K 1% L12 17.5A R761 1.3K 1% C749 0.1uF 50V CVDD C380 1000uF 2.5V VGG 3 4.7uF 16V AVGG Thermal_PAD Thermal_via1 Thermal_via2 Thermal_via3 Thermal_via4 Thermal_via5 Thermal_via6 Thermal_via7 Thermal_via8 Thermal_via9 Thermal_via10 Thermal_via11 Thermal_via12 Thermal_via13 Thermal_via14 Thermal_via15 Thermal_via16 Thermal_via17 Thermal_via18 Thermal_via19 Thermal_via20 Thermal_via21 PGND_1 PGND_2 PGND_3 PGND_4 PGND_5 PGND_6 PGND_7 PGND_8 AGND VGG_DIS C795 470uF 4V C377 47uF 6.3V C373 47uF 6.3V VCC3V3_AUX R82 10K R783 1K 1% R544 R760 931 1% R755 0 C815 330pF 50V 10K C51 C365 47uF 6.3V RDLY FARM0_VGG2 C767 C762 47uF 6.3V C773 47uF 6.3V C779 47uF 6.3V Farm0_PWM-3A 1 Farm0_SRE_A3 2 Farm0_FF-3A 9 Farm0_lsenes-3A 7 0.22uF 16V 4 L5 CVDD1 13 14 15 16 17 18 19 20 0.47uH C97 47uF 6.3V C436 470uF 4V C452 47uF 6.3V CVDD1 C440 0.1uF 16V 1 C110 47uF 6.3V 2 R741 R743 10 10 5% 5% Farm0_UCD_EAP3 Farm0_UCD_EAN3 R294 R293 10 10 5% 5% 10 12 11 PWM_B SRE_B PWM_A SRE_A FLT_B FLT_A IMON_B BST_B BST_A BSW_B BSW_A SWB CVDD1 Corresponding "EA" Pins MUST be routed as differential signals and connected next to DSP for specific rails Series resistors on EA nets to be placed at the load for proper voltage feedback. Farm0_PWM-4A 25 Farm0_SRE_A4 18 Farm0_FF-4A 24 Farm0_lsenes-4A C50 0.22uF Note: Should be placed underneath inductor of associated power stage 10K 10K R81 VCC3V3_AUX R540 16V 23 14 SWA 0.47uH L6 CVDD1T 17.5A PGND_3 PGND_4 NC-PGND_2 C435 470uF 4V 15 17 16 C111 47uF 6.3V C451 47uF 6.3V R567 1K 1% CVDD1T TI_UCD7242RSJT Note: Analog GND to same point Series resistors on EA nets to be placed at the load for proper voltage feedback. TI_UCD74120RVF <Characteristic> 26 20 IMON_A PGND_1 PGND_2 NC-PGND_1 B 16V 27 29 28 19 22uF C423 1uF 25V 0603 CVDD Corresponding "EA" Pins MUST be routed as differential signals and connected next to DSP for specific rails 13 17.5A R198 1K 1% Farm0_UCD_EAP2 Farm0_UCD_EAN2 3 30 32 31 U9 VIN_3 VIN_4 NC-VIN_2 SW_1 SW_2 SW_3 SW_4 SW_5 SW_6 SOC ARM Vcore @6A C425 TMON BOOT TI_UCD74120 IMON 2K C58 1000pF 50V VCC12 16V VIN_1 VIN_2 NC-VIN_1 FLT 28 R469 22uF VGG 8.06K 1% HS_SNS C426 C383 0.1uF 16V BP3 37 SRE 27 5 -205 178 154 133 115 100 86.6 75 64.9 56.2 48.7 42.2 -- OPEN 11 10 9 8 7 6 5 4 3 2 1 0 SHORT 10K Farm0_ILIM2 32 Farm0_UCD_TEMP3 VCC12 VDD 22 PMBus Address PMBus RESISTANCE ( K ohm ) 16V R461 22.6K 1% R768 PMBus Address Bins 30 PWM VGG_DIS C830 R456 1uF 25V 0.01uF MICROCHIP_MCP9700AT-E/LT AGND 29 Farm0_lsenes-2A 33 C775 ARM Fixed Core Supply testmode Farm0_FF-2A 0.95V @5A DSP Fixed Core Supply 6 Farm0_SRE_A2 31 0.95V @5A Farm0_UCD_TEMP2 8 10K 3 1 5 21 R460 VCC3V3_AUX VIN_6 VIN_5 VIN_4 VIN_3 VIN_2 VIN_1 Farm0_PWM-2A 38 B NC_3 NC_2 NC_1 U44 34 6 4 VCC12 VOUT NC1 NC2 C98 47uF 6.3V C92 0.1uF 16V C57 4.7uF 16V Farm0_UCD_EAP4 Farm0_UCD_EAN4 R606 R605 10 10 5% 5% CVDD1T Corresponding "EA" Pins MUST be routed as differential signals and connected next to DSP for specific rails A Series resistors on EA nets to be placed at the load for proper voltage feedback. DSPM-8305E Designed for TI by ADVANTECH Title Smart_Reflex AVS Size Document Number D Date: 5 4 3 2 Rev A104 K2EVM-HK Tuesday, November 04, 2014 1 Sheet 40 of 43 5 4 3 2 1 VCC3V3_AUX 1 U25 C232 1uF 6.3V R376 1.5K 1% C280 C281 C269 R342 R345 4 50V Farm1_UCD_TEMP1 5 50V Farm1_UCD_TEMP2 6 50V Farm1_UCD_TEMP3 62 63 V33DIO1 V33DIO2 VinMon 50 51 560pF 50V 3.3K 1% 52 53 560pF 50V NL/2K 1% C244 R353 54 55 560pF 50V 698 1% 56 57 560pF 50V 2K 1% TP48 10 TP45 38 4.7K 1% 40 VCC3V3_AUX R336 R359 1.3K 1% EAp2 EAn2 R361 R360 75K 1% 75K 1% 61 60 C 24 OUT IN BI OUT IN R346 1% R351 VCC3V3_AUX Farm1_UCD_EN_L 15 16 27 28 1K EAp3 EAn3 EAp4 EAn4 JTAG_RCK SYNC_IN/JTAG_TDI JTAG_TRST Addr0 Addr1 Power_Good PMBUS_CLK PMBUS_DATA PMBUS_ALERT PMBUS_CNTRL 1M 1% R377 10K 1% 9 R682 C652 VID1A VID1B VID1C VID1S VID2A VID2B VID2C VID2S PMBUS Address = 4Eh UCD_PWR_OK 25 21 2 34 23 1 EAp1 EAn1 750 1% C252 R358 PMBUS_CLK PMBUS_DAT PMBUS_ALERT Farm1_UCD_EN R693 C663 FLT3A DPWM3A CS3A Temp1/AuxADC1 Temp2/AuxADC2 Temp3/AuxADC3 Temp4/AuxADC4 Close to UCD9244 37,40 37,40 36,37,40 37 13 19 3 BPCAP 750 1% R356 UCD_PWR_OK R370 RESET Farm1_FF-1A_L Farm1_PWM-1A 100 1% VID3A VID3B VID3C VID3S VID4A/JTAG_TCK VID4B/JTAG_TDO VID4C/JTAG_TMS VID4S DGND1 DGND2 DGND3 AGND1 AGND2 AGND3 PowerPad Thermal_VIA1 Thermal_VIA2 Thermal_VIA3 Thermal_VIA4 Thermal_VIA5 Thermal_VIA6 Thermal_VIA7 Thermal_VIA8 Thermal_VIA9 Thermal_VIA10 Thermal_VIA11 Thermal_VIA12 Thermal_VIA13 Thermal_VIA14 Thermal_VIA15 Thermal_VIA16 Thermal_VIA17 Thermal_VIA18 Thermal_VIA19 Thermal_VIA20 Thermal_VIA21 Thermal_VIA22 Thermal_VIA23 Thermal_VIA24 Thermal_VIA25 R378 Farm1_lsenes-1A NL/4.99K 0 Farm1_FF-1A PLL, 1.8V I/O and SERDES @5A C283 NL/0.1uF 16V 0.01uF 16V R365 FLT2A DPWM2A CS2A FLT4A DPWM4A CS4A C239 R347 R349 Farm1_UCD_EAN4 37 11 17 59 C260 750 1% Farm1_UCD_EAN3 Farm1_UCD_EAP4 FLT1A DPWM1A CS1A V33A 750 1% Farm1_UCD_EAN2 Farm1_UCD_EAP3 1000pF 1000pF 1000pF C236 R343 Farm1_UCD_EAN1 Farm1_UCD_EAP2 V33D R694 Farm1_UCD_VIN Farm1_UCD_EAP1 47 V33FB 1% Farm1_FF-2A_L Farm1_PWM-2A 100 1% R380 Farm1_lsenes-2A 0 Farm1_FF-2A C284 NL/0.1uF 16V 0.01uF 16V D U27 VCC12 4.99K 1% Farm1_FF-3A_L Farm1_PWM-3A 100 1% R354 Farm1_lsenes-3A C251 NL/0.1uF 16V 0.01uF 16V R686 NL/4.99K 1% R683 Farm1_FF-4A_L Farm1_PWM-4A 100 1% C653 0.01uF 16V R687 NL/4.99K 1% 41 42 18 12 R331 R330 R366 R379 4.7K 1% 4.7K 1% 4.7K 1% 4.7K 1% 20 22 29 14 R688 R362 R344 R381 4.7K 1% 4.7K 1% 4.7K 1% 4.7K 1% 30 31 32 33 R341 R340 R334 R339 4.7K 1% 4.7K 1% 4.7K 1% 4.7K 1% 36 37 39 35 R337 R332 R650 R651 4.7K 1% 4.7K 1% 4.7K 1% 4.7K 1% 0 Farm1_FF-3A VCC3V3_AUX R338 Farm1_lsenes-4A R386 10K Farm1_PWM-1A 4 Farm1_SRE_A1 3 PWM VIN UCD74106 SRE TMON 13 10 ohm C306 22uF 16V 10 Farm1_UCD_TEMP1 VCC1V8 Farm1_FF-1A C231 NL/0.1uF 16V 2 Farm1_FLTRST 12 FLT BST FLTRST SW 1 6 C292 0.22uF 25V 10 ohm C723 0.1uF 16V VCC1V5 11 IMON PGND TP50 L9 5 C327 470uF 4V C728 470uF 4V C721 47uF 6.3V C313 47uF 6.3V VDD33 R397 1K 1% 10 ohm GND VGG 10 ohm VCC0V85 R699 22.6K 1% C722 1000pF 50V C293 4.7uF 16V VCC3V3_AUX UCD9244 750 ohm EAP1 EAN1 470 pF EAp1 EAn1 470 pF EAp2 EAn2 470 pF EAp3 EAn3 470 pF EAp4 EAn4 750 ohm EAP2 EAN2 10 ohm VCC1V8 1.5uH 6A 7 VCC3V3_AUX R395 10K 10 ohm GND Farm1_SW_Shape1 Farm1_lsenes-1A 10 ohm GND 0 Farm1_FF-4A AGND 7 44 R375 10.2K 1% C279 1000pF 50V 45 46 VCC12 D 58 BP3 B31 C228 2200pF 2.2uF 0.7A 6.3V 10 ohm GND 750 ohm EAP3 EAN3 750 ohm EAP4 EAN4 TI_UCD74106RGMT <Characteristic> 8 C230 0.1uF 16V_X7R 16V 2 C582 0.1uF 16V_X7R 16V 9 3 C282 0.1uF 16V_X7R 16V C314 1uF 16V Series resistors on EA nets to be placed at the load for proper voltage feedback. 8 26 43 49 48 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Farm1_UCD_EAP1 Farm1_UCD_EAN1 R670 R668 10 10 5% 5% VCC1V8 C Corresponding "EA" Pins MUST be routed as differential signals and connected next to DSP for specific rails Series resistors on EA nets to be placed at the load for proper voltage feedback. TI_UCD9244RGCR Note: Should be placed underneath inductor of associated power stage 4 VCC3V3_AUX VDD 2 GND C688 0.1uF 16V A 22.6K 1% R113 8.06K 1% C62 0.1uF 16V FARM1_VGG2 R537 2 10K 37 Farm1_ILIM2 32 Farm1_RDLY2 39 Farm1_AVGG2 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 26 25 24 23 22 21 SRE_MD SW_1 SW_2 SW_3 SW_4 SW_5 SW_6 5 R116 C63 0.22uF 25V FARM1_SW_Shape2 CSP CSN TP10 0.47uH L3 17.5A R538 1.3K 1% C430 0.1uF 50V VCC1V5 C832 1000uF 2.5V C65 470uF 4V C47 47uF 6.3V C59 47uF 6.3V C53 47uF 6.3V C419 47uF 6.3V C46 47uF 6.3V C68 47uF 6.3V VCC3V3_AUX R329 10K R65 1K 1% R639 36FARM1_CSP2 R115 2.49K 1% 35FARM1_CSN2 R114 2.49K 1% R545 931 1% R547 0 RDLY VGG C432 470uF 4V PGND_1 PGND_2 PGND_3 PGND_4 PGND_5 PGND_6 PGND_7 PGND_8 3 FARM1_VGG2 C420 4.7uF 16V AGND VGG_DIS 1 Farm1_SRE_A3 2 Farm1_FF-3A 9 Farm1_lsenes-3A 10K C221 0.22uF 7 3 16V 4 L8 VDD33 AVGG Thermal_PAD Thermal_via1 Thermal_via2 Thermal_via3 Thermal_via4 Thermal_via5 Thermal_via6 Thermal_via7 Thermal_via8 Thermal_via9 Thermal_via10 Thermal_via11 Thermal_via12 Thermal_via13 Thermal_via14 Thermal_via15 Thermal_via16 Thermal_via17 Thermal_via18 Thermal_via19 Thermal_via20 Thermal_via21 Farm1_PWM-3A 13 14 15 16 17 18 19 20 R328 1K 1% C223 47uF 6.3V 3.3uH 6A C544 470uF 4V C222 47uF 6.3V 13 10 12 11 1 Farm1_UCD_EAP2 Farm1_UCD_EAN2 R757 R756 10 10 5% 5% VCC1V5 Farm1_UCD_EAP3 Farm1_UCD_EAN3 Corresponding "EA" Pins MUST be routed as differential signals and connected next to DSP for specific rails Series resistors on EA nets to be placed at the load for proper voltage feedback. R348 R352 10 10 5% 5% PWM_A SRE_A FLT_B FLT_A IMON_B BST_A BSW_B BSW_A SWB 26 Farm1_PWM-4A 25 Farm1_SRE_A4 18 Farm1_FF-4A Farm1_lsenes-4A 20 IMON_A BST_B 24 C182 0.22uF 10K 10K 14 R612 16V 0.47uH L7 VCC0V85 C503 470uF 4V 15 17 16 C196 47uF 6.3V C509 47uF 6.3V R320 1K 1% VCC0V85 TI_UCD7242RSJT C197 47uF 6.3V C501 0.1uF 16V C226 4.7uF 16V Farm1_UCD_EAP4 Farm1_UCD_EAN4 Note: Analog GND to same point Series resistors on EA nets to be placed at the load for proper voltage feedback. VCC3V3_AUX 17.5A PGND_3 PGND_4 NC-PGND_2 VDD33 Corresponding "EA" Pins MUST be routed as differential signals and connected next to DSP for specific rails R318 23 SWA PGND_1 PGND_2 NC-PGND_1 16V 27 29 28 19 30 32 31 22uF SRE_B C181 1uF 25V 0603 2 B C504 PWM_B SOC USB and SERDES 0.85V @TBD C186 1000pF 50V VCC12 16V U23 DDR3 [email protected] 10 7 8 9 10 11 12 BP3 ILIM 22uF C44 0.1uF 16V 2K VIN_3 VIN_4 NC-VIN_2 BOOT TI_UCD74111RVF <Characteristic> IMON C537 28R85 BP3 30 FLT 27 TMON 33 1uF 25V R93 R105 29 VCC12 VDD HS_SNS 22 C61 Farm1_FF-2A Farm1_lsenes-2A SRE VIN_1 VIN_2 NC-VIN_1 -205 178 154 133 115 100 86.6 75 64.9 56.2 48.7 42.2 -- PWM VGG_DIS OPEN 11 10 9 8 7 6 5 4 3 2 1 0 SHORT 31 AGND PMBus Address PMBus RESISTANCE ( K ohm ) Farm1_SRE_A2 Farm1_UCD_TEMP3 testmode 10K SOC VDD33 @TBD MICROCHIP_MCP9700AT-E/LT 6 R92 Farm1_UCD_TEMP2 8 VCC3V3_AUX 38 3 1 5 21 PMBus Address Bins Farm1_PWM-2A NC_3 NC_2 NC_1 B VIN_6 VIN_5 VIN_4 VIN_3 VIN_2 VIN_1 U8 34 6 4 VCC12 VOUT NC1 NC2 VGG Q15 C43 22uF 16V 5 VCC12 R355 R357 10 10 5% 5% VCC0V85 Corresponding "EA" Pins MUST be routed as differential signals and connected next to DSP for specific rails A Series resistors on EA nets to be placed at the load for proper voltage feedback. DSPM-8305E Designed for TI by ADVANTECH Title Smart_Reflex VDD33/1.8V/1.5V/0.85V Size Document Number D Date: 5 4 3 2 Rev A104 K2EVM-HK Tuesday, November 04, 2014 1 Sheet 41 of 43 5 4 3 2 1 VCC1V2 1.2V @0.38A Q7 TI_TPS73701DRBT 2 6 7 TP38 D 5 C132 0.1uF 16V VCC1V2_EN VOUT FB EN 1 VCC1V2 3 R280 0 5% 4 9 R237 NL/1K 37 NC1 NC2 NC3 C144 10uF 6.3V VIN GND EPAD 8 VCC3V3_AUX C150 10uF 6.3V C158 0.1uF 16V D R1 VCC1V2_EN IN R281 10K 1% R255 10K VCCB0V75 DDR3-1600 DiscreteSDRAM ArrayI R2 R769 VCC1V5 Vout=(R1+R2)/R2*1.204 1.204V = (0+10k)/10k*1.204 C372 10uF 6.3V 1K VCC3V3_AUX 1% C768 0.1uF 16V R770 1K 1% R785 10K C764 0.01uF 16V U60 TI_TPS51200DRCT 1 2 3 VCCB0V75 C778 10uF 6.3V C787 10uF 6.3V 4 C376 10uF 6.3V 5 REFIN 8 VIN 5 VOUT FB 1 VCC2V5_EN 3 R283 39.2K 1% 11 12 13 14 15 16 C783 0.1uF 16V C792 2.2uF 10V C148 10uF 6.3V C C159 0.1uF 16V R1 R284 36.5K 1% VCCA0V75 R2 For DDR3-1600 SO-DIMM Vout=(R1+R2)/R2*1.204 2.50V =(39.2k+36.5k)/36.5k*1.204 R441 VCC1V5 C349 10uF 6.3V 1K VCC3V3_AUX 1% C753 0.1uF 16V R442 1K 1% R750 10K C363 0.01uF 16V 2 3 VCCA0V75 TP58 C833 220uF 4V C339 10uF 6.3V C336 10uF 6.3V 4 C343 10uF 6.3V 5 4 5 7 IN BIAS EN SS C18 560pF 50V PG GND THERMAL_PAD THERMAL_VIA_1 THERMAL_VIA_2 THERMAL_VIA_3 THERMAL_VIA_4 THERMAL_VIA_5 C29 0.1uF 16V IN_1 IN_2 6 11 12 13 14 15 16 C31 10uF 6.3V VIN PGOOD VO GND PGND VOSNS EN REFOUT 10 B VCCA0V75_PGOOD 9 OUT_1 OUT_2 FB 3 TP94 8 7 IN 6 VCC0V75_EN 37,42 VCCA0V75REF C342 0.1uF 16V C344 2.2uF 10V [email protected] Q2 1 2 VLDOIN 11 12 13 14 15 16 0.75V @3A VCC3V3_AUX REFIN EPAD VIA1 VIA2 VIA3 VIA4 VIA5 VPP1V8 C355 0.1uF 16V U38 TI_TPS51200DRCT 1 B SOC_VPPB_EN 37,42 IN R251 10K 13 VCC0V75_EN VCCB0V75REF VCC2V5 4 9 EN 6 REFOUT TP39 2 6 7 R585 NL/1K NC1 NC2 NC3 C133 0.1uF 16V GND EPAD C143 10uF 6.3V IN 2.5V @0.21A Q8 TI_TPS73701DRBT VCC3V3_AUX 7 EN VOSNS TP96 8 GND PGND VCC0V75_PGOOD 9 PGOOD VO 0.75V @3A C 10 VIN VLDOIN EPAD VIA1 VIA2 VIA3 VIA4 VIA5 TP97 VCC2V5 37 C834 220uF 4V C769 0.1uF 16V TP5 9 10 VPP1V8 8 R23 3.57K 1% R1 R481 2.87K 1% R2 C23 10uF 6.3V C392 0.1uF 16V TI_TPS74701DRCT <Characteristic> R28 10K A A Vout=0.8*(1+R1/R2) DSPM-8305E Designed for TI by ADVANTECH 1.79512V =0.8*(1+3.57k/2.87k) Title Power_1.2V/2.5V/0.75V/1.8V Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 42 of 43 5 4 3 2 VCC3V3_AUX 1 VCC3V3_MP_ALT Assume 90% Pe, Iin = ( 3.3V * 2.58A ) / 90% / 12V = 788mA VCC3V3_AUX U2 TI_TPS54620RGY 56.2K 1% 1 2 3 4 5 6 7 B3 2A 120_100MHz VCC12 C386 10uF 16V C385 10uF 16V VCC12 C5 0.1uF 16V RT/CLK GND1 GND2 PVIN1 PVIN2 VIN VSENSE PWRGD BOOT PH2 PH1 EN SS/TR COMP VCC3_AUX_PGOOD 14 13 C22 0.1uF 16V 12 L2 11 VCC3V3_AUX_EN_R 10 9 8 R22 1.69K 1% 15 C6 0.1uF 16V 3.3V_MP@150mA D VCC3V3_AUX TP2 TP60 VCC3V3_MP_ALT 3.3uH 6A C400 100uF 6.3V C413 10uF 6.3V B2 2A 120_100MHz C41 100uF 16V Q10 3 VCC12 R13 31.6K 1% C391 0.01uF 16V C4 0.1uF 16V R1 VIN C8 10uF 16V ADJ/GND R15 3.3V_AUX @2.57A R21 10K 1 [email protected] EPAD D VOUT1 VOUT2 2 4 C390 100uF 6.3V TLV1117-33CDCY 0.8A C14 8200pF 50V R14 10K 1% Rrt=48000xFsw(kHz)^(-0.997)-2 =48000x840^(-0.997)-2 =~56.2 (k ohms) (Over all tolerance is 5% ,DC tolerance is 2.5% ) +++output capacitor Calculation+++ Cout=(2*delta(Iout))/(Fsw*delta(Vout)) Cout=(2*3/(840kHz*0.0825) Cout=~87uF C Vout=0.8 V*(R1/R2+1) 3.3=0.8 V*(10k/3.1k+1) (KIND=0.3) +++Inductor Calculation+++ L = (Vin - Vout)/(Iout * Kind) * (Vout/(Vin * Fsw) L = ((12 - 3.3)/(3A * 0.3) * (3.3 / (12 * 840kHz)) L = 9.67 * 0.33u L = ~3.2 uH R2 CN24 1 2 VCC3V3_AUX_EN_R IN VCC3V3_AUX_EN 37 PH_2x1V_2.00mm <Characteristic> R24 10K UCD Initial Flash CN24(1-2) C MINIJUMPER_2_2.0mm <Characteristic> Reference Capacitor=100uF Reference Inductor 3.3uH VCC5 Assume 90% Pe, Iin = ( 5V * 1.9A ) / 90% / 12V = 880mA *Parameters need to calculate confirm [email protected] VCC3V3_AUX U1 TI_TPS54620RGY VCC12 B 1 2 3 4 5 6 7 120_100MHz 2A C11 10uF 16V VCC12 C10 0.01uF 16V C2 0.1uF 16V 5V @1.9A R11 10K 1% RT/CLK GND1 GND2 PVIN1 PVIN2 VIN VSENSE EPAD B1 82.5K PWRGD BOOT PH2 PH1 EN SS/TR COMP VCC5_PGOOD 14 13 C13 0.1uF 16V 12 L1 11 10 VCC5_EN_R2 R18 0 9 8 15 R8 R17 22.6K 1% C9 1200pF 50V TP3 22uH Reference Capacitor=100uF A VCC5 C399 100uF 6.3V C387 NL/56pF 50V C16 0.01uF 16V IN VCC5_EN C39 NL/22uF 12.5V C403 NL/10uF 16V R7 10K 1% B R1 37 R479 10K R10 1.87K 1% Rrt=48000xFsw(kHz)^(-0.997)-2 =48000x570^(-0.997)-2 =~83.82 (k ohms) (Over all tolerance is 5% ,DC tolerance is 2.5% ) +++output capacitor Calculation+++ Cout=(2*delta(Iout))/(Fsw*delta(Vout)) Cout=(2*2/(570kHz*0.125) Cout=~56.14uF TP4 2.8A R2 Vout=0.8 V*(R1/R2+1) 5=0.8 V*(10k/1.87k+1) +++Inductor Calculation+++ (KIND=0.3) L = (Vin - Vout)/(Iout * Kind) * (Vout/(Vin * Fsw) L = ((12 - 5)/(2.3A * 0.3) * (5 / (12 * 570kHz)) L = 10 * 0.73u L = ~7.3 uH A Reference Inductor 22uH DSPM-8305E Designed for TI by ADVANTECH Title Power_VCC5 / VCC3V3_AUX/MP_ALT Size C Date: 5 4 3 2 Document Number Rev A104 K2EVM-HK Tuesday, November 04, 2014 Sheet 1 43 of 43