5 4 3 2 1 K2E SCHEMATIC MAJOR REVISION HISTORY : I2C ADDRESS TABLE : D D DATE PCB REV. SCH. REV. DESCRIPTION REF DES DESCRIPTION 7 BIT ADDRESS 1.0 1.0 Proto Build 15-NOV-2013 EEPROM1 1MBit I2C EEPROM 0x50 2.0 2.0 Alpha Build 05-MAR-2014 SODIMM SODIMM EEPROM 0x53 2.0 2.01 Alpha ECNs Implemented 24-APR-2014 U4 UCD9090 0x68 C C PCB MECHANICAL DETAILS : PCB LAYER STACK-UP DETAILS : 1. PCB SIZE: 7.11" x 2.89" x 0.063" 3. NUMBER OF LAYERS: 12 4. IMPEDANCE CONTROL: YES B B NOTES, UNLESS OTHERWISE SPECIFIED : 1. 2. 3. 4. A RESISTANCE VALUES ARE IN OHMS. CAPACITANCE VALUES ARE IN MICROFARADS. PARTS NOT INSTALLED ARE INDICATED WITH 'NU'. SIGNAL NET NAMES WITH "#" SUFFIX, ARE ACTIVE LOW SIGNALS. DISCLAIMER: THIS CIRCUIT DESIGN IS PROVIDED AS REFERENCE ONLY, WITHOUT WARRANTY EXPRESSED OR IMPLIED. THE USER IS ENCOURAGED TO PERFORM ALL DUE DILIGENCE WITH RESPECT TO DESIGN AND ANALYSIS. FOR COMMITTED PERFORMANCE AND FUNCTIONALITY, PLEASE REFER TO THE DEVICE DATA MANUAL. 5 Project K2E EVM Copyright (C) 2014 Texas Instruments Incorporated. All rights reserved. Designed for TI by eInfochips Title COVER PAGE Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 4 3 2 Sheet 1 1 of 37 A 5 4 3 2 1 SCHEMATIC PAGE DESCRIPTION : D D 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 C B : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : COVER PAGE TABLE OF CONTENTS SYSTEM BLOCK DIAGRAM PLACEMENT POWER CONSUMPTION POWER SEQUENCE POWER DISTRIBUTION CLOCK DIAGRAM BMC BLOCK DIAGRAM AMC CONNECTOR SPI TO GPIO CONNECTOR SOC SGMII PCIE_MCM SOC XFI USB SOC DDR3 EMU & JTAG PCIe to SATA SOC EMIF NAND MISC SOC CLOCK & Smart-Reflex SOC POWERA SOC POWERB SOC GND CLOCK SOURCE--1 CLOCK SOURCE--2 DDR3 SODIMM AND BMC LCD SGMII Ethernet PHY BMC LM3S2D93 BMC MISC mTCA ZD3/120-pin Exp. POWER SUPPLY--1 POWER SUPPLY-2 XDS200_1 XDS200_2 XDS200_3 XDS200_POWER XDS200_EMULATION REVISION HISTORY C B Project K2E EVM A Designed for TI by eInfochips Title TABLE OF CONTENTS Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 2 of 37 A 5 4 3 2 1 D D C C B B Project K2E EVM A Designed for TI by eInfochips Title SYSTEM BLOCKDIGRAM Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 3 of 37 A 5 4 3 2 1 PLACEMENT D D C C B B Project K2E EVM A Designed for TI by eInfochips Title PLACEMENT Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 4 of 37 A 5 4 3 2 1 POWER CONSUMPTION D D C C B B Project K2E EVM A Designed for TI by eInfochips Title POWER CONSUMPTION Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 5 of 37 A 5 4 3 2 1 D D C C B B Project K2E EVM A Designed for TI by eInfochips Title POWER SEQUENCING Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 6 of 37 A 5 4 3 2 1 D D C C B B Project K2E EVM A Designed for TI by eInfochips Title POWER DISTRIBUTION Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 7 of 37 A 5 4 3 2 1 D D C C B B Project K2E EVM A Designed for TI by eInfochips Title CLOCK DIAGRAM Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 8 of 37 A 5 4 3 2 1 D D C C B B Project K2E EVM A Designed for TI by eInfochips Title BMC BLOCK DIAGRAM Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 9 of 37 A 5 4 3 2 1 AMC EDGE CONNECTOR VCC3V3_AUX D AMC_JTAG_TDI AMC_JTAG_TDO AMC_JTAG_TMS AMC_JTAG_TCK VCC12_AMC R595 R591 R581 R578 10K 10K 10K 10K AMC_JTAG_RST# R585 10K D AMC1 GF-AMC-B VCC3V3_MP_AMC MMC_PS_N1 [27] MMC_GA0 OUT Management Power [12] [12] AMC0_SGMII2_TX_DP AMC0_SGMII2_TX_DN [12] [12] AMC0_SGMII2_RX_DP AMC0_SGMII2_RX_DN [12] [12] AMC1_SGMII3_TX_DP AMC1_SGMII3_TX_DN [12] [12] AMC1_SGMII3_RX_DP AMC1_SGMII3_RX_DN SGMII[3:2] [27] [27] MMC_GA1 MMC_GA2 IN IN OUT OUT OUT IN IN OUT OUT OUT C SATA [16] [16] AMC2_SATA0_TX_DP AMC2_SATA0_TX_DN [16] [16] AMC2_SATA0_RX_DP AMC2_SATA0_RX_DN IN IN OUT OUT C238 C233 100nF 25V 100nF 25V C228 C226 100nF 25V 100nF 25V VCC3V3_MP R656 10K [27] [12] [12] PCIe--0 MMC_ENABLE_N AMC4_PCIe0_TX0P AMC4_PCIe0_TX0N [12] [12] AMC4_PCIe0_RX0P AMC4_PCIe0_RX0N [12] [12] AMC5_PCIe0_TX1P AMC5_PCIe0_TX1N [12] [12] AMC5_PCIe0_RX1P AMC5_PCIe0_RX1N [27] SMB_SCL_IPMBL OUT IN IN OUT OUT C187 C176 100nF 25V 100nF 25V C165 C162 100nF 25V 100nF 25V IN IN OUT OUT OUT LAYOUT NOTE: These caps to be implemented adjacent to AMC connector WITHOUT additional vias. B [27] TCLKB also serves as a 25.0MHz LVDS clock to CLK3 PRI_REF for the HyperLink synchronizat i on. SMB_SDA_IPMBL BI TCLKA_TSIP0CLKA_P TCLKA_TSIP0CLKA_N OUT OUT [24] [24] TCLKB_25MHz_P TCLKB_25MHz_N OUT OUT [19] [19] PCIe_REF_CLK_P PCIe_REF_CLK_N OUT OUT MMC_PS_N1 D11 [12] [12] [27] MMC_PS_N0 B340A-13-F MMC_PS_N0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 GND_1 PWR_12V_1 PS1 MP GA0 RSRVD6 GND_2 RSRVD8 PWR_12V_2 GND_3 Tx0+ Tx0GND_4 Rx0+ Rx0GND_5 GA1 PWR_12V_3 GND_6 Tx1+ Tx1GND_7 Rx1+ Rx1GND_8 GA2 PWR_12V_4 GND_9 Tx2+ Tx2GND_10 Rx2+ Rx2GND_11 Tx3+ Tx3GND_12 Rx3+ Rx3GND_13 ENABLE PWR_12V_5 GND_14 Tx4+ Tx4GND_15 Rx4+ Rx4GND_16 Tx5+ Tx5GND_17 Rx5+ Rx5GND_18 SCL_L PWR_12V_6 GND_19 Tx6+ Tx6GND_20 Rx6+ Rx6GND_21 Tx7+ Tx7GND_22 Rx7+ Rx7GND_23 SDA_L PWR_12V_7 GND_24 TCLKA+ TCLKAGND_25 TCLKB+ TCLKBGND_26 FCLKA+ FCLKAGND_27 PS0 PWR_12V_8 GND_28 GND_56 TDI TDO TRST TMS TCK GND_55 Tx20+ Tx20GND_54 Rx20+ Rx20GND_53 Tx19+ Tx19GND_52 Rx19+ Rx19GND_51 Tx18+ Tx18GND_50 Rx18+ Rx18GND_49 Tx17+ Tx17GND_48 Rx17+ Rx17GND_47 TCLKD+ TCLKDGND_46 TCLKC+ TCLKCGND_45 Tx15+ Tx15GND_44 Rx15+ Rx15GND_43 Tx14+ Tx14GND_42 Rx14+ Rx14GND_41 Tx13+ Tx13GND_40 Rx13+ Rx13GND_39 Tx12+ Tx12GND_38 Rx12+ Rx12GND_37 Tx11+ Tx11GND_36 Rx11+ Rx11GND_35 Tx10+ Tx10GND_34 Rx10+ Rx10GND_33 Tx9+ Tx9GND_32 Rx9+ Rx9GND_31 Tx8+ Tx8GND_30 Rx8+ Rx8GND_29 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 AMC_JTAG_TDI AMC_JTAG_TDO AMC_JTAG_RST# AMC_JTAG_TMS AMC_JTAG_TCK DSP_SCL_AMC DSP_SDA_AMC OUT IN OUT OUT OUT R574 R573 0E 0E IN BI AMC_JTAG_TDI AMC_JTAG_TDO AMC_JTAG_TRST# AMC_JTAG_TMS AMC_JTAG_TCK EXP_SCL2_3V3 EXP_SDA2_3V3 [15] [15] [15] [15] [15] JTAG [18,29] [18,29] Expansion I2C C OUT OUT TCLKC_FS_P TCLKC_FS_N BI IN R621 100E C872 [12] [12] PHY_MDIO_2V5 AMC_MDC_2V5 [12,26,29] [12] LAYOUT NOTE: Place these components close to AMC EDGE connector 10pF50V R492 R490 0E 0E R489 R485 0E 0E OUT OUT TSIP0_RX1_TX0 TSIP0_TX1_RX0 [12] [12] OUT OUT TSIP0_RX0_TX1 TSIP0_TX0_RX1 [12] [12] TSIP B OUT Project K2E EVM A Designed for TI by eInfochips Title AMC INTERFACE Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 10 of 37 A 5 4 3 2 1 VCC1V8 VCC3V3_MP SPI LEVEL SHIFT 3V3 to 1V8 C311 VCC3V3_MP C314 VCC1V8 100nF 25V C331 C330 100nF 25V 100nF 25V OUT OUT OUT IN IN OUT IN SPI_GPIO_INT0 SPI_GPIO_INT1 SPI_GPIO_INT2 MCU_SPI0_CLK MCU_SPI0_MOSI MCU_SPI0_MISO SPI_GPIO_RESET 20 18 17 16 15 14 13 12 B1 B2 B3 B4 B5 B6 B7 B8 2 19 VCCA SPI_GPIO_INT0 SPI_GPIO_INT1 SPI_GPIO_INT2 MCU_SPI0_CLK MCU_SPI0_MOSI MCU_SPI0_MISO SPI_GPIO_RESET MCU_SPI0_CS3z MCU_SPI0_CS4z MCU_SPI0_CS5z IN IN IN MCU_SPI0_CS3z_1V8 MCU_SPI0_CS4z_1V8 MCU_SPI0_CS5z_1V8 D TXS0108EPWR 10 1 3 4 5 6 7 8 9 OE A1 A2 A3 A4 A5 A6 A7 A8 R317 4.7K 1% SPI_GPIO_INT0_1V8 SPI_GPIO_INT1_1V8 SPI_GPIO_INT2_1V8 MCU_SPI0_CLK_1V8 MCU_SPI0_MOSI_1V8 MCU_SPI0_MISO_1V8 SPI_GPIO_RESET_1V8 SPI TO GPIO 1.8V Level U39 MCP23S17T-E/SS [19] [27] [15] [30] 11 [27] [27] [27] [23,24,27] [23,24,27] [23,24,27] [27] MCU_SPI0_CS3z MCU_SPI0_CS4z MCU_SPI0_CS5z 100nF 25V VCC1V8 VCCB U41 GND D [27] [27] [27] 1 2 3 4 5 6 7 8 U38 SN74AVC4T245PWR 16 VCCA VCCB 15 1DIR 1OE 14 2DIR 2OE 13 1A1 1B1 12 1A2 1B2 11 2A1 2B1 10 2A2 2B2 9 GND1 GND2 SOC_RSV008 PLLLOCK_LED SOC_GPIO_16 SOC_VPPB_EN IN OUT OUT OUT PLLLOCK_LED DEBUG_LED_BUFF_OE SPI_GPIO_INT1_1V8 SPI_GPIO_RESET_1V8 SPI TO GPIO 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0 1.8V Level GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS CS SCK SI SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OUT OUT IN IN IN IN NAND_WPz [17] EEPROM_WPz [18] BD_PRESENT [29] BD_ID0 [29] BD_ID1 [29] BD_ID2 [29] VCC1V8 MCU_SPI0_CS4z_1V8 MCU_SPI0_CLK_1V8 MCU_SPI0_MOSI_1V8 MCU_SPI0_MISO_1V8 U44 MCP23S17T-E/SS [15] [15] [15] [15] [15] [15] [15] [15] SOC_GPIO_07 SOC_GPIO_06 SOC_GPIO_05 SOC_GPIO_04 SOC_GPIO_03 SOC_GPIO_02 SOC_GPIO_01 SOC_GPIO_00 OUT OUT OUT OUT OUT OUT OUT OUT SPI_GPIO_INT0_1V8 C SPI_GPIO_RESET_1V8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS CS SCK SI SO OUT OUT OUT OUT OUT OUT OUT OUT SOC_GPIO_08 SOC_GPIO_09 SOC_GPIO_10 SOC_GPIO_11 SOC_GPIO_12 SOC_GPIO_13 SOC_GPIO_14 SOC_GPIO_15 [15] [15] [15] [15] [15] [15] [15] [15] SPI TO GPIO 3.3V Level VCC1V8 MCU_SPI0_CS3z_1V8 MCU_SPI0_CLK_1V8 MCU_SPI0_MOSI_1V8 MCU_SPI0_MISO_1V8 C U8 MCP23S17T-E/SS [29] uRTM_PS# [23] CLK1_REF_SEL [24] CLK2_REF_SEL SOC_I2C1_DIMM_EN SOC_I2C1_PMBUS_EN [29] EXT_PS# [29] MCU_RESETSTATz [26] PHY1_INT# [27] SPI_GPIO_INT3 [18] [18] IN OUT OUT OUT OUT IN OUT R94 0E IN SPI_GPIO_INT3 OUT SPI_GPIO_RESET 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS CS SCK SI SO 1 REFCLK1_PD# [23] OUT 2 REFCLK2_PD# [24] OUT 3 4 PLL_LOCK1 [23] IN 5 PLL_LOCK2 [24] IN 6 7 CLK_RSTz [23,24] OUT 8 R93 0E PHY2_INT# [26] IN 9 VCC3V3_MP 10 MCU_SPI0_CS6z 11 MCU_SPI0_CS6z IN MCU_SPI0_CLK 12 MCU_SPI0_MOSI 13 MCU_SPI0_MISO 14 [27] CDCM-620X Control SPI TO GPIO VCC1V8 1.8V Level SPI_GPIO_INT2_1V8 B VCC1V8 OUT OUT OUT BOOTMODE14 BOOTMODE15 BOOTMODE_ON VCC3V3_AUX C320 C321 [15] [15] [15] C875 100nF 25V SOC_RESETFULLZ [19] SOC_RESETZ [19] SOC_PORZ [19] VCC1V8 [19,27] MCU_SPI0_CS5z_1V8 MCU_SPI0_CLK_1V8 MCU_SPI0_MOSI_1V8 MCU_SPI0_MISO_1V8 DSP_PMBUS_EN R628 IN 0E SOC_GPIO_11 C876 100nF 25V U79 TXS0102DCUR 3 6 5 4 2 VccA VccB OE A1 A2 GND B1 B2 100nF 25V U40 [29] [29] [29] [29] [29] [29] [29] [29] 7 8 1 IN PMBUS_ALERT [27,28,31] EXP_GPIO_08 EXP_GPIO_09 EXP_GPIO_10 EXP_GPIO_11 EXP_GPIO_12 EXP_GPIO_13 EXP_GPIO_14 EXP_GPIO_15 BI BI BI BI BI BI BI BI 20 18 17 16 15 14 13 12 B1 B2 B3 B4 B5 B6 B7 B8 100nF 25V 2 OUT OUT OUT 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS CS SCK SI SO VCCA GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0 TXS0108EPWR 10 1 3 4 5 6 7 8 9 OE A1 A2 A3 A4 A5 A6 A7 A8 EXP_GPIO_EN SOC_GPIO_08 SOC_GPIO_09 SOC_GPIO_10 SOC_GPIO_11 SOC_GPIO_12 SOC_GPIO_13 SOC_GPIO_14 SOC_GPIO_15 B 11 SPI_GPIO_RESET_1V8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCCB IN IN OUT OUT OUT IN OUT GND [19,27] SOC_RESETSTATZ [19] SOC_BOOTCOMPLETE [19] SOC_LRESETNMIENZ [19] SOC_LRESETZ [19] SOC_NMIZ [19] SOC_HOUT [19] SOC_PACLKSEL VCC1V8 PMBUS ALERT BUFFER U43 MCP23S17T-E/SS VCC1V8 VCC1V8 VCC1V8 C317 VCC1V8 C316 100nF 25V C333 U37 TXB0102DCUR 7 VccB VccA OE C334 20 18 17 16 15 14 13 12 B1 B2 B3 B4 B5 B6 B7 B8 2 19 VCCA BI BI BI BI BI BI BI BI VCCB EXP_GPIO_00 EXP_GPIO_01 EXP_GPIO_02 EXP_GPIO_03 EXP_GPIO_04 EXP_GPIO_05 EXP_GPIO_06 EXP_GPIO_07 OE A1 A2 A3 A4 A5 A6 A7 A8 10 1 3 4 5 6 7 8 9 IN SOC_GPIO_00 SOC_GPIO_01 SOC_GPIO_02 SOC_GPIO_03 SOC_GPIO_04 SOC_GPIO_05 SOC_GPIO_06 SOC_GPIO_07 EXP_GPIO_EN U48 SN74LVC125APWR VCC SOC_GPIO_12 2 SOC_GPIO_13 5 SOC_GPIO_14 9 SOC_GPIO_15 12 R327 BI 8 1 B1 B2 4.7K 1% 4.7K 1% 1 4 10 13 1A 1Y 2A 2Y 3A 3Y 4A 4Y OE1# OE2# OE3# OE4# GND EXP_GPIO_EN 4 A1 A2 GND 5 4 2 SOC_GPIO_16 100nF 25V 14 3 6 8 11 7 Project OUT SOC_DEBUG_LED1 [18] OUT SOC_DEBUG_LED2 [18] OUT SOC_DEBUG_LED3 [18] OUT SOC_DEBUG_LED4 [18] K2E EVM 3 Designed for TI by eInfochips Title SPI to GPIO Converter Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 EXP_GPIO_16 EXP_GPIO_EN C15 [27] DEBUG_LED_BUFF_OE R330 [29] VCC1V8 TXS0108EPWR 11 A [29] [29] [29] [29] [29] [29] [29] [29] 100nF 25V GND 100nF 25V U46 100nF 25V 3 6 2 Sheet 1 11 of 37 A 5 4 [10] [10] [10] [10] [29] [29] [29] [29] [29] [29] [29] [29] [26] SOC_SGMII0_TXN [26] SOC_SGMII0_TXP [26] SOC_SGMII1_TXN [26] SOC_SGMII1_TXP AMC0_SGMII2_TX_DN AMC0_SGMII2_TX_DP AMC1_SGMII3_TX_DN AMC1_SGMII3_TX_DP uTCA_SGMII4_TX_DN uTCA_SGMII4_TX_DP uTCA_SGMII5_TX_DN uTCA_SGMII5_TX_DP uTCA_SGMII6_TX_DN uTCA_SGMII6_TX_DP uTCA_SGMII7_TX_DN uTCA_SGMII7_TX_DP 1 R629 NU 33E K2E C161 C163 C159 C160 C157 C158 C146 C153 C143 C145 C136 C141 C133 C135 C127 C132 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V SOC_SGMII0_RXN_R AN29 SOC_SGMII0_RXP_R AN30 SOC_SGMII1_RXN_R AM28 SOC_SGMII1_RXP_R AM29 AMC0_SGMII2_RX_DN_R AN26 AMC0_SGMII2_RX_DP_R AN27 AMC1_SGMII3_RX_DN_RAM25 AMC1_SGMII3_RX_DP_R AM26 uTCA_SGMII4_RX_DN_R AN23 uTCA_SGMII4_RX_DP_R AN24 uTCA_SGMII5_RX_DN_R AM22 uTCA_SGMII5_RX_DP_R AM23 uTCA_SGMII6_RX_DN_R AN20 uTCA_SGMII6_RX_DP_R AN21 uTCA_SGMII7_RX_DN_R AM19 uTCA_SGMII7_RX_DP_R AM20 AL30 AL29 AK29 AK28 AL27 AL26 AK26 AK25 AL24 AL23 AK23 AK22 AL21 AL20 AK20 AK19 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT SGMII0RXN0 SGMII0RXP0 SGMII0RXN1 SGMII0RXP1 SGMII0RXN2 SGMII0RXP2 SGMII0RXN3 SGMII0RXP3 SGMII0RXN4 SGMII0RXP4 SGMII0RXN5 SGMII0RXP5 SGMII0RXN6 SGMII0RXP6 SGMII0RXN7 SGMII0RXP7 SGMII0TXN0 SGMII0TXP0 SGMII0TXN1 SGMII0TXP1 SGMII0TXN2 SGMII0TXP2 SGMII0TXN3 SGMII0TXP3 SGMII0TXN4 SGMII0TXP4 SGMII0TXN5 SGMII0TXP5 SGMII0TXN6 SGMII0TXP6 SGMII0TXN7 SGMII0TXP7 MDCLK0 MDIO0 AH6 R630 33E AH5 R631 0E OUT SOC_XFIMDC OUT SOC_SGMII_MDC BI R632 NU 0E BI [13] [13] SOC_SGMII_MDIO SOC_XFI_MDIO [13] [13] LAYOUT NOTE: VCC1V8 VCC2V5 Place R629 and R630 close to SoC VCC1V8 VCC2V5 C417 100nF 25V SGMII00REFRES SGMII01REFRES AJ27 AJ22 R479 R472 3K 3K 1% 1% SOC_SGMII_MDIO SOC_XFI_MDIO 5 4 2 VCC1V8 R627 R626 4.7K 1% 4.7K 1% C423 100nF 25V U58 TXS0102DCUR 3 100K 6 R390 VccA VccB OE A1 A2 GND B1 B2 C893 100nF 25V SOC_SGMII_MDC R655 0E 21 20 19 18 17 16 15 14 R642 0E 22 7 SOC_XFIMDC 8 R407 1 R412 0E 0E BI BI PHY_MDIO_2V5 [10,26,29] EXP_XFI_MDIO_2V5 [29] VCC2V5 R624 R625 1K 1K C894 100nF 25V U80 SN74LVC8T245RHLR 24 23 VCCB VCCB VCCA B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 A4 A5 A6 A7 A8 OE# 1% 1% GND3 GND2 GND1 D [10] [10] [10] [10] [29] [29] [29] [29] [29] [29] [29] [29] SOC_SGMII0_RXN SOC_SGMII0_RXP SOC_SGMII1_RXN SOC_SGMII1_RXP AMC0_SGMII2_RX_DN AMC0_SGMII2_RX_DP AMC1_SGMII3_RX_DN AMC1_SGMII3_RX_DP uTCA_SGMII4_RX_DN uTCA_SGMII4_RX_DP uTCA_SGMII5_RX_DN uTCA_SGMII5_RX_DP uTCA_SGMII6_RX_DN uTCA_SGMII6_RX_DP uTCA_SGMII7_RX_DN uTCA_SGMII7_RX_DP 2 TPAD DIR 1 3 4 5 6 7 8 9 10 R634 R635 R636 R637 R638 R639 R640 25 2R654 33E 33E 33E 33E 33E 33E 33E D 1% 1% 1% 1% 1% 1% 1% OUT OUT OUT OUT TP96 OUT TP97 AMC_MDC_2V5 RTM_MDC_2V5 PHY1_MDC_2V5 PHY2_MDC_2V5 EXP_XFI_MDC_2V5 [10] [29] [26] [26] [29] 0E 13 12 11 SGMII X8 [26] [26] [26] [26] 3 U23G K2E_Processor 7 of 26 TSIP VCC3V3_AUX C633 C635 100nF 25V 100nF 25V [10] [10] AMC5_PCIe0_TX1N AMC5_PCIe0_TX1P [10] [10] AMC4_PCIe0_RX0N AMC4_PCIe0_RX0P [10] [10] [16] [16] AMC5_PCIe0_RX1N AMC5_PCIe0_RX1P PCIe1_TX1N PCIe1_TX1P OUT OUT OUT OUT C662 C649 100nF 25V AMC4_PCIe0_TX0N_R AL18 100nF 25V AMC4_PCIe0_TX0P_R AL17 C634 C610 100nF 25V AMC5_PCIe0_TX1N_R AK17 100nF 25V AMC5_PCIe0_TX1P_R AK16 AN17 AN18 IN IN AM16 AM17 IN IN OUT OUT [16] [16] PCIe1_TX2N PCIe1_TX2P [16] [16] PCIe1_RX1N PCIe1_RX1P IN IN [16] [16] PCIe1_RX2N PCIe1_RX2P IN IN OUT OUT C607 C599 100nF 25V 100nF 25V PCIe1_TX1N_R PCIe1_TX1P_R AL15 AL14 C585 C573 100nF 25V 100nF 25V PCIe1_TX2N_R PCIe1_TX2P_R AK14 AK13 AN14 AN15 AM13 AM14 PCIE0TXN0 PCIE0TXP0 PCIE0TXN1 PCIE0TXP1 [10] [10] [10] [10] PCIe--0 TSIP0_RX0_TX1 TSIP0_RX1_TX0 TSIP0_TX0_RX1 TSIP0_TX1_RX0 13 12 11 10 9 IN IN OUT OUT B1 B2 B3 B4 NC2 PCIE0RXN0 PCIE0RXP0 C VCC1V8 OE A1 A2 A3 A4 NC1 8 2 3 4 5 6 R475 K2E 4.7K 1% AM31 AL33 TSIP0TR0 TSIP0TR1 AL32 AM32 PCIE0RXN1 PCIE0RXP1 PCIE1TXN0 PCIE1TXP0 PCIE1TXN1 PCIE1TXP1 U23F K2E_Processor TXS0104EPWR 7 AMC4_PCIe0_TX0N AMC4_PCIe0_TX0P 1 U68 K2E [10] [10] 14 U23O K2E_Processor VCCA C VCC1V8 VCCB LAYOUT NOTE: Place ALL PCIe DC-blocking caps close to the TX pins GND PCIE[1:0] X2 TSIP0_CLKA TSIP0_CLKB AK31 AK33 TSIP0_FSA TSIP0_FSB AJ31 AK32 TSIP0TX0 TSIP0TX1 TSIP0CLKA TSIP0CLKB TSIP0FSA TSIP0FSB PCIe--1 6 of 26 PCIE1RXN0 PCIE1RXP0 PCIE1RXN1 PCIE1RXP1 PCIE0REFRES PCIE1REFRES AG14 AJ10 R460 R449 3K 3K VCC1V8 1% 1% VCC3V3_AUX 16 of 26 C730 C731 100nF 25V B [10] TCLKA_TSIP0CLKA_P IN [10] TCLKA_TSIP0CLKA_N IN R486 VCC3V3_AUX 100E R482 HyperLink X4 [29] [29] [29] [29] [29] [29] [29] [29] A [29] [29] [29] [29] HyperLink0_TXN0 HyperLink0_TXP0 HyperLink0_TXN1 HyperLink0_TXP1 HyperLink0_TXN2 HyperLink0_TXP2 HyperLink0_TXN3 HyperLink0_TXP3 HyperLink0_TXFLCLK HyperLink0_TXFLDAT HyperLink0_TXPMCLK HyperLink0_TXPMDAT OUT OUT OUT OUT OUT OUT OUT OUT IN IN OUT OUT CLK nCLK OE Q0 Q1 GND 7 R487 6 R483 22E 22E 22E 22E TSIP0_FSA TSIP0_FSB 5 VCC1V8 C746 C747 K2E IN IN IN IN IN IN IN IN OUT OUT IN IN 2 3 4.7K 1% 4 B TSIP0_CLKA TSIP0_CLKB VCC3V3_AUX U23R K2E_Processor [29] HyperLink0_RXN0 [29] HyperLink0_RXP0 [29] HyperLink0_RXN1 [29] HyperLink0_RXP1 [29] HyperLink0_RXN2 [29] HyperLink0_RXP2 [29] HyperLink0_RXN3 [29] HyperLink0_RXP3 [29] HyperLink0_RXFLCLK [29] HyperLink0_RXFLDAT [29] HyperLink0_RXPMCLK [29] HyperLink0_RXPMDAT U70 100nF ICS83026BGI-01LF 25V 1 8 VDD VDDO C111 C115 C109 C110 C107 C108 C101 C104 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF R416 25V 25V 25V 25V 25V 25V 25V 25V 22E R414 HyperLink0_RXN0_C AN8 HyperLink0_RXP0_C AN9 HyperLink0_RXN1_C AM7 HyperLink0_RXP1_C AM8 HyperLink0_RXN2_C AN5 HyperLink0_RXP2_C AN6 HyperLink0_RXN3_C AM4 HyperLink0_RXP3_C AM5 HyperLink0_RXFLCLK_R AJ3 HyperLink0_RXFLDAT AE3 HyperLink0_RXPMCLK AE1 HyperLink0_RXPMDAT AD1 HyperLink0_TXN0 AL9 HyperLink0_TXP0 AL8 HyperLink0_TXN1 AK8 HyperLink0_TXP1 AK7 HyperLink0_TXN2 AL6 HyperLink0_TXP2 AL5 HyperLink0_TXN3 AK5 HyperLink0_TXP3 AK4 HyperLink0_TXFLCLK AC6 HyperLink0_TXFLDAT AH4 22EHyperLink0_TXPMCLK_RAB6 HyperLink0_TXPMDAT AF5 R434 1% 3K AJ5 100nF 25V HYPLNK0RXN0 HYPLNK0RXP0 HYPLNK0RXN1 HYPLNK0RXP1 HYPLNK0RXN2 HYPLNK0RXP2 HYPLNK0RXN3 HYPLNK0RXP3 HYPLNK0RXFLCLK HYPLNK0RXFLDAT HYPLNK0RXPMCLK HYPLNK0RXPMDAT [10] TCLKC_FS_P [10] TCLKC_FS_N IN R501 HYPLNK0TXN0 HYPLNK0TXP0 HYPLNK0TXN1 HYPLNK0TXP1 HYPLNK0TXN2 HYPLNK0TXP2 HYPLNK0TXN3 HYPLNK0TXP3 HYPLNK0TXFLCLK HYPLNK0TXFLDAT HYPLNK0TXPMCLK HYPLNK0TXPMDAT 100E IN VCC3V3_AUX R513 100nF U72 25V ICS83026BGI-01LF 1 8 VDD VDDO 2 3 4.7K 1% 4 Project K2E EVM CLK nCLK OE Q0 Q1 GND 7 R499 6 R495 5 Designed for TI by eInfochips Title SERDES INTERFACE Size C HYPLNK0REFRES Document Number Rev 16_00175_02 2.01 19 of 26 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 12 of 37 A 5 4 3 2 1 XFI X2 U23T K2E_Processor K2E D [29] [29] [29] [29] SOC_XFI_RX_DN0 SOC_XFI_RX_DP0 SOC_XFI_RX_DN1 SOC_XFI_RX_DP1 IN IN IN IN [29] [29] [29] [29] SOC_XFI_TX_DN0 SOC_XFI_TX_DP0 SOC_XFI_TX_DN1 SOC_XFI_TX_DP1 OUT OUT OUT OUT C119 C123 C116 C118 100nF 100nF 100nF 100nF SOC_XFI_RX_DN0_R SOC_XFI_RX_DP0_R SOC_XFI_RX_DN1_R SOC_XFI_RX_DP1_R 25V 25V 25V 25V AN11 AN12 AM10 AM11 XFIRXN0 XFIRXP0 XFIRXN1 XFIRXP1 AL12 AL11 AK11 AK10 TSPUSHEVT0 TSPUSHEVT1 TSSYNCEVT TSCOMPOUT XFITXN0 XFITXP0 XFITXN1 XFITXP1 TSREFCLKN TSREFCLKP TSRXCLKOUT0N TSRXCLKOUT0P [12] SOC_SGMII_MDC [12] OUT SOC_SGMII_MDC 33E NU R643 SOC_XFIMDC SOC_XFIMDC OUT SOC_XFI_MDIO SOC_XFI_MDIO BI [12] [12] SOC_SGMII_MDIO BI 33E 0E TSRXCLKOUT1N TSRXCLKOUT1P AF6 AE7 R644 R645 AG3 AL1 IN IN AE5 AF4 OUT OUT AK1 TSREFCLKN_R AK2 TSREFCLKP_R C83 C84 100nF 25V 100nF 25V AJ2 AJ1 AH1 AG2 R446 R441 3K 3K 1% AG10 1% AH7 USB0_RXN USB0_RXP USB0_TXN USB0_TXP USB_CLKN_R C462 100nF 25V USB_CLKP_R C463 100nF 25V I N USB_CLKN I N USB_CLKP 100uF 10V USB0VBUS U29 TPS22913BYZVR A1 A2 VOUT VIN VDD_USB_0 100nF 6.3V 100nF 6.3V ACM2012-900-2P-TL 2 3 L7 USB0_RXN USB0_RXP 1 1uF 16V GND USB0_TXN C186 100nF 25V USB0_TXP C189 100nF 25V 4 5 6 7 8 9 ACM2012-900-2P-TL 2 3 L9 USB_VBUS_EN B2 ON USB_RXN_R USB_RXP_R C174 C164 100nF B1 25V J7 USB3.0_9H 1 2 3 4 USBDN_R USBDP_R 4 1 4 H1 H2 ED6 NC6 8 7 C529 FB20 120_100MHz 0.5A C528 1 USB0DP 5 10 USB_SHIELD VCC1V8 USB -- 1 (HOST or Device) B USB1DRVVBUS R223 0E C537 100nF 6.3V 100nF 6.3V C453 10uF 25V U27 SN74LVC1G07DBVR VCC 1 5 2 3 4 P11 USB1_0V85 VDD33 VBUS1 R172 R424 0E R8 T9 1K USB1_ID W6 VBUS1_R V4 USB1DRVVBUS AC1 USB1DVDD33 USB1DP USB1DM USB1VP USB1VPTX USB1RX0M USB1RX0P USB1TX0M USB1TX0P USB1ID0 USB1VBUS USB1DRVVBUS 100nF 25V 1uF 16V 5 4 IN 1 2 3 OUT GND FLT EN C142 100nF 25V C144 100uF 10V FB22 120_100MHz USB1_RXN USB1_RXP USB1_TXN USB1_TXP VCC0V85 R436 200E V5 USB1RESREF VDDUSB1_1 VDDUSB1_2 25 of 26 R12 T11 VDD_USB_1 C538 FB30 120_100MHz 0.5A C546 100nF 6.3V 100nF 6.3V ACM2012-900-2P-TL 2 3 USB1_TXN 1 4 L5 ACM2012-900-2P-TL 3 C129 100nF 25V 2 USB1_TXP C126 100nF 25V 1 USB1DP USB1_RXN USB1_RXP USB1DN_R USB1DP_R USB1_ID USB1_TXN_R USB1_TXP_R 4 L4 ACM2012-900-2P-TL 2 3 1 L3 1 2 3 4 5 6 7 8 9 10 USB1_RXN_R USB1_RXP_R 4 SH1 SH2 SH3 SH4 SH5 SH6 100nF 25V B1 GND ON B2 5 10 1uF 16V I N USB_VBUS_EN [28] USB_SHIELD 13 2 12 3 11 4 14 1 ED1 NC1 ED2 NC2 ED3 NC3 9 6 NCG GND ED4 NC4 C150 ED5 NC5 8 7 C151 ED6 NC6 U28 TPS22913BYZVR A2 VOUT VIN C441 C512 C523 C517 10nF 10V 4.7uF 10V 100nF 6.3V 10nF 10V 4.7uF 10V MICRO AB VBUS DUSB 2.0 D+ ID GND MicA_SSTXMicA_SSTX+ GND_DRAIN MicA_SSRXMicA_SSRX+ SH1 SH2 SH3 SH4 SH5 SH6 FB23 120_100MHz USB0_VDD3V3 C505 C504 C454 100nF 6.3V 10nF 10V 4.7uF 10V Project K2E EVM <Characteristic> 4 3 VDD33 FB25 120_100MHz VCC0V85 USB0_0V85 C524 C499 C469 100nF 6.3V 10nF 10V 4.7uF 10V Designed for TI by eInfochips Title SoC_XFI_USB Size U24 SP3012-06UTG VDD33 FB27 120_100MHz C498 C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 B USB1_VDD3V3 100nF 6.3V USB_SHIELD USB1VBUS A1 3A C513 A VBUS1 VCC0V85 USB1_0V85 J6 KMMXAB10SMT4SB30 USB1DP USB1DN USB1DN N1 P1 R2 P2 FB6 USB_SHIELD USB 3.0 MICRO AB CONN. R4 P4 U30 SP3012-06UTG U26 TPS2065CDBVR K2E USB1VPH NCG GND USB1VBUS C154 R222 4.7K 1% U23W K2E_Processor R10 PTH_1 PTH_2 30_100MHz R220 NU 0E USB1_VDD3V3 StdA_SSRXStdA_SSRX+ GND_DRAIN StdA_SSTXStdA_SSTX+ VCC5V GND C539 USB3.0 TypeA VBUS DUSB 2.0 D+ GND USB_SHIELD VCC5V C156 VDD33 C ACM2012-900-2P-TL 2 3 L8 USB0DN [23] [23] VCC0V85 U10 V11 C205 100nF 25V C214 USB 3.0 TYPE-- A CONN. VBUS0 VDDUSB0_1 VDDUSB0_2 EN R246 NU 0E USB0RESREF 25 of 26 4 1 2 3 14 1 T1 U1 U2 V2 T4 U4 USBCLKM USBCLKP Y6 USB0DP USB0DN OUT GND FLT ED1 NC1 USB0RX0M USB0RX0P USB0TX0M USB0TX0P USB0ID0 USB0VBUS USB0DRVVBUS V3 W3 IN 13 2 200E U32 TPS2065CDBVR 5 ED2 NC2 R438 1uF 16V GND USB0DP USB0DM USB0VP USB0VPTX 1K USB0_ID W4 0E VBUS0_R W5 USB0DRVVBUSAB1 USB0VBUS C777 R245 4.7K 1% 100nF 25V 12 3 R431 R426 0E U31 SN74LVC1G07DBVR VCC 1 5 2 3 4 ED3 NC3 VBUS0 USB0DRVVBUS R533 USB0DVDD33 U8 V9 [29] [29] 11 4 USB0_0V85 C TSRX_CLK1N TSRX_CLK1P VCC5V C194 K2E USB0VPH Y11 OUT OUT D ED4 NC4 W10 [29] [29] VCC5V U23U K2E_Processor USB0_VDD3V3 TSRX_CLK0N TSRX_CLK0P 24 of 26 USB -- 0 (HOST) C443 10uF 25V OUT OUT 9 6 100nF 6.3V [24] [24] ED5 NC5 C557 TSREFCLKN TSREFCLKP IN IN XFIREFRES0 XFIREFRES1 VCC1V8 100nF 6.3V [29] [29] SOC_SGMII_MDIO0E NU R646 Place R643 and R644 close to SoC C545 [29] [29] TSSYNCEVT_E TSCOMPOUT_E XFIMDCLK XFIMDIO LAYOUT NOTE: VDD33 TSPUSHEVT0_E TSPUSHEVT1_E 2 Sheet 1 13 of 37 A 5 4 3 2 1 SOC DDR3 D D U23K K2E_Processor K2E [25] [25] [25] SOC_DDR3A_EDQSN_[0..7] SOC_DDR3A_EDQSN_8 SOC_DDR3A_EDQSP_[0..7] [25] OUT OUT OUT SOC_DDR3A_EDQSP_8 [25] [25] [25] SOC_DDR3A_EBA_0 SOC_DDR3A_EBA_1 SOC_DDR3A_EBA_2 OUT SOC_DDR3A_EDQSN_0 SOC_DDR3A_EDQSN_1 SOC_DDR3A_EDQSN_2 SOC_DDR3A_EDQSN_3 SOC_DDR3A_EDQSN_4 SOC_DDR3A_EDQSN_5 SOC_DDR3A_EDQSN_6 SOC_DDR3A_EDQSN_7 SOC_DDR3A_EDQSN_8 SOC_DDR3A_EDQSP_0 SOC_DDR3A_EDQSP_1 SOC_DDR3A_EDQSP_2 SOC_DDR3A_EDQSP_3 SOC_DDR3A_EDQSP_4 SOC_DDR3A_EDQSP_5 SOC_DDR3A_EDQSP_6 SOC_DDR3A_EDQSP_7 SOC_DDR3A_EDQSP_8 C2 B4 A7 B10 B24 B27 B30 D33 A22 C1 A4 B7 A10 A24 A27 A30 C33 B22 D13 C13 B18 OUT OUT OUT DDRDQS0N DDRDQS1N DDRDQS2N DDRDQS3N DDRDQS4N DDRDQS5N DDRDQS6N DDRDQS7N DDRDQS8N DDRDQS0P DDRDQS1P DDRDQS2P DDRDQS3P DDRDQS4P DDRDQS5P DDRDQS6P DDRDQS7P DDRDQS8P DDRA00 DDRA01 DDRA02 DDRA03 DDRA04 DDRA05 DDRA06 DDRA07 DDRA08 DDRA09 DDRA10 DDRA11 DDRA12 DDRA13 DDRA14 DDRA15 D15 C15 B16 C16 D16 E16 A17 E17 A18 B17 A13 D18 E18 E12 C18 E19 SOC_DDR3A_EA0 SOC_DDR3A_EA1 SOC_DDR3A_EA2 SOC_DDR3A_EA3 SOC_DDR3A_EA4 SOC_DDR3A_EA5 SOC_DDR3A_EA6 SOC_DDR3A_EA7 SOC_DDR3A_EA8 SOC_DDR3A_EA9 SOC_DDR3A_EA10 SOC_DDR3A_EA11 SOC_DDR3A_EA12 SOC_DDR3A_EA13 SOC_DDR3A_EA14 SOC_DDR3A_EA15 OUT SOC_DDR3A_EA[0..15] [25] DDRBA0 DDRBA1 DDRBA2 11 65 C C U23J K2E_Processor K2E [25] [25] SOC_DDR3A_EODT_0 SOC_DDR3A_EODT_1 OUT OUT [25] [25] SOC_DDR3A_ECAS# SOC_DDR3A_ERAS# OUT OUT [25] [25] SOC_DDR3A_EWE# OUT SOC_DDR3A_EMRESETN OUT [25] [25] SOC_DDR3A_ECKN_0 SOC_DDR3A_ECKP_0 OUT OUT [25] [25] SOC_DDR3A_ECKN_1 SOC_DDR3A_ECKP_1 OUT OUT D12 E11 B12 B13 E13 R469 1% 4.7K D20 B14 B15 A15 A16 DDRODT0 DDRODT1 DDRCASz DDRRASz DDRCKE0 DDRCKE1 DDRWEz DDRCE0z DDRCE1z C20 A19 A12 C12 OUT OUT SOC_DDR3A_ECKE_0 SOC_DDR3A_ECKE_1 [25] [25] OUT OUT SOC_DDR3A_ECS_0# SOC_DDR3A_ECS_1# [25] [25] DDRRESETz DDRCLKOUTN0 DDRCLKOUTP0 DDRCLKOUTN1 DDRCLKOUTP1 DDRRZQ0 DDRRZQ1 DDRRZQ2 E15 G12 G18 R465 R454 R467 240E 240E 240E 1% 1% 1% 10 of 26 U23L K2E_Processor SOC_DDR3A_EDQ0 SOC_DDR3A_EDQ1 SOC_DDR3A_EDQ2 SOC_DDR3A_EDQ3 SOC_DDR3A_EDQ4 SOC_DDR3A_EDQ5 SOC_DDR3A_EDQ6 SOC_DDR3A_EDQ7 SOC_DDR3A_EDQ8 SOC_DDR3A_EDQ9 SOC_DDR3A_EDQ10 SOC_DDR3A_EDQ11 SOC_DDR3A_EDQ12 SOC_DDR3A_EDQ13 SOC_DDR3A_EDQ14 SOC_DDR3A_EDQ15 SOC_DDR3A_EDQ16 SOC_DDR3A_EDQ17 SOC_DDR3A_EDQ18 SOC_DDR3A_EDQ19 SOC_DDR3A_EDQ20 SOC_DDR3A_EDQ21 SOC_DDR3A_EDQ22 SOC_DDR3A_EDQ23 SOC_DDR3A_EDQ24 SOC_DDR3A_EDQ25 SOC_DDR3A_EDQ26 SOC_DDR3A_EDQ27 SOC_DDR3A_EDQ28 SOC_DDR3A_EDQ29 SOC_DDR3A_EDQ30 SOC_DDR3A_EDQ31 SOC_DDR3A_EDQ32 SOC_DDR3A_EDQ33 SOC_DDR3A_EDQ34 SOC_DDR3A_EDQ35 SOC_DDR3A_EDQ36 SOC_DDR3A_EDQ37 SOC_DDR3A_EDQ38 SOC_DDR3A_EDQ39 B E2 D1 F2 E1 F1 D2 F3 B2 A5 A6 B5 E5 C4 D4 E4 B3 D6 E6 E7 B6 C6 C8 A8 B8 E10 B11 A11 C10 D10 B9 E9 A9 B23 E23 D24 C24 E24 E25 B25 A25 DDRD00 DDRD01 DDRD02 DDRD03 DDRD04 DDRD05 DDRD06 DDRD07 DDRD08 DDRD09 DDRD10 DDRD11 DDRD12 DDRD13 DDRD14 DDRD15 DDRD16 DDRD17 DDRD18 DDRD19 DDRD20 DDRD21 DDRD22 DDRD23 DDRD24 DDRD25 DDRD26 DDRD27 DDRD28 DDRD29 DDRD30 DDRD31 DDRD32 DDRD33 DDRD34 DDRD35 DDRD36 DDRD37 DDRD38 DDRD39 K2E DDRD40 DDRD41 DDRD42 DDRD43 DDRD44 DDRD45 DDRD46 DDRD47 DDRD48 DDRD49 DDRD50 DDRD51 DDRD52 DDRD53 DDRD54 DDRD55 DDRD56 DDRD57 DDRD58 DDRD59 DDRD60 DDRD61 DDRD62 DDRD63 DDRDQM0 DDRDQM1 DDRDQM2 DDRDQM3 DDRDQM4 DDRDQM5 DDRDQM6 DDRDQM7 DDRDQM8 DDRCB00 DDRCB01 DDRCB02 DDRCB03 DDRCB04 DDRCB05 DDRCB06 DDRCB07 A E28 D28 C28 E27 B28 A26 B26 C26 A29 A28 B31 E29 B29 C30 E30 D30 F31 F33 F32 E32 E33 C32 D32 B32 SOC_DDR3A_EDQ40 SOC_DDR3A_EDQ41 SOC_DDR3A_EDQ42 SOC_DDR3A_EDQ43 SOC_DDR3A_EDQ44 SOC_DDR3A_EDQ45 SOC_DDR3A_EDQ46 SOC_DDR3A_EDQ47 SOC_DDR3A_EDQ48 SOC_DDR3A_EDQ49 SOC_DDR3A_EDQ50 SOC_DDR3A_EDQ51 SOC_DDR3A_EDQ52 SOC_DDR3A_EDQ53 SOC_DDR3A_EDQ54 SOC_DDR3A_EDQ55 SOC_DDR3A_EDQ56 SOC_DDR3A_EDQ57 SOC_DDR3A_EDQ58 SOC_DDR3A_EDQ59 SOC_DDR3A_EDQ60 SOC_DDR3A_EDQ61 SOC_DDR3A_EDQ62 SOC_DDR3A_EDQ63 A3 E3 D8 E8 E26 D26 E31 A31 B20 A23 D22 E22 E21 C22 B21 A20 A21 OUT OUT OUT OUT OUT OUT OUT OUT OUT SOC_DDR3A_ECC0 SOC_DDR3A_ECC1 SOC_DDR3A_ECC2 SOC_DDR3A_ECC3 SOC_DDR3A_ECC4 SOC_DDR3A_ECC5 SOC_DDR3A_ECC6 SOC_DDR3A_ECC7 B SOC_DDR3A_EDM_0 SOC_DDR3A_EDM_1 SOC_DDR3A_EDM_2 SOC_DDR3A_EDM_3 SOC_DDR3A_EDM_4 SOC_DDR3A_EDM_5 SOC_DDR3A_EDM_6 SOC_DDR3A_EDM_7 SOC_DDR3A_EDM_8 BI [25] [25] [25] [25] [25] [25] [25] [25] [25] SOC_DDR3A_ECC[0..7] [25] Project K2E EVM Designed for TI by eInfochips Title 12 of 26 SoC DDR3 Size C SOC_DDR3A_EDQ[0..63] 5 4 [25] Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 3 2 Sheet 1 14 of 37 A 5 4 3 2 1 SOC GPIO U23I K2E_Processor MIPI 60 K2E V30 AA29 Y29 V33 V32 W30 W32 V31 W31 W33 AB29 Y30 Y32 AA30 Y33 Y31 AA33 AB32 AB33 AB31 AC29 AC33 AD29 AC31 AC32 AB30 AC30 AD32 AD33 AD31 AE33 AD30 GPIO00/LENDIAN GPIO01/BOOTMODE0 GPIO02/BOOTMODE1 GPIO03/BOOTMODE2 GPIO04/BOOTMODE3 GPIO05/BOOTMODE4 GPIO06/BOOTMODE5 GPIO07/BOOTMODE6 GPIO08/BOOTMODE7 GPIO09/BOOTMODE8 GPIO10/BOOTMODE9 GPIO11/BOOTMODE10 GPIO12/BOOTMODE11 GPIO13/BOOTMODE12 GPIO14/MAINPLLODSEL GPIO15/ARM_BENDIAN GPIO16/BOOTMODE13 GPIO17/BOOTMODE14/EMU19 GPIO18/BOOTMODE15/EMU20 GPIO19/EMU21 GPIO20/EMU22 GPIO21/EMU23 GPIO22/EMU24 GPIO23/EMU25 GPIO24/EMU26 GPIO25/EMU27 GPIO26/EMU28 GPIO27/EMU29 GPIO28/EMU30 GPIO29/EMU31 GPIO30/EMU32 GPIO31/EMU33 D BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI SOC_EMU_19 SOC_EMU_20 SOC_EMU_21 SOC_EMU_22 SOC_EMU_23 SOC_EMU_24 SOC_EMU_25 SOC_EMU_26 SOC_EMU_27 SOC_EMU_28 SOC_EMU_29 SOC_EMU_30 SOC_EMU_31 SOC_EMU_32 SOC_EMU_33 SOC_GPIO_00 SOC_GPIO_01 SOC_GPIO_02 SOC_GPIO_03 SOC_GPIO_04 SOC_GPIO_05 SOC_GPIO_06 SOC_GPIO_07 SOC_GPIO_08 SOC_GPIO_09 SOC_GPIO_10 SOC_GPIO_11 SOC_GPIO_12 SOC_GPIO_13 SOC_GPIO_14 SOC_GPIO_15 SOC_GPIO_16 [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] EMU1 BB_60V_S0.5mm VCC1V8 H1 R45 R52 R65 EMU_TCK EMU_TDI SOC_EMU_02 SOC_TVD EMU_TCK_R EMU_TDI_R EMU_RTCK 100E 10E 10E R145 10E R68 SOC_EMU_03 SOC_EMU_00 SOC_EMU_01 SOC_EMU_04 SOC_EMU_05 SOC_EMU_06 SOC_EMU_07 SOC_EMU_08 SOC_EMU_09 SOC_EMU_10 SOC_EMU_11 SOC_EMU_12 SOC_EMU_13 SOC_EMU_14 SOC_EMU_15 SOC_EMU_16 SOC_EMU_17 SOC_EMU_18 SOC_EMU_19 SOC_EMU_20 9 of 26 VCC1V8 R132 R131 R128 R146 R401 R143 R130 R129 R403 R402 R147 R393 R392 R144 R391 R400 R399 R394 R227 R224 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E SOC_EMU_02_R 0E TDIS SOC_EMU_03_R SOC_EMU_00_R SOC_EMU_01_R SOC_EMU_04_R SOC_EMU_05_R SOC_EMU_06_R SOC_EMU_07_R SOC_EMU_08_R SOC_EMU_09_R SOC_EMU_10_R SOC_EMU_11_R SOC_EMU_12_R SOC_EMU_13_R SOC_EMU_14_R SOC_EMU_15_R SOC_EMU_16_R SOC_EMU_17_R SOC_EMU_18_R SOC_EMU_19_R SOC_EMU_20_R 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 AMC JTAG 3V3 to 1V8 CONVERTER VCC3V3_AUX 4.7K 1% SOC_EMU_01 R127 4.7K 1% EMU_TMS EMU_TDO R37 R51 OUT R64 NU 4.7K 1% VCC1V8 EMU_TRST#_R R67 EMU_TRST# 0E SOC_TVD SOC_EMU_21_R SOC_EMU_22_R SOC_EMU_23_R SOC_EMU_24_R SOC_EMU_25_R SOC_EMU_26_R SOC_EMU_27_R SOC_EMU_28_R SOC_EMU_29_R SOC_EMU_30_R SOC_EMU_31_R SOC_EMU_32_R SOC_EMU_33_R 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E 10E R516 R502 R225 R520 R517 R228 R503 R504 R229 R226 R518 R519 R505 TRGRSTZ [27,36] 4.7K 1% R66 4.7K 1% EMU_TDO R44 4.7K 1% EMU_TCK R53 4.7K 1% R46 100E C18 50V 8.2pF EMU_TRST# R341 D 4.7K 1% SOC_EMU_21 SOC_EMU_22 SOC_EMU_23 SOC_EMU_24 SOC_EMU_25 SOC_EMU_26 SOC_EMU_27 SOC_EMU_28 SOC_EMU_29 SOC_EMU_30 SOC_EMU_31 SOC_EMU_32 SOC_EMU_33 VCC3V3_AUX R100 4.7K 1% EMU_DET VCC1V8 H3 H4 H5 H6 R109 10E 10E R31 EMU_TDI H2 VCC1V8 SOC_EMU_00 EMU_TMS_R EMU_TDO_R EMU_TMS C374 VCC1V8 VCC3V3_AUX U57 SN74LVC244APWR VCC C C357 100nF 25V 100nF 25V B1 B2 B3 B4 NC2 1 VCCA 13 12 11 10 9 IN IN IN OUT VCCB AMC_JTAG_TDI AMC_JTAG_TMS AMC_JTAG_TCK AMC_JTAG_TDO C31 VCC1V8 TXS0104EPWR OE A1 A2 A3 A4 NC1 100nF 25V LAYOUT NOTE: 8 2 3 4 5 6 R378 4.7K 1% AMC_JTAG_TDI_1V8 AMC_JTAG_TMS_1V8 AMC_JTAG_TCK_1V8 AMC_JTAG_TDO_1V8 - Place termination resistors for EMU_TCK, TDI, TMS as close to MIPI-60 header as possible - Place termination resistors for SOC_TDO and SOC_EMU* signals as close to the SoC as possible U12 SN74LVC1G04DCKR 5 EMU_DET 2 1 EMU_TDI EMU_TMS EMU_TRST# SOC_TDO EMU_TCK 2 4 6 8 11 13 15 17 R385 R386 1 19 VCC A NC Y GND EMU_ENABLE 4 3 4.7K 1% 4.7K 1% 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 1OE 2OE GND 20 C SOC_TDI 18 SOC_TMS 16 SOC_TRST# 14 EMU_TDO 12 9 R389 22E SOC_TCK 7 R387 22E EMU_RTCK 5 3 10 7 [10] [10] [10] [10] GND U11 14 C353 100nF 25V LAYOUT NOTE: VCC3V3_AUX Termination resistors for SOC_TCK and EMU_RTCK should be placed as close to U57 as possible XDS_USB_VBUS C348 VCC1V8 100nF 25V U56 SN74LVC1T45DCKR 6 1 VCCB VCCA 4 3 AMC_JTAG_TRST#_1V8 A 2 5 B DIR GND C361 100nF 25V [10] AMC_JTAG_TRST# I N [36] JTAG_SELECT 4.7K 1% XDS200_TDI XDS200_TMS BI [36] XDS200_TRST# BI AMC_JTAG_TMS_1V8 5 XDS200_TMS 6 AMC_JTAG_TRST#_1V8 11 XDS200_TRST# 10 B XDS200_TDO AMC_JTAG_TDO_1V8 14 XDS200_TDO 13 BI S E# IA0 IA1 YA VCC1V8 16 EMU_ENABLE 15 C368 IB0 IB1 YB IC0 IC1 YC ID0 ID1 YD EMU_TDI 4 U55 SN74LVC2G125DCUR 8 VCC 7 EMU_TMS 9 EMU_TRST# 12 EMU_TDO [11] 8 [11] BOOTMODE14 IN [11] BOOTMODE15 IN 2 5 1 7 BOOTMODE_ON I N VCC1V8 R357 17 GND [36] 1 AMC_JTAG_TDI_1V8 2 XDS200_TDI 3 BI [36] VCC 1A 1Y 2A 2Y 1OE# 2OE# 100nF 25V 6SOC_EMU_19_R B 3SOC_EMU_20_R GND R344 100nF 25V U7 TS3L110 EPAD C355 4 R343 4.7K 1% VCC3V3_AUX 4.7K 1% U23N K2E_Processor K2E LAYOUT NOTE: AG32 SOC_TMS SOC_TDI SOC_TDO SOC_TCK C351 U49 TS3L110 100nF 25V VCC JTAG_SELECT [36] XDS200_TCK BI [36] XDS_RTCK BI [36] XDS200_EMU0 BI TP91 [36] SOC_TRST# XDS200_EMU1 1 AMC_JTAG_TCK_1V8 2 XDS200_TCK 3 BI XDS_RTCK 5 6 XDS_EMU0 11 10 XDS_EMU1 14 13 S E# IA0 IA1 YA IB0 IB1 YB IC0 IC1 YC ID0 ID1 YD 8 15 of 26 15 EMU_ENABLE 4 EMU_TCK 7 EMU_RTCK 9 SOC_EMU_00_R 12 SOC_EMU_01_R Project K2E EVM EMU & JTAG Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 3 Designed for TI by eInfochips Title C Place U49 as close to MIPI-60 header as possible to minimize stubs on SOC_EMU_00_R and SOC_EMU_01_R 4 16 Size LAYOUT NOTE: 5 Place U55 as close to MIPI-60 header as possible to minimize stubs on SOC_EMU _19_R and SOC_EMU_20_R VCC3V3_AUX EPAD TRSTz AH32 AG31 AF29 AJ33 SOC_EMU_00 SOC_EMU_01 SOC_EMU_02 SOC_EMU_03 SOC_EMU_04 SOC_EMU_05 SOC_EMU_06 SOC_EMU_07 SOC_EMU_08 SOC_EMU_09 SOC_EMU_10 SOC_EMU_11 SOC_EMU_12 SOC_EMU_13 SOC_EMU_14 SOC_EMU_15 SOC_EMU_16 SOC_EMU_17 SOC_EMU_18 17 TMS TDI TDO TCK A AC5 AA6 AC4 AE6 AD6 AD3 AB5 AC3 AB4 AH3 AF3 AG4 AD2 AC2 AB3 AA5 AB2 Y5 AH2 GND EMU00 EMU01 EMU02 EMU03 EMU04 EMU05 EMU06 EMU07 EMU08 EMU09 EMU10 EMU11 EMU12 EMU13 EMU14 EMU15 EMU16 EMU17 EMU18 2 Sheet 1 15 of 37 A 5 4 3 2 1 PCIe TO SATA CONTROLLER AVDD1 VCC1V8 AVDD0 VAA1 DVDD1V0 D D VAA2_1 VAA2_0 R510 SATA_CLKN SATA_CLKP R511 R512 IN IN [12] [12] [12] [12] PCIe1_TX1N PCIe1_TX1P PCIe1_TX2N PCIe1_TX2P [12] [12] [12] [12] PCIe1_RX1N PCIe1_RX1P PCIe1_RX2N PCIe1_RX2P 45 44 43 41 42 36 37 IN IN IN IN C770 C769 C782 C771 OUT OUT OUT OUT PCIe_SPI_CLK PCIe_SPI_DI PCIe_SPI_DO PCIe_SPI_CS VCC1V8 C 10K 0E 0E 100nF 100nF 100nF 100nF R548 R543 R531 R535 25V 25V 25V 25V 38 39 33 34 22E 22E 22E 22E 8 6 3 5 CLKN CLKP TXN_0 TXP_0 TXN_1 TXP_1 PRXN0 PRXP0 PRXN1 PRXP1 RXN_0 RXP_0 RXN_1 RXP_1 88SE9182A2 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 PTXN0 PTXP0 PTXN1 PTXP1 SPI_CLK SPI_DI SPI_DO SPI_CS ISET TST0 TST1 TST2 TST3 TST4 TST5 TST6 NU 1% 1M XTALIN_OSC 1 TP TESTMODE XTLOUT 20 3 VSS 30 C795 33pF 50V TXN_1 TXP_1 22 21 16 15 RXN_1 RXP_1 OUT OUT IN IN AMC2_SATA0_TX_DN AMC2_SATA0_TX_DP [10] [10] AMC2_SATA0_RX_DN AMC2_SATA0_RX_DP [10] [10] 47 53 54 10 11 12 31 VCC5V R250 6.04K 1% J10 0678005001 RXP_1 RXN_1 48 49 50 51 55 56 2 27 13 TXN_1 TXP_1 C242 C241 C240 C239 100nF 25V 100nF 25V 100nF 25V 100nF 25V 6 5 3 2 RX_P RX_M TX_M TX_P GND[0] GND[1] GND[2] SH[0] SH[1] 1 4 7 C828 C826 100uF 10V 22uF 10V C825 C824 10uF 100nF 25V 25V C814 100nF 25V C813 10uF 25V C812 25V 22uF C M1 M2 FB12 3A J8 280371-2 1 2 3 4 30_100MHz SATA_GND TP58 R552 10K VCC12 EPAD Y6 ABM3B-25.000MHZ-B2-T 4 R554 1% NU 1M 24 25 18 19 57 2 32 PERST_N R555 29 VCONT_10 17 23 28 VAA1 VAA2_1 VAA2_0 52 7 35 40 AVDD1 AVDD0 VCC1V8 [24] [24] VDDIO_2 VDDIO_1 VDD_6 VDD_5 VDD_4 VDD_3 VDD_2 VDD_1 46 26 14 9 4 1 VCONT_10 U75 C791 33pF 50V EEPROM VCC3V3_AUX U76 AT26F004 DVDD1V0 VCC1V8 B FB33 120_100MHz PCIe_SPI_CS 1 PCIe_SPI_CLK 6 PCIe_SPI_DO 5 PCIe_SPI_DI 2 VAA1 CS# VCC SCL Si WP# HOLD# SO GND 8 C796 3 7 100nF 25V 4 B VCC1V8 C203 C207 C220 C222 C227 C224 C196 C799 C800 C801 C802 2.2uF 100nF 100nF 100nF 100nF 100nF 100nF 10V 25V 25V 25V 25V 25V 25V 2.2uF 100nF 10nF 10V 25V 25V 1nF 50V C216 2 1uF 16V VCC1V8 AVDD0 FB7 120_100MHz VCC1V8 FB11 120_100MHz VAA2_0 VCONT_10 1 Q9 PBSS5120T,215 2.2uF 100nF 10nF 10V 25V 25V C234 C235 C236 C237 1nF 50V 2.2uF 100nF 10nF 10V 25V 25V VCC1V8 1nF 50V 3 C193 C192 C191 C190 DVDD1V0 C217 10uF 25V AVDD1 FB9 120_100MHz VCC1V8 FB10 120_100MHz VAA2_1 C223 C221 C218 C213 C229 C230 C231 C232 2.2uF 100nF 10nF 10V 25V 25V 1nF 50V 2.2uF 100nF 10nF 10V 25V 25V 1nF 50V VCC1V8 Project K2E EVM A C749 10uF 25V Designed for TI by eInfochips C215 Title 100nF 25V Place these capacitor near to U75 PCIe to SATA Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 16 of 37 A 5 4 3 2 SOC EMIF 1 NAND FLASH VCC1V8 VCC1V8 U23V K2E_Processor K2E G5 K3 K4 J1 H5 J6 H6 H1 H2 G6 K5 H3 J4 H4 K6 J5 SOC_EMIFD0 SOC_EMIFD1 SOC_EMIFD2 SOC_EMIFD3 SOC_EMIFD4 SOC_EMIFD5 SOC_EMIFD6 SOC_EMIFD7 SOC_EMIFD8 SOC_EMIFD9 SOC_EMIFD10 SOC_EMIFD11 SOC_EMIFD12 SOC_EMIFD13 SOC_EMIFD14 SOC_EMIFD15 SOC_EMIFRNW_R EMIFWEz B Y C GND 0E A1 A2 A3 A4 A5 A6 A7 A8 SOC_EMIFRNW [11] 2 3 4 5 6 7 8 9 BI BI BI BI BI BI BI BI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 BUFF_EMIFD7 BUFF_EMIFD6 BUFF_EMIFD5 BUFF_EMIFD4 BUFF_EMIFD3 BUFF_EMIFD2 BUFF_EMIFD1 BUFF_EMIFD0 NAND_WPz IN R99 [29] [29] [29] [29] [29] [29] [29] [29] SOC_EMIFWEZ C7 C3 SOC_EMIFOEZ SOC_EMIFWAIT0 D4 C8 SOC_EMIFCE0Z SOC_EMIFA12 C6 D5 SOC_EMIFA11 C4 1% 4.7K VCC1V8 21 22 23 24 25 26 27 G3 G8 G5 R88 1% 4.7K WE WP RE R/B CE CLE ALE DNU1 DNU2 LOCK NU R95 1% 4.7K NU VSS1 VSS2 VSS3 VSS4 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 VCC1 VCC2 VCC3 VCC4 A1 A10 A2 A9 B1 B10 B9 D6 D7 D8 E3 E4 E5 E6 E7 E8 F3 F4 F5 F6 F8 G6 G7 H3 H5 H6 H7 J3 J5 L1 L10 L2 L9 M1 M10 M2 M9 D VCC1V8 G4 D3 H8 J6 C21 100nF 25V C22 100nF 25V C26 10uF 25V C 25V 100nF C371 SOC_EMIFRNW_R VCC1V8 SOC_EMIFRNW T6 N3 SOC_EMIFWAIT0 SOC_EMIFWAIT1 R5 SOC_EMIFWEZ EMIF_BUFF_OE SOC_EMIFD15 SOC_EMIFD14 SOC_EMIFD13 SOC_EMIFD12 SOC_EMIFD11 SOC_EMIFD10 SOC_EMIFD9 SOC_EMIFD8 19 18 17 16 15 14 13 12 11 OE B1 B2 B3 B4 B5 B6 B7 B8 SN74AUCH245RGYR A1 A2 A3 A4 A5 A6 A7 A8 E-PAD_1 E-PAD_2 E-PAD_3 E-PAD_4 E-PAD_5 E-PAD_6 E-PAD_7 2 3 4 5 6 7 8 9 BI BI BI BI BI BI BI BI BUFF_EMIFD15 BUFF_EMIFD14 BUFF_EMIFD13 BUFF_EMIFD12 BUFF_EMIFD11 BUFF_EMIFD10 BUFF_EMIFD9 BUFF_EMIFD8 [29] [29] [29] [29] [29] [29] [29] [29] 21 22 23 24 25 26 27 GND VCC1V8 SOC_EMIFCE3Z 6 R388 H4 J4 K4 K5 K6 J7 K7 J8 F7 K8 K3 C5 Y3 10 C30 100nF 25V U13 SN74LVC1G11DCKR 5 VCC SOC_EMIFCE1Z 1 A U53 MT29F4G08ABBDAH4D R183 1% 4.7K SN74AUCH245RGYR E-PAD_1 E-PAD_2 E-PAD_3 E-PAD_4 E-PAD_5 E-PAD_6 E-PAD_7 26 of 26 SOC_EMIFCE2Z 3 1 20 OE B1 B2 B3 B4 B5 B6 B7 B8 DIR 19 18 17 16 15 14 13 12 11 VCC U16 EMIF_BUFF_OE SOC_EMIFD7 SOC_EMIFD6 SOC_EMIFD5 SOC_EMIFD4 SOC_EMIFD3 SOC_EMIFD2 SOC_EMIFD1 SOC_EMIFD0 U14 EMIFWAIT0 EMIFWAIT1 Note: NAND FLASH Device size is 4Gb. SOC_EMIFD0 SOC_EMIFD1 SOC_EMIFD2 SOC_EMIFD3 SOC_EMIFD4 SOC_EMIFD5 SOC_EMIFD6 SOC_EMIFD7 25V 100nF C391 VCC1V8 SOC_EMIFOEZ Y2 EMIFOEz EMIFRnW R182 1% 4.7K GND SOC_EMIFCE0Z SOC_EMIFCE1Z SOC_EMIFCE2Z SOC_EMIFCE3Z SOC_EMIFCE2Z SOC_EMIFCE3Z DIR C AA1 Y4 W1 Y1 1K R184 1% 4.7K 10 EMIFD00 EMIFD01 EMIFD02 EMIFD03 EMIFD04 EMIFD05 EMIFD06 EMIFD07 EMIFD08 EMIFD09 EMIFD10 EMIFD11 EMIFD12 EMIFD13 EMIFD14 EMIFD15 SOC_EMIFBE0Z SOC_EMIFBE1Z 1K R74 1 EMIFCE0z EMIFCE1z EMIFCE2z EMIFCE3z AA2 R6 R418 SOC_EMIFWAIT0 20 EMIFBE0z EMIFBE1z SOC_EMIFWAIT1 VCC D [29] SOC_EMIFWAIT1 OUT SOC_EMIFA00 SOC_EMIFA01 SOC_EMIFA02 SOC_EMIFA03 SOC_EMIFA04 SOC_EMIFA05 SOC_EMIFA06 SOC_EMIFA07 SOC_EMIFA08 SOC_EMIFA09 SOC_EMIFA10 SOC_EMIFA11 SOC_EMIFA12 SOC_EMIFA13 SOC_EMIFA14 SOC_EMIFA15 SOC_EMIFA16 SOC_EMIFA17 SOC_EMIFA18 SOC_EMIFA19 SOC_EMIFA20 SOC_EMIFA21 SOC_EMIFA22 SOC_EMIFA23 P3 P5 U6 V6 P6 N6 M3 N4 N5 M5 M4 L1 U5 T5 L3 T3 L2 L5 M6 K2 K1 L4 R3 L6 EMIFA00 EMIFA01 EMIFA02 EMIFA03 EMIFA04 EMIFA05 EMIFA06 EMIFA07 EMIFA08 EMIFA09 EMIFA10 EMIFA11 EMIFA12 EMIFA13 EMIFA14 EMIFA15 EMIFA16 EMIFA17 EMIFA18 EMIFA19 EMIFA20 EMIFA21 EMIFA22 EMIFA23 SOC_EMIFCE1Z EMIF_BUFF_OE 4 2 VCC1V8 B B VCC1V8 1OE# 2OE# 18 16 14 12 9 7 5 3 OUT OUT OUT OUT BUFF_EMIFA16 BUFF_EMIFA17 BUFF_EMIFA18 BUFF_EMIFA19 [29] [29] [29] [29] OUT OUT OUT OUT BUFF_EMIFA20 BUFF_EMIFA21 BUFF_EMIFA22 BUFF_EMIFA23 [29] [29] [29] [29] EPAD 2Y1 2Y2 2Y3 2Y4 10 EMIF_BUFF_OE 1 19 2A1 2A2 2A3 2A4 GND [29] [29] [29] [29] 11 13 15 17 VCC1V8 C20 C19 100nF 25V 1uF 16V 9 7 5 3 VCC OUT OUT OUT OUT OUT OUT OUT OUT BUFF_EMIFA08 BUFF_EMIFA09 BUFF_EMIFA10 BUFF_EMIFA11 BUFF_EMIFA12 BUFF_EMIFA13 BUFF_EMIFA14 BUFF_EMIFA15 SOC_EMIFBE0Z SOC_EMIFBE1Z SOC_EMIFCE1Z SOC_EMIFCE2Z [29] [29] [29] [29] 2 4 6 8 SOC_EMIFCE3Z 11 SOC_EMIFRNW 13 SOC_EMIFOEZ 15 SOC_EMIFWEZ 17 [29] [29] [29] [29] 1 19 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2A1 2A2 2A3 2A4 1OE# 2OE# 2Y1 2Y2 2Y3 2Y4 20 18 16 14 12 9 7 5 3 EPAD 1OE# 2OE# 20 18 16 14 12 C25 C29 100nF 25V 1uF 16V U54 SN74AUCH244RGYR GND 2Y1 2Y2 2Y3 2Y4 EPAD EMIF_BUFF_OE 1 19 2A1 2A2 2A3 2A4 GND 11 13 15 17 BUFF_EMIFA04 BUFF_EMIFA05 BUFF_EMIFA06 BUFF_EMIFA07 21 SOC_EMIFA12 SOC_EMIFA13 SOC_EMIFA14 SOC_EMIFA15 1Y1 1Y2 1Y3 1Y4 10 A 1A1 1A2 1A3 1A4 OUT OUT OUT OUT SOC_EMIFA20 SOC_EMIFA21 SOC_EMIFA22 SOC_EMIFA23 20 OUT OUT OUT OUT BUFF_EMIFBE0Z BUFF_EMIFBE1Z BUFF_EMIFCE1Z BUFF_EMIFCE2Z [29] [29] [29] [29] OUT OUT OUT OUT BUFF_EMIFCE3Z BUFF_EMIFRNW BUFF_EMIFOEZ BUFF_EMIFWEZ [29] [29] [29] [29] Project K2E EVM SoC_EMIF_NAND INTERFACE C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 Designed for TI by eInfochips Title Size 21 VCC 2 4 6 8 [29] [29] [29] [29] 1Y1 1Y2 1Y3 1Y4 VCC1V8 U6 SN74AUCH244RGYR SOC_EMIFA08 SOC_EMIFA09 SOC_EMIFA10 SOC_EMIFA11 BUFF_EMIFA00 BUFF_EMIFA01 BUFF_EMIFA02 BUFF_EMIFA03 1A1 1A2 1A3 1A4 10 1OE# 2OE# 2Y1 2Y2 2Y3 2Y4 10 EMIF_BUFF_OE 1 19 2A1 2A2 2A3 2A4 9 7 5 3 OUT OUT OUT OUT EPAD 11 13 15 17 1Y1 1Y2 1Y3 1Y4 GND SOC_EMIFA04 SOC_EMIFA05 SOC_EMIFA06 SOC_EMIFA07 1A1 1A2 1A3 1A4 18 16 14 12 2 4 6 8 21 2 4 6 8 VCC 20 SOC_EMIFA16 SOC_EMIFA17 SOC_EMIFA18 SOC_EMIFA19 21 VCC SOC_EMIFA00 SOC_EMIFA01 SOC_EMIFA02 SOC_EMIFA03 U10 SN74AUCH244RGYR C23 C24 100nF 1uF 25V 16V U51 SN74AUCH244RGYR C28 C27 100nF 25V 1uF 16V 2 Sheet 1 17 of 37 A 5 4 3 2 1 I2C--0 1V8 to 3V3 CONVERTER UART 1V8 to 3V3 CONVERTER VCC1V8 VCC3V3_MP VCC1V8 VCC1V8 VCC3V3_AUX U23Q K2E_Processor C516 SPI--2 [29] [29] [29] [29] [29] [29] [29] 22E P31 22E R29 22E P33 22E L30 22E R31 P30 22E L33 R541 R526 R233 R524 R542 SOC_SPI2_CS0 OUT OUT SOC_SPI2_CS1 SOC_SPI2_CS2 OUT OUT SOC_SPI2_CS3 SOC_SPI2_DOUT OUT SOC_SPI2_DIN IN OUT SOC_SPI2_CLK SPI1SCS0 SPI1SCS1 SPI1SCS2 SPI1SCS3 SPI1DOUT SPI1DIN SPI1CLK R232 T31 T33 R235 U29 T32 R234 SOC_UART1_CTS_V1P8 22E SOC_UART1_RTS_V1P8 SOC_UART1_RXD_V1P8 22E SOC_UART1_TXD_V1P8 J33 H33 K29 USIMCLK USIMIO USIMRST AG28 AG30 AJ32 AH30 AG29 AH31 SDA0 SCL0 SDA1 SCL1 SDA2 SCL2 100nF 25V 2 10 1% 4.7K R329 SOC_UART0_RXD_V1P8 1 SOC_UART0_TXD_V1P8 3 4 5 SOC_UART1_RXD_V1P8 6 SOC_UART1_TXD_V1P8 7 SOC_UART1_RTS_V1P8 8 SOC_UART1_CTS_V1P8 9 R538 R523 IN IN OUT OUT 22E 22E SOC_SDA0 SOC_SCL0 SOC_SDA1 SOC_SCL1 SOC_SDA2 SOC_SCL2 4.7K 4.7K SOC_TIMI0 SOC_TIMI1 SOC_TIMO0 SOC_TIMO1 [29] [29] [29] [29] OE A1 A2 A3 A4 A5 A6 A7 A8 TXS0108EPWR 100nF 25V 1 2 3 4 1% SOC_SCL0 SOC_SDA0 VCC1V8 R240 4.7K 1% IN OUT OUT IN SOC_UART1_RX_3V3 SOC_UART1_TX_3V3 SOC_UART1_RTS_3V3 SOC_UART1_CTS_3V3 VCC3V3_MP R425 R422 4.7K 4.7K 1% 1% NU NU [27] [27] EEPROM1 M24M01-RMN6TP 1 2 3 4 PMBus mode R429 4.7K 1% MCU_EXP_SCL MCU_EXP_SDA IN BI DU E1 E2 VSS R459 R466 R423 4.7K 1% IN SOC_SCL0 SOC_SDA0 EEPROM_WPz [18] USB_VIO 0E R615 I2C--1 1V8 to 3V3 CONVERTER C7 C6 1uF 16V 100nF 25V 1uF 16V DD+ 7 1 USB_VBUS B D13 TPD4S012DRYR 8 VBUS 6 USB_VBUS_R 2 10KV 100nF 25V GND C4 5 120_100MHz 4 FB13 4 3 90 OHM DIFF. IMPEDANCE CONTROL GND_USB VDD VIO 7 REGIN USB_VBUS_R 3 1 2 3 4 5 RST VCC3V3_AUX C736 RTS_ECI CTS_ECI RXD_ECI TXD_ECI GPIO.1_ECI / DSR_ECI GPIO.0_ECI / DTR_ECI NC / DCD_ECI / VPP SUSPEND / RI_ECI RXD_SCI TXD_SCI RTS_SCI CTS_SCI GPIO.2_SCI / DSR_SCI GPIO.1_SCI / DTR_SCI GPIO.0_SCI / DCD_SCI SUSPEND / RI_SCI 11 10 12 13 14 15 16 17 1 2 3 4 SOC_SCL1 SOC_SDA1 SOC_UART0_Detect SOC_UART0_RXD_3V3 VCC1V8 R494 R491 VCCA SCLA SDAA GND 100nF 25V VCCB SCLB SDAB EN 8 7 6 5 OUT DIMM_SCL [25] BI DIMM_SDA [25] SOC_I2C1_DIMM_EN IN VCC3V3_AUX 4.7K 1% 4.7K 1% R497 R493 0E VCC3V3_AUX [11] 4.7K 1% 4.7K 1% VCC3V3_AUX VCC1V8 R361 4.7K IN OUT R359 4.7K SOC_UART0_TXD_3V3 [27] CP2105_SOC_U0RX [18] IN OUT MCU_PA1_U0TX [27,28] CP2105_MCU_U0RX [27] U50 MAX3221ECPWR 12 16 SOC_URX_3V3 20 21 19 18 22 23 24 1 C737 U71 TCA9517DR 100nF 25V VCC3V3_AUX SOC_UART0_TXD_3V3 9 11 R358 C343 100nF 25V 2 4.7K 4 NU DAP 100nF 25V 2 6 PTH2 PTH1 VBUS DD+ GND_1 GND_2 CP2105_SOC_U0RX I N C346 100nF 25V 3 25 4.7K 1% 9 R6 J1 54819-0519 1 2 3 4 U52 SN74LVC2G157DCUT 8 A VCC 7 B G 6 Y A/B 5 GND Y 6 5 C3 C322 PW_SEQ_SCL [18,19,28] PW_SEQ_SDA [18,19,28] PW_SEQ_I2C_EN [27] [11] VCC1V8 SOC_URX_3V3 R613 NU 0E USB_VIO OUT BI IN 4.7K 1% 4.7K 1% R421 4.7K 1% VCC3V3_AUX U2 CP2105 100nF 25V 8 7 6 5 VCCB SCLB SDAB EN VCC3V3_MP C468 100nF 25V 8 7 6 5 VCC WC SCL SDA VCCA SCLA SDAA GND C SoC UART0 TO USB FB14 220_100MHz C541 U66 TCA9517DR 1 2 3 4 VCC3V3_AUX USB_VBUS [27] VCC3V3_MP VCC1V8 R242 4.7K 1% NU SOC_I2C_EN 3V3 I2C ISOLATOR [29] [29] [29] [29] VCC1V8 - VCNTL mode (Default): Pull-down are installed and Pull-ups are NU - PMBus Mode: Install Pull-ups and depopulate Pull-downs R614 IN SOC_UART0_RXD_3V3 SOC_UART0_TXD_3V3 VCC1V8 R241 4.7K 1% MCU_EXP_SCL MCU_EXP_SDA D 20 18 17 16 15 14 13 12 B1 B2 B3 B4 B5 B6 B7 B8 VCNTL mode NOTE: 8 7 6 5 VCCB SCLB SDAB EN C542 SOC_TIMI0 SOC_TIMI1 USB_VBUS VCCA SCLA SDAA GND U45 I2C EEPROM R239 4.7K 1% NU 100nF 25V U64 TCA9517DR 100nF 25V 18 of 26 C 100nF 25V 19 VCC1V8 UART--1 R238 NU 0E R243 NU 0E R522 NU 0E K33 K32 K31 K30 TIMI0/AVSIFSEL0 TIMI1/AVSIFSEL1 TIMO0 TIMO1 C332 1% W29 TP56TP54TP82 U33 UART0DSR UART0DTR SPI2SCS0 SPI2SCS1 SPI2SCS2 SPI2SCS3 SPI2DOUT SPI2DIN SPI2CLK SOC_UART0_RXD_V1P8 22E SOC_UART0_TXD_V1P8 C335 VCCB P29 M32 N30 N33 P32 R30 M33 UART1CTS UART1RTS UART1RXD UART1TXD R33 R32 T29 T30 R527 VCCA SPI--0 D UART0CTS UART0RTS UART0RXD UART0TXD GND TP60 TP59 SPI0_DOUT TP57 R525 SPI0_DIN SPI0_CLK R540 SPI0SCS0 SPI0SCS1 SPI0SCS2 SPI0SCS3 SPI0DOUT SPI0DIN SPI0CLK 11 22E L31 M29 L29 L32 22E N29 M31 22EM30 R539 C515 R435 R440 K2E SPI0_CS0 10 FORCEON FORCEOFF# RIN DIN DOUT C1+ C2+ C1- C2- V+ 1uF 16V 100nF 25V I2C--1 PMBus Connection C722 100nF 25V VCC3V3_AUX 8 SOC_RS232_RX 13 SOC_RS232_TX 5 C342 100nF 25V SOC_UART0_Detect R339 4.7K 1% COM1 1 2 3 4 U69 PCA9306DCUR 1 2 3 4 SOC_SCL1 SOC_SDA1 GND VREF1 SCL1 SDA1 EN VREF2 SCL2 SDA2 8 7 6 5 R484 22-23-2041 2.2K R480 2.2K IN OUT BI VCC1V8 R474 200K5% SOC_I2C1_PMBUS_EN PW_SEQ_SCL PW_SEQ_SDA [11] [18,19,28] [18,19,28] C724 100nF 25V B 6 7 V- C341 100nF 25V 1 14 EN# GND INVALID# C356 15 VCC ROUT C352 I2C--2 1V8 to 3V3 CONVERTER GND_USB VCC1V8 VCC3V3_AUX DEBUG LEDs C97 VCC3V3_AUX DBG_D1 3 3 2 [11] SOC_DEBUG_LED1 510E1 1% R48 IN 2 VCC1V8 R443 7 16 15 22E 8 VCC DU/NC8 DU/NC7 DU/NC6 DU/NC5 DU/NC4 DU/NC3 DU/NC2 DU/NC1 S SCK DQ0 DQ1 R200 R197 1 Q12 2N3904 0.2A 2 14 13 12 11 6 5 4 3 DBG_D2 2 1 SOC_DEBUG_LED3 R70 IN 510E1 1% K2E EVM 9 W/Vpp/DQ2 R453 4.7K 1% [11] SOC_DEBUG_LED4 R353 IN 510E1 1% SML-LX0402USBC-TR Q13 2N3904 0.2A 4 3 R193 4.7K OUT EXP_SCL2_3V3 BI EXP_SDA2_3V3 VCC3V3_AUX [10,29] [10,29] VCC3V3_AUX 4.7K 1% 4.7K 1% Designed for TI by eInfochips Title 120E Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 100nF 25V 8 7 6 5 MISC R73 R 3 IN DBG_D3 2 1 2 NOR_WPz HOLD/DQ3 VSS [27] VCC3V3_AUX 1 4.7K 1% VCCB SCLB SDAB EN R201 R198 Project Q5 2N3904 0.2A VCC1V8 R428 VCCA SCLA SDAA GND 120E R [11] 4.7K 1% 4.7K 1% 1 2 3 4 VCC3V3_AUX R71 SML-LX0402USBC-TR 3 SPI0_CS0 SPI0_CLK SPI0_DOUT 4.7K 1% SPI0_DIN R447 510E 1% 2 VCC1V8 R340 IN NOR1 N25Q128A11ESF40F 10 A SOC_DEBUG_LED2 SOC_SCL2 SOC_SDA2 VCC1V8 KPBA-3010ESGC Q4 2N3904 0.2A C98 U21 TCA9517DR 100nF 25V 49.9E 3 [11] 2 1 R69 R 128Mb SPI NOR Flash C474 100nF 25V G 2 Sheet 1 18 of 37 A 5 4 3 2 1 SOC REFERENCE CLOCK PCI CLOCK MUX VCC3V3_AUX All blocking capacitors should be placed near SOC to keep connect i ng r out es s hort and m i ni m i z e vi as VCC3V3_PCIE SEL I/p PAIR SEL IN2/IN2# HIGH IN1/IN1# 3 B7 2200pF 0.7A C493 10nF 25V 2 LOW 1 C494 10nF 25V C584 10nF 25V C594 10uF 25V K2E [23] [23] NETCPCLKN NETCPCLKP IN IN [24] [24] DDR3_CLKN DDR3_CLKP IN IN HYPER0_LINK_CLKN HYPER0_LINK_CLKP IN IN SGMIICLKN SGMIICLKP IN IN D [24] [24] VCC3V3_PCIE VCC3V3_AUX [10] PCIE_REF_CLK_P R451 2 IN R456 (LVDS) R463 NU 10K [10] PCIE_REF_CLK_N [24] PCIE0CLKP IN [24] PCIE0CLKN IN IN1 VDD_1 VDD_2 VDD_3 100E 3 IN PCIECLK_MUX_SEL PCIECLKN_R R462 R444 C532 100nF 25V PCIECLKP_R (HCSL) R448 C506 100nF 25V PCIECLKN_R 5 CLK IN PCIECLK_MCU_PD PCIECLK_OE IN IN 100nF 25V 100nF 25V G3 G4 AJ8 AJ7 C681 C673 AJ25 AJ24 100nF 6.3V 100nF 6.3V AJ18 AJ17 15 PCIECLKP_MR R457 PCIE0CLKP_M 33E 1% [24] [24] PCIE1CLKN PCIE1CLKP IN IN [23] [23] XFICLKN XFICLKP IN IN CORECLKN CORECLKP IN IN AJ15 AJ14 H32 J32 AE2 AF2 G2 G1 AL3 AL2 AG5 K8 J8 W8 W7 J30 J29 AG8 AJ20 AG12 AJ28 AJ26 AH9 B19 E20 A14 RSV000 RSV001 RSV002 RSV003 RSV004 RSV005 RSV006 RSV007 RSV008 RSV009 RSV010 RSV011 RSV012 RSV013 RSV014 RSV015 RSV016 RSV017 RSV018 RSV019 RSV020 RSV021 RSV022 RSV023 DDRCLKN DDRCLKP HYPLNK0CLKN HYPLNK0CLKP SGMII0CLKN SGMII0CLKP PCIE0CLKN PCIE0CLKP PCIE1CLKN PCIE1CLKP SOC_RSV000 SOC_RSV001 SOC_RSV002 SOC_RSV003 SOC_RSV004 SOC_RSV005 SOC_RSV006 SOC_RSV007 SOC_RSV008 SOC_RSV009 SOC_RSV010 SOC_RSV011 SOC_RSV012 SOC_RSV013 SOC_RSV014 SOC_RSV015 SOC_RSV016 SOC_RSV017 SOC_RSV018 SOC_RSV019 SOC_RSV020 SOC_RSV021 SOC_RSV022 SOC_RSV023 R236 R237 R419 R420 R210 R206 R430 R427 R445 0E 0E 0E 0E 0E 0E 0E 0E OUT TP53 TP55 TP65 TP64 TP43 TP42 TP67 TP66 SOC_RSV008 0E R173 R174 R521 R534 R433 R473 R461 0E 0E 0E 0E 0E 0E 0E R437 0E R214 0E D [11] TP70 TP36 TP37 TP81 TP80 TP68 TP74 TP71 TP75 TP76 TP69 TP72 TP73 TP47 100E 6 CLK CLK_MUX_SEL 16 4 7 R464 R442 10K 10K 14 PCIECLKN_MR R452 SEL GND_1 GND_2 GND_3 PD OE 9 R439 PCIE0CLKN_M 33E 1% IN2 IREF PCIECLK_MUX_SEL C457 C456 NETCPCLKN NETCPCLKP R455 NU 100E 1.2K [27] [27] 100nF 25V NETCPCLKN_R AN3 100nF 25V NETCPCLKP_R AM2 PCIE0CLKN_M PCIE0CLKP_M IN2 10K [27] 1 10 11 C73 C72 IN1 PCIECLKP_R 10K [23] [23] U65 IDT5V41068APGGI VCC3V3_PCIE NOTE: These series resistors will deleted in future revisions. U23H K2E_Processor C492 10uF 25V R450 R458 150E 150E AJ12 AJ11 XFICLKN XFICLKP 475E [23] [23] 8 12 13 C95 C94 AG1 AF1 100nF 25V 100nF 25V CORECLKN CORECLKP 8 of 26 C C LAYOUT NOTE: SMART REFLEX Make sure that TP33 is on top layer U23M K2E_Processor K2E R165 TP33 VCC1V8 [11] U23P K2E_Processor K2E VCL VD B VCNTL0 VCNTL1 VCNTL2 VCNTL3 VCNTL4 VCNTL5 V29 DSP_VCL_R U30 DSP_VD_R H29 G33 H31 H30 G32 J31 R536 4.7K 1% R528 4.7K 1% R244 4.7K 1% [11] [11,27] R537 4.7K 1% [11] SOC_PORZ [11] SOC_RESETZ [11] SOC_LRESETZ SOC_RESETFULLZ SOC_RESETSTATZ SOC_LRESETNMIENZ LM10011_VID1A LM10011_VID1B LM10011_VID1C LM10011_VID1S AE4 AH33 IN AE29 AF33 AF32 AH29 IN IN IN OUT AE30 IN VCC1V8 OUT OUT OUT OUT 0E R506 BOOTCOMPLETE SYSCLKOUT NMIz PORz HOUT RESETz LRESETz RESETFULLz RESETSTATz NETCPCLKSEL AF31 AG33 AF30 AG6 OUT IN SOC_BOOTCOMPLETE SOC_NMIZ SOC_HOUT OUT IN [11] [11] SOC_PACLKSEL [11] [11] LRESETNMIENz B 14 of 26 4.7K 1% [31] [31] [31] [31] 17 of 26 SOC_PORZ NOTE: These caps are for early silicon debug purposes ONLY and SHOULD NOT be implemented on customer designs. SOC_RESETZ C726 NU 100nF 25V C200 NU 100nF 25V SOC_RESETFULLZ C197 NU 100nF 25V C201 NU 10nF 25V C727 NU 10nF 25V C198 NU 10nF 25V C202 NU 1nF 50V C728 NU 1nF 50V C199 NU 1nF 50V VCC1V8 C650 100nF 25V R231 4.7K 1% SOC_RESETFULLZ R230 1K SOC_RESETZ R488 1K U67 PCA9306DCUR DSP_VCL_R DSP_VD_R A SOC_PORZ VCC1V8 R468 2.2K R470 2.2K 1 2 3 4 GND VREF1 SCL1 SDA1 EN VREF2 SCL2 SDA2 8 7 6 5 R471 200K 5% IN OUT BI DSP_PMBUS_EN PW_SEQ_SCL PW_SEQ_SDA [11,27] [18,28] [18,28] Project K2E EVM C661 100nF 25V Designed for TI by eInfochips Title CLOCK and SMART REFLEX Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 19 of 37 A 5 4 3 SOC POWER 2 1 VCC1V8 Place near to SOC U23D K2E_Processor VCC1V8 VCC1V8 K2E J2 J28 K27 L8 L28 M2 M7 M27 D N8 N28 N31 P7 P27 R28 DVDD18_1 DVDD18_2 DVDD18_3 DVDD18_4 DVDD18_5 DVDD18_6 DVDD18_7 DVDD18_8 DVDD18_9 DVDD18_10 DVDD18_11 DVDD18_12 DVDD18_13 DVDD18_14 VCC0V75REF F15 DDRVREFSSTL C576 100nF 6.3V 4 of 26 DVDD18_15 DVDD18_16 DVDD18_17 DVDD18_18 DVDD18_19 DVDD18_20 DVDD18_21 DVDD18_22 DVDD18_23 DVDD18_24 DVDD18_25 DVDD18_26 DVDD18_27 DVDD18_28 DVDD18_29 DVDD18_30 DVDD18_31 DVDD18_32 DVDD18_33 DVDD18_34 DVDD18_35 DVDD18_36 DVDD18_37 DVDD18_38 DVDD18_39 DVDD18_40 DVDD18_41 DVDD18_42 DVDD18_43 T7 T27 U28 U31 V7 V27 W28 Y7 Y27 AA3 AA8 AA28 AA31 AB7 AB27 AC8 C708 C761 C760 C712 100nF 6.3V 10uF 25V 10uF 25V 4.7uF 10V D VCC1V8 Place near to SOC pins AC28 AD4 AD27 AE8 AE26 AE28 AE31 AF27 AG26 AH27 AJ30 AM33 AN32 C497 C500 C501 C489 C470 C485 C496 C715 C717 100nF 6.3V 100nF 6.3V 100nF 6.3V 10nF 10V 10nF 10V 10nF 10V 1000pF 50V 1000pF 50V 1000pF 50V These Caps are added recently VCC1V8 Place near to SOC pins VCC1V8 Place near to SOC pins C716 C502 C707 C714 C709 C473 C718 C711 C471 560pF 16V 560pF 16V 560pF 16V 560pF 16V 560pF 16V 560pF 16V 560pF 16V 560pF 16V 560pF 16V C479 C710 C483 C725 C704 C703 C484 C729 C719 560pF 16V 560pF 16V 560pF 16V 100nF 6.3V 100nF 6.3V 100nF 6.3V 10nF 10V 10nF 10V 10nF 10V C C VCC1V8 AVDDA1 10nF 10V AVDDA1 AVDDA2 AVDDA3 AVDDA6 AVDDA7 AVDDA8 AVDDA9 AVDDA10 K9 M9 VPP0 VPP1 C511 100nF 6.3V VCC1V5 A2 A32 B1 B33 C3 C7 C11 C17 C21 C25 C31 D5 D9 D14 D19 D23 D27 D29 F5 F7 F9 F11 F13 F17 F19 F21 F23 F25 F27 F29 G10 G14 G20 G26 G28 G30 H7 B AF7 AVDDA1 K7 AVDDA2 VDDPLL0 AD7 AVDDA3 G8 E14 G16 G22 G24 AVDDA2 C482 FB21 470_100MHz 1A C481 10nF 10V 100nF 6.3V VCC1V5 DVDD15_38 DVDD15_39 DVDD15_40 DVDD15_41 DVDD15_42 DVDD15_43 DVDD15_44 DVDD15_45 DVDD15_46 DVDD15_47 AVDDA3 H9 H11 H13 H15 H17 H19 H21 H23 H25 H27 C562 C495 C586 C551 C674 C651 10nF 10V 100nF 6.3V 10nF 10V 100nF 6.3V 10nF 10V 100nF 6.3V VCC1V8 Close to SOC DVDD15_1 DVDD15_2 DVDD15_3 DVDD15_4 DVDD15_5 DVDD15_6 DVDD15_7 DVDD15_8 DVDD15_9 DVDD15_10 DVDD15_11 DVDD15_12 DVDD15_13 DVDD15_14 DVDD15_15 DVDD15_16 DVDD15_17 DVDD15_18 DVDD15_19 DVDD15_20 DVDD15_21 DVDD15_22 DVDD15_23 DVDD15_24 DVDD15_25 DVDD15_26 DVDD15_27 DVDD15_28 DVDD15_29 DVDD15_30 DVDD15_31 DVDD15_32 DVDD15_33 DVDD15_34 DVDD15_35 DVDD15_36 DVDD15_37 FB28 100_100MHz 1.2A VCC1V8 Close to SOC K2E VPP1V8 VDDPLL0 FB26 470_100MHz C476 1A C491 10uF 25V 100nF 6.3V C490 U23B K2E_Processor VCC1V8 Close to SOC Close to SOC C486 FB24 470_100MHz 1A C477 10nF 10V 100nF 6.3V B Close to SOC VCC1V5 VCC1V5 VCC1V5 Place near to SOC Place near to SOC pins C601 C602 C475 C713 C705 C706 C685 C638 C664 C637 C611 C720 4.7uF 10V 4.7uF 10V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V C697 560pF 16V C622 560pF 16V C612 560pF 16V C613 560pF 16V C536 560pF 16V C510 560pF 16V C487 560pF 16V C564 560pF 16V C721 560pF 16V C472 560pF 16V 2 of 26 Project K2E EVM A Title VCC1V5 Place near to SOC pins SOC_POWERA C488 C533 C507 C553 C519 C684 C595 C552 C691 C671 C480 C663 C577 C565 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 Designed for TI by eInfochips 4 3 2 Sheet 1 20 of 37 A 5 4 CVDD U23A K2E_Processor CVDD D C 2 1 CVDD1 CVDD K2E J12 J14 J16 J18 J20 J22 J26 K11 K13 K15 K17 K19 K21 K23 K25 L10 L12 L14 L16 L18 L20 L22 M15 M17 M19 M21 M25 N10 N14 N16 N18 N20 N22 N26 P13 P15 P17 P19 P21 P23 P25 R14 R16 R18 R20 R22 R24 R26 T13 T15 T17 T19 T21 T23 T25 U12 U14 U16 U18 U20 U22 U24 U26 V13 V15 V17 V19 V21 V23 V25 W12 W14 W16 W18 W20 W22 W24 W26 Y9 Y15 Y17 Y19 Y21 Y25 AA10 AA16 3 SOC POWER 0.85V - 1.05V (CVDD) (Smart Reflex) CVDD_87 CVDD_88 CVDD_89 CVDD_90 CVDD_91 CVDD_92 CVDD_93 CVDD_94 CVDD_95 CVDD_96 CVDD_97 CVDD_98 CVDD_99 CVDD_100 CVDD_101 CVDD_102 CVDD_103 CVDD_104 CVDD_105 CVDD_106 CVDD_107 CVDD_108 CVDD_109 CVDD_110 CVDD_111 CVDD_112 CVDD_113 CVDD_114 CVDD_01 CVDD_02 CVDD_03 CVDD_04 CVDD_05 CVDD_06 CVDD_07 CVDD_08 CVDD_09 CVDD_10 CVDD_11 CVDD_12 CVDD_13 CVDD_14 CVDD_15 CVDD_16 CVDD_17 CVDD_18 CVDD_19 CVDD_20 CVDD_21 CVDD_22 CVDD_23 CVDD_24 CVDD_25 CVDD_26 CVDD_27 CVDD_28 CVDD_29 CVDD_30 CVDD_31 CVDD_32 CVDD_33 CVDD_34 CVDD_35 CVDD_36 CVDD_37 CVDD_38 CVDD_39 CVDD_40 CVDD_41 CVDD_42 CVDD_43 CVDD_44 CVDD_45 CVDD_46 CVDD_47 CVDD_48 CVDD_49 CVDD_50 CVDD_51 CVDD_52 CVDD_53 CVDD_54 CVDD_55 CVDD_56 CVDD_57 CVDD_58 CVDD_59 CVDD_60 CVDD_61 CVDD_62 CVDD_63 CVDD_64 CVDD_65 CVDD_66 CVDD_67 CVDD_68 CVDD_69 CVDD_70 CVDD_71 CVDD_72 CVDD_73 CVDD_74 CVDD_75 CVDD_76 CVDD_77 CVDD_78 CVDD_79 CVDD_80 CVDD_81 CVDD_82 CVDD_83 CVDD_84 CVDD_85 CVDD_86 AA18 AA20 AA22 AA26 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB25 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AC24 AC26 AD11 AD13 AD15 AD17 AD19 AD21 AD25 Place near to SOC C66 C438 C437 C62 C63 100uF 6.3V 47uF 6.3V 47uF 6.3V 10uF 25V 10uF 25V C781 C793 100uF 6.3V 4.7uF 25V C675 560pF 16V C678 560pF 16V C668 C672 10nF 10V 100nF 6.3V C534 560pF 16V C548 560pF 16V C555 C570 10nF 10V 100nF 6.3V CVDD Place near to SOC pins CVDD Place near to SOC pins C641 C509 C559 C535 C645 C642 C677 C547 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V 100nF 6.3V C699 C688 C543 C566 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V D CVDD Place near to SOC pins C698 47nF 50V CVDD CVDD1 Place near to SOC pins CVDD1_1 CVDD1_2 CVDD1_3 CVDD1_4 CVDD1_5 CVDD1_6 CVDD1_7 CVDD1_8 CVDD1_9 CVDD1_10 CVDD1_11 CVDD1_12 C666 L24 M11 M13 M23 N12 N24 Y13 Y23 AA12 AA14 AA24 AB23 C665 47nF 50V C686 47nF 50V C578 C554 C521 C522 C587 C544 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V C181 100nF 25V C751 100nF 25V C170 100nF 25V C459 C89 C742 C755 1uF 16V 1uF 16V 1uF 16V 1uF 16V Place near to SOC pins C571 C582 C643 C694 C629 C628 C590 C657 C658 C549 C526 C508 C580 C627 22nF 6.3V 22nF 6.3V 22nF 6.3V 22nF 6.3V 22nF 6.3V 22nF 6.3V 22nF 6.3V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V 10nF 10V C449 100nF 25V CVDD C167 100nF 25V CVDD C179 100nF 25V C90 100nF 25V C172 100nF 25V C744 100nF 25V C173 100nF 25V C753 100nF 25V Place near to SOC pins CVDD1 VNWA1 VNWA2 VNWA3 VNWA4 C656 22nF 6.3V C617 22nF 6.3V C591 22nF 6.3V C569 22nF 6.3V C690 22nF 6.3V C644 22nF 6.3V C525 22nF 6.3V CVDD CVDD P9 J24 AD23 AD9 CVDD CVDD Place near to SOC CVDD RSV026 RSV027 VDDCMON VSSCMON L26 R477 0E K26 R478 0E J10 J9 C520 NU 100nF 6.3V OUT VDDCMON [31] OUT VSSCMON [31] C439 C64 C65 C436 100uF 6.3V 100uF 6.3V 47uF 6.3V 10uF 25V Place near to SOC pins C626 47nF 50V C687 47nF 50V C689 C667 10nF 10V 10nF 10V Place near to SOC pins C619 22nF 6.3V C618 22nF 6.3V C558 22nF 6.3V C702 22nF 6.3V C78 C79 C740 C741 470nF 10V 470nF 10V 470nF 10V 470nF 10V C CVDD CVDD Place near to SOC pins C701 22nF 6.3V C581 22nF 6.3V C616 C700 100nF 6.3V 100nF 6.3V C676 100nF 6.3V CVDD C655 CVDD 100nF 6.3V C169 C80 C739 C168 C448 C77 4.7uF 10V 4.7uF 10V 2.2uF 10V 2.2uF 10V 2.2uF 10V 2.2uF 10V C503 NU 100nF 6.3V 1 of 26 CVDD C750 100nF 25V C752 100nF 25V C754 100nF 25V C460 100nF 25V C93 100nF 25V C92 100nF 25V C76 100nF 25V C464 100nF 25V C182 220nF 10V C180 220nF 10V C178 220nF 10V C743 220nF 10V C738 220nF 10V C171 220nF 10V C166 220nF 10V C465 100nF 25V C461 100nF 25V C91 100nF 25V C447 100nF 25V C451 100nF 25V CVDD CVDD Place TOP Tie C183 220nF 10V C452 220nF 10V C445 220nF 10V C450 220nF 10V C88 220nF 10V C458 220nF 10V C446 220nF 10V C81 220nF 10V C466 220nF 10V B B VCC0V85 U23C K2E_Processor VDDALV THESE CAPS ARE ADDED FOR PROVISION ONLY. VALUES CAN BE CHANGED BASED ON PI ANALYSIS RESULT K2E FB31 AE10 AE12 AE14 AE16 AE18 AE20 AE22 AE24 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF23 AF25 AG16 AG18 AG20 AG22 AG24 120 OHM_100Mhz C593 100nF 6.3V C514 10nF 10V C659 560pF 16V VDDALV Place near to SOC pins C669 100nF 6.3V C609 100nF 6.3V C560 100nF 6.3V C646 100nF 6.3V C680 100nF 6.3V C592 100nF 6.3V C630 100nF 6.3V C631 C527 560pF 100nF 16V 6.3V C550 560pF 16V C572 560pF 16V VDDALV1 VDDALV2 VDDALV3 VDDALV4 VDDALV5 VDDALV6 VDDALV7 VDDALV8 VDDALV9 VDDALV10 VDDALV11 VDDALV12 VDDALV13 VDDALV14 VDDALV15 VDDALV16 VDDALV17 VDDALV18 VDDALV19 VDDALV20 VDDALV21 VDDALV22 CVDD VDDAHV1 VDDAHV2 VDDAHV3 VDDAHV4 VDDAHV5 VDDAHV6 VDDAHV7 VDDAHV8 AH11 AH13 AH15 AH17 AH19 AH21 AH23 AH25 Place near to SOC pins VCC1V8 VDDAHV FB29 C614 NU TBD C692 NU TBD C608 NU TBD C615 NU TBD C640 NU TBD Place near to SOC pins C625 NU TBD C654 NU TBD C623 NU TBD C568 NU TBD C693 NU TBD C567 NU TBD C589 NU TBD C639 NU TBD C624 NU TBD C652 NU TBD C579 NU TBD C556 NU TBD C653 NU TBD 120 OHM_100Mhz CVDD Place near to SOC pins C588 NU TBD C597 NU TBD C679 NU TBD C575 NU TBD C596 NU TBD 3 of 26 A A VDDAHV VCC1V8 CVDD VDDAHV CVDD Project Place near to SOC pins Designed for TI by eInfochips K2E EVM C696 C647 C648 560pF 16V C621 560pF 16V C620 560pF 16V C670 560pF 16V 100nF 6.3V C695 100nF 6.3V C540 100nF 6.3V C598 100nF 6.3V C583 100nF 6.3V C561 100nF 6.3V 100uF 6.3V C745 TBD C74 TBD C96 TBD C756 TBD C757 TBD C185 TBD C184 TBD C75 TBD NU NU NU NU NU NU NU NU C683 TBD C660 TBD C603 TBD C606 TBD C604 TBD C632 TBD C605 TBD C563 TBD NU NU NU NU NU NU NU NU Title SoC_POWERB Size D Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 21 of 37 5 4 3 2 1 SOC GROUND U23E K2E_Processor D D K2E A1 A33 C5 C9 C14 C19 C23 C27 C29 D3 D7 D11 D17 D21 D25 D31 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 H8 H10 H12 H14 H16 H18 H20 H22 H24 H26 H28 J3 J7 J11 J13 J15 J17 J19 J21 J23 J25 J27 K10 K12 K14 K16 K18 K20 K22 K24 K28 L7 L9 L11 L13 L15 L17 L19 L21 L23 L25 L27 M1 M8 M10 M12 M14 M16 M18 M20 M22 M24 M26 M28 N2 N7 N9 N11 N13 N15 N17 N19 N21 N23 N25 C B A VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 N27 N32 P8 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 R1 R7 R9 R11 R13 R15 R17 R19 R21 R23 R25 R27 T2 T8 T10 T12 T14 T16 T18 T20 T22 T24 T26 T28 U3 U7 U9 U11 U13 U15 U17 U19 U21 U23 U25 U27 U32 V1 V8 V10 V12 V14 V16 V18 V20 V22 V24 V26 V28 W2 W9 W11 W13 W15 W17 W19 W21 W23 W25 W27 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Y22 Y24 Y26 Y28 AA4 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AA27 AA32 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AB26 AB28 AC7 AC9 AC11 AC13 U23S K2E_Processor K2E AC15 AC17 AC19 AC21 AC23 AC25 AC27 AD5 AD8 AD10 AD12 AD14 AD16 AD18 AD20 AD22 AD24 AD26 AD28 AE9 AE11 AE13 AE15 AE17 AE19 AE21 AE23 AE25 AE27 AE32 AF8 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG7 AG9 AG11 AG13 AG15 AG17 AG19 AG21 AG23 AG25 AG27 AH8 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 AJ4 AJ6 AJ9 AJ13 AJ16 AJ19 AJ21 AJ23 AJ29 AK3 AK6 AK9 AK12 AK15 AK18 AK21 AK24 AK27 AK30 AL4 AL7 AL10 AL13 AL16 AL19 AL22 AL25 AL28 AL31 AM1 AM3 AM6 AM9 AM12 AM15 AM18 AM21 AM24 AM27 AM30 AN1 AN2 AN4 AN7 AN10 AN13 AN16 AN19 AN22 AN25 AN28 AN31 AN33 C B 20 of 26 Project K2E EVM 5 of 26 Designed for TI by eInfochips Title SoC Ground Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 22 of 37 A 5 4 3 2 1 CLOCK SOURCE-- 1 1 R164 NU 0E 25M_CLK_REFP VCCPLLA1A 2 Y5 NU ABM3B-25.000MHZ-B2-T R167 NU 0E 11 12 8 9 VCC3V3_AUX CLK1_ELF Y4 25 MHz 1 VCC [11] OUT EN GND 3 R163 0E CLK1_REF_SEL IN 25M_CLK_REFP R108 [11,24] 2 CLK_RSTz [11] From MCU connect to this signal REFCLK1_PD# [27] [11,24,27] [11,24,27] [11,24,27] MCU_SPI0_CS0z MCU_SPI0_CLK MCU_SPI0_MISO MCU_SPI0_MOSI 41 6 R157 0E 0E 10uF C42 40 44 25V IN IN REFCLK1_PD# 43 CLK1_SYNC 42 4 5 3 2 IN IN OUT IN 1 47 0E 0E 37 38 13 18 19 24 27 30 31 34 VDD_Y0_Y1_1 VDD_Y0_Y1_2 VDD_Y2_Y3_1 VDD_Y2_Y3_2 VDD_Y4 VDD_Y5 VDD_Y6 VDD_Y7 10 7 39 VDD_PLL1 VDD_PLL2 Y0_P Y0_N SEC_REFP SEC_REFN Y1_P Y1_N PRI_REFP PRI_REFN Y2_P Y2_N CDCM6208V1RGZT ELF REF_SEL Y3_P Y3_N REG_CAP RESETN/PWR Y4_P Y4_N PDN Y5_P Y5_N SYNCN SCS/AD1/PIN3 SCL/PIN4 SDO/AD0/PIN2 SDI/SDA/PIN1 SI_MODE0 SI_MODE1 Y6_P Y6_N Y7_P Y7_N 14 15 156.25MHz Output OUT OUT XFICLKP XFICLKN [19] [19] OUT OUT USB_CLKP USB_CLKN OUT OUT 25M_SEC_REFP 25M_SEC_REFN OUT OUT SGMIICLKP SGMIICLKN [19] [19] OUT OUT CORECLKP CORECLKN [19] [19] OUT OUT NETCPCLKP NETCPCLKN 17 16 20 21 100.00MHz Output [13] [13] 23 22 26 25 29 28 32 33 35 36 [24] [24] 156.25MHz Output 100.00MHz Output 100.00MHz Output [19] [19] 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 R151 R138 STATUS0 STATUS1/PIN0 VDD_VCO 46 45 OUT TP26 VDD_SEC_REF PLL_LOCK1 DVDD STATUS0 outputs the PLL_LOCK signal STATUS1 the LOSS OF REFERENCE. 25M_CLK_REFP 25M_CLK_REFN 4 48 U18 [11] 100nF 25V VCC3V3_AUX_F2 D C58 NU 33pF 50V C35 VCCPLLA1B 25M_CLK_REFN VDD_PRI_REF C54 NU 33pF 50V VCCPLLA1B THERMAL_VIA_16 THERMAL_VIA_15 THERMAL_VIA_14 THERMAL_VIA_13 THERMAL_VIA_12 THERMAL_VIA_11 THERMAL_VIA_10 THERMAL_VIA_9 THERMAL_VIA_8 THERMAL_VIA_7 THERMAL_VIA_6 THERMAL_VIA_5 THERMAL_VIA_4 THERMAL_VIA_3 THERMAL_VIA_2 THERMAL_VIA_1 GND_EPAD D VCC3V3_AUX_F2 VCC3V3_AUX_F2 3 4 C C pull-up resistor VCC3V3_AUX CLK1_ELF R133 499E C33 C34 22nF CLK1_SYNC R136 10K REFCLK1_PD# R137 10K 25V 100pF 50V Synthesizer mode (high loop bandwidth) CDCM6208V1: With C1=100pF, R2=500, C2=22nF and Internal components R3=100, C3=242.5pF, fPFD=25MHz, and ICP=2.5mA: Loop bandwidth ~ (337kHz) Serial Interface Mode or Pin Mode Selection DESCRIPTION MCU_SI_MODE[1:0] VCC3V3_AUX 00 SPI MODE 01 I2C MODE VCC3V3_AUX_F2 (Default) 1 10 11 3 B6 2200pF 0.7A PIN MODE (NO SERIAL PROGRAMMING) 2 B C401 C430 C431 C432 C416 C411 C404 C406 C414 C420 C429 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V B RESEERVED VCC3V3_AUX VCCPLLA1A 1 3 2 B3 2200pF 0.7A C41 C49 100nF 25V 1uF 16V VCC3V3_AUX VCCPLLA1B Project K2E EVM A 1 3 2 B4 2200pF 0.7A C38 C47 100nF 25V 1uF 16V Title CLOCK SOURCE-- 1 Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 Designed for TI by eInfochips 2 Sheet 1 23 of 37 A 5 from AMC.0 [10] [10] 4 TCLKB_25MHz_P I N TCLKB_25MHz_N I N C53 C56 100nF 25V 100nF 25V 2 1 CLOCK SOURCE --2 TCLKD_P_C TCLKD_N_C R160 49.9E R171 49.9E R161 R155 D 3 5.6K VCC3V3_AUX 1% 3.16K 1% D VCCPLLA2A C59 VCC3V3_AUX_F1VCCPLLA2B 1uF 16V VCCPLLA2B VCC3V3_AUX_F1 VCC3V3_AUX_F1 from VCTCXO 25Mhz [23] [23] 25M_SEC_REFP 25M_SEC_REFN R178 R177 IN IN 11 12 0E 0E TCLKD_P_C TCLKD_N_C [11] CLK2_REF_SEL IN 8 9 R154 [11] From MCU connect to this signal [27] [11,23,27] [11,23,27] [11,23,27] CLK_RSTz IN REFCLK2_PD# IN MCU_SPI0_CS1z MCU_SPI0_CLK MCU_SPI0_MISO MCU_SPI0_MOSI 41 6 10uF 40 44 0E R112 [11,23] CLK2_ELF 0E C45 25V REFCLK2_PD# 43 CLK2_SYNC 42 4 5 3 2 IN IN OUT IN R150 R135 1 47 0E 0E 37 38 39 10 13 18 19 24 27 30 31 34 Y0_P Y0_N SEC_REFP SEC_REFN Y1_P Y1_N PRI_REFP PRI_REFN Y2_P Y2_N CDCM6208V1RGZT ELF REF_SEL Y3_P Y3_N REG_CAP RESETN/PWR Y4_P Y4_N PDN Y5_P Y5_N SYNCN SCS/AD1/PIN3 SCL/PIN4 SDO/AD0/PIN2 SDI/SDA/PIN1 SI_MODE0 SI_MODE1 Y6_P Y6_N Y7_P Y7_N 14 15 OUT OUT HYPER0_LINK_CLKP HYPER0_LINK_CLKN OUT OUT PCIE0CLKP PCIE0CLKN [19] [19] OUT OUT PCIE1CLKP PCIE1CLKN [19] [19] [19] [19] 17 16 20 21 23 22 26 25 29 28 32 33 35 36 OUT OUT SATA_CLKP SATA_CLKN OUT OUT RSV_CLKP RSV_CLKN OUT OUT TSREFCLKP TSREFCLKN [13] [13] OUT OUT DDR3_CLKP DDR3_CLKN [19] [19] 312.50MHz Output 100.00MHz Output 100.00MHz Output 100.00MHz Output 100.00MHz Output 100.00MHz Output 100.00MHz Output [16] [16] [29] [29] C 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 C STATUS0 STATUS1/PIN0 VDD_Y0_Y1_1 VDD_Y0_Y1_2 VDD_Y2_Y3_1 VDD_Y2_Y3_2 VDD_Y4 VDD_Y5 VDD_Y6 VDD_Y7 TP25 VDD_PLL1 VDD_PLL2 46 45 OUT THERMAL_VIA_16 THERMAL_VIA_15 THERMAL_VIA_14 THERMAL_VIA_13 THERMAL_VIA_12 THERMAL_VIA_11 THERMAL_VIA_10 THERMAL_VIA_9 THERMAL_VIA_8 THERMAL_VIA_7 THERMAL_VIA_6 THERMAL_VIA_5 THERMAL_VIA_4 THERMAL_VIA_3 THERMAL_VIA_2 THERMAL_VIA_1 GND_EPAD PLL_LOCK2 VDD_VCO 7 DVDD 49.9E 49.9E [11] VDD_SEC_REF U17 R601 R602 NU VDD_PRI_REF STATUS0 outputs the PLL_LOCK signal STATUS1 the LOSS OF REFERENCE. NU 48 VCC3V3_AUX_F1 pull-up resistor VCC3V3_AUX R113 REFCLK2_PD# CLK2_SYNC 10K R139 10K VCC3V3_AUX VCC3V3_AUX_F1 1 B 3 2 B5 2200pF 0.7A R134 402E C36 C44 22nF 25V Serial Interface Mode or Pin Mode Selection DESCRIPTION MCU_SI_MODE[1:0] VCC3V3_AUX C413 C403 C412 C427 C426 C425 C397 C419 C428 C405 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 100nF 25V 1 3 B1 2200pF 0.7A 220pF 50V Synthesizer mode (high loop bandwidth) CDCM6208V1: With C1=220pF, R2=400 , C2=22nF and Internal components R3=100O, C3=242.5pF, fPFD=25MHz, and ICP=2.5mA: Loop bandwidth ~ (274kHz) 00 SPI MODE 01 I2C MODE (Default) 2 CLK2_ELF B C415 PIN MODE (NO SERIAL PROGRAMMING) 10 VCC3V3_AUX 1 C48 100nF 25V 1uF 16V C40 C46 100nF 25V 1uF 16V 3 B2 2200pF 0.7A RESEERVED 2 11 VCCPLLA2A C39 VCCPLLA2B Project K2E EVM A Designed for TI by eInfochips Title CLOCK SOURCE-- 2 Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 24 of 37 A 5 4 3 2 1 DDR3 SODIMM SOC_DDR3A_EDQ[0..63] SOC_DDR3A_ECC[0..7] [14] SOC_DDR3A_EA[0..15] IN D [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] VCC3V3_AUX R251 4.7K 1% R247 4.7K 1% NU R252 4.7K 1% DIMM_SA0 DIMM_SA1 SOC_DDR3A_EBA_0 SOC_DDR3A_EBA_1 SOC_DDR3A_EBA_2 SOC_DDR3A_ECS_0# SOC_DDR3A_ECS_1# SOC_DDR3A_ECKP_0 SOC_DDR3A_ECKN_0 SOC_DDR3A_ECKP_1 SOC_DDR3A_ECKN_1 SOC_DDR3A_ECKE_0 SOC_DDR3A_ECKE_1 SOC_DDR3A_ECAS# SOC_DDR3A_ERAS# SOC_DDR3A_EWE# [18] [18] R253 4.7K 1% NU [14] [14] DIMM_SCL DIMM_SDA SOC_DDR3A_EODT_0 SOC_DDR3A_EODT_1 [14] IN IN IN IN IN IN IN IN IN [14] SOC_DDR3A_EDQSN_[0..7] IN GND [14] [14] 107 105 106 103 104 99 100 98 97 92 117 96 95 130 90 88 DIMM_SA0 DIMM_SA1 DIMM_SCL DIMM_SDA 119 108 91 127 129 111 113 112 114 87 89 125 122 121 197 201 202 200 126 128 IN IN [14] SOC_DDR3A_EDM_0 [14] SOC_DDR3A_EDM_1 [14] SOC_DDR3A_EDM_2 [14] SOC_DDR3A_EDM_3 [14] SOC_DDR3A_EDM_4 [14] SOC_DDR3A_EDM_5 [14] SOC_DDR3A_EDM_6 [14] SOC_DDR3A_EDM_7 SOC_DDR3A_EDQSP_[0..7] C IN IN IN IN IN IN IN IN IN IN IN IN IN IN SOC_DDR3A_EA0 SOC_DDR3A_EA1 SOC_DDR3A_EA2 SOC_DDR3A_EA3 SOC_DDR3A_EA4 SOC_DDR3A_EA5 SOC_DDR3A_EA6 SOC_DDR3A_EA7 SOC_DDR3A_EA8 SOC_DDR3A_EA9 SOC_DDR3A_EA10 SOC_DDR3A_EA11 SOC_DDR3A_EA12 SOC_DDR3A_EA13 SOC_DDR3A_EA14 SOC_DDR3A_EA15 11 28 44 59 140 157 172 189 SOC_DDR3A_EDQSP_8 I N SOC_DDR3A_EDQSN_8 I N SOC_DDR3A_EDQSP_0 SOC_DDR3A_EDQSP_1 SOC_DDR3A_EDQSP_2 SOC_DDR3A_EDQSP_3 SOC_DDR3A_EDQSP_4 SOC_DDR3A_EDQSP_5 SOC_DDR3A_EDQSP_6 SOC_DDR3A_EDQSP_7 SOC_DDR3A_EDQSN_0 SOC_DDR3A_EDQSN_1 SOC_DDR3A_EDQSN_2 SOC_DDR3A_EDQSN_3 SOC_DDR3A_EDQSN_4 SOC_DDR3A_EDQSN_5 SOC_DDR3A_EDQSN_6 SOC_DDR3A_EDQSN_7 12 27 45 62 141 156 173 188 10 25 43 60 139 154 171 186 SOC_DDR3A_EDQSP_8 SOC_DDR3A_EDQSN_8 77 75 76 SOC_DDR3A_EDM_8 I N [14] 120 118 DIMM1A 2013289-1_DDR3-SODIMM_204P 5 A0 DQ0 7 A1 DQ1 13 A2 DQ2 15 A3 DQ3 4 A4 DQ4 6 A5 DQ5 16 A6 DQ6 18 A7 DQ7 19 A8 DQ8 21 A9 DQ9 31 A10/AP DQ10 33 A11 DQ11 22 A12/BC DQ12 24 A13 DQ13 34 A14 DQ14 36 A15 DQ15 37 DQ16 39 BA0 DQ17 49 BA1 DQ18 51 BA2 DQ19 40 CS0 DQ20 42 CS1 DQ21 48 CK0 DQ22 50 CK0 DQ23 55 CK1 DQ24 57 CK1 DQ25 63 CKE0 DQ26 65 CKE1 DQ27 54 CAS DQ28 56 RAS DQ29 66 WE DQ30 68 SA0 DQ31 133 SA1 DQ32 135 SCL DQ33 145 SDA DQ34 147 DQ35 134 ODT0 DQ36 136 ODT1 DQ37 142 DQ38 144 DM0 DQ39 151 DM1 DQ40 153 DM2 DQ41 159 DM3 DQ42 161 DM4 DQ43 148 DM5 DQ44 150 DM6 DQ45 160 DM7 DQ46 162 DQ47 165 DQS0 DQ48 167 DQS1 DQ49 177 DQS2 DQ50 179 DQS3 DQ51 166 DQS4 DQ52 168 DQS5 DQ53 174 DQS6 DQ54 176 DQS7 DQ55 183 DQS0 DQ56 185 DQS1 DQ57 191 DQS2 DQ58 193 DQS3 DQ59 180 DQS4 DQ60 182 DQS5 DQ61 192 DQS6 DQ62 194 DQS7 DQ63 DQS8 DQS8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM8 CS2 CS3 69 71 81 83 72 74 80 82 VCC1V5 DIMM1B 2013289-1_DDR3-SODIMM_204P [14] 85 86 93 94 101 102 109 110 115 116 123 124 131 132 [14] SOC_DDR3A_EDQ4 SOC_DDR3A_EDQ0 SOC_DDR3A_EDQ5 SOC_DDR3A_EDQ1 SOC_DDR3A_EDQ6 SOC_DDR3A_EDQ2 SOC_DDR3A_EDQ3 SOC_DDR3A_EDQ7 SOC_DDR3A_EDQ14 SOC_DDR3A_EDQ13 SOC_DDR3A_EDQ8 SOC_DDR3A_EDQ10 SOC_DDR3A_EDQ12 SOC_DDR3A_EDQ15 SOC_DDR3A_EDQ9 SOC_DDR3A_EDQ11 SOC_DDR3A_EDQ17 SOC_DDR3A_EDQ16 SOC_DDR3A_EDQ22 SOC_DDR3A_EDQ23 SOC_DDR3A_EDQ19 SOC_DDR3A_EDQ20 SOC_DDR3A_EDQ21 SOC_DDR3A_EDQ18 SOC_DDR3A_EDQ30 SOC_DDR3A_EDQ28 SOC_DDR3A_EDQ26 SOC_DDR3A_EDQ25 SOC_DDR3A_EDQ31 SOC_DDR3A_EDQ29 SOC_DDR3A_EDQ27 SOC_DDR3A_EDQ24 SOC_DDR3A_EDQ33 SOC_DDR3A_EDQ34 SOC_DDR3A_EDQ39 SOC_DDR3A_EDQ37 SOC_DDR3A_EDQ36 SOC_DDR3A_EDQ35 SOC_DDR3A_EDQ32 SOC_DDR3A_EDQ38 SOC_DDR3A_EDQ46 SOC_DDR3A_EDQ45 SOC_DDR3A_EDQ42 SOC_DDR3A_EDQ41 SOC_DDR3A_EDQ43 SOC_DDR3A_EDQ47 SOC_DDR3A_EDQ40 SOC_DDR3A_EDQ44 SOC_DDR3A_EDQ48 SOC_DDR3A_EDQ49 SOC_DDR3A_EDQ50 SOC_DDR3A_EDQ51 SOC_DDR3A_EDQ52 SOC_DDR3A_EDQ53 SOC_DDR3A_EDQ54 SOC_DDR3A_EDQ55 SOC_DDR3A_EDQ63 SOC_DDR3A_EDQ61 SOC_DDR3A_EDQ60 SOC_DDR3A_EDQ59 SOC_DDR3A_EDQ56 SOC_DDR3A_EDQ62 SOC_DDR3A_EDQ58 SOC_DDR3A_EDQ57 VCC3V3_AUX C789 2.2uF 10V [14] VCC0V75REF C790 100nF 25V 199 198 30 SOC_DDR3A_EMRESETN 1 84 VCC0V75REF C120 2.2uF 10V C57 100nF 25V C531 2.2uF 10V C530 100nF 25V 2 3 8 9 14 17 20 23 26 29 32 35 38 41 46 VCC1V5 VDDSPD EVENT RESET VREF_DQ VREF_CA VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 47 52 53 58 61 64 67 70 73 78 79 137 138 143 146 149 152 155 158 163 164 169 170 175 178 181 184 187 190 195 196 C600 22uF 10V C636 22uF 10V C682 22uF 10V C723 22uF 10V D VCC0V75 VTT1 VTT2 PTH_1 PTH_2 203 204 G1 G2 C VCC0V75 C574 22uF 10V SOC_DDR3A_ECC3 SOC_DDR3A_ECC2 SOC_DDR3A_ECC0 SOC_DDR3A_ECC7 SOC_DDR3A_ECC1 SOC_DDR3A_ECC4 SOC_DDR3A_ECC6 SOC_DDR3A_ECC5 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 C805 100nF 25V VCC0V75 C803 100nF 25V C804 100nF 25V C808 1uF 16V C806 1uF 16V C807 1uF 16V VCC1V5 C124 1uF 16V C130 1uF 16V C140 1uF 16V C147 1uF 16V C155 1uF 16V C125 1uF 16V DM16 SODIMM Module B B LCD1 NHD-C12832A1Z-FSB-FBW-3V3 VCC3V3_MP VCC3_LCD VCC3V3_AUX VCC3_LCDBK R310 R306 100E H4 H3 H2 H1 VCC3_LCDBK R308 6.98K K C304 4.7uF 25V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 R1 REF 3 220E R309 10K A Q10 APL431LBAI-TRG 2 1 C301 C310 1uF 1uF 16V 16V R2 C305 470nF 10V C306 470nF 10V A C307 470nF 10V VO = 1.24v(1+R1/R2)+0.15uA*R1 C302 1uF 16V C308 470nF 10V 3.018V =1.24 (1+10k/6.98k)+0.15u*10k C309 470nF 10V IN IN IN IN IN MCU_SPI1_CS0z [27] LCD_RSTz [27] LCD_A0 [27] MCU_SPI1_CLK [27] MCU_SPI1_MOSI [27] SPI1 CS0 LCD control Project K2E EVM Designed for TI by eInfochips Title DDR3- SODIMM AND LCD VCC3_LCD Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 25 of 37 A 5 4 3 2 ETHERNET PHY 1 AVDD1V8_1 AVCC3V3_1 AVDD1V8_1 AVDD1V8_1 PHY1_MDI0_N 1A 1 TX1+ VCC2V5 DVDD1V0_1 R568 R559 R562 R564 R571 R572 31 32 TP89 TP90 VCC1V8 10 6 42 DVDD_1 DVDD_2 VDDO_SEL 39 40 37 41 36 20 25 11 49 52 VDDO_1 VDDO_2 VDDO_3 PHY1_MDI2_P 88E1514 2 1 5 4 SIN_N SIN_P SOUT_N SOUT_P C816 C817 LED[0] LED[1] LED[2]/INTn XTAL_IN 1 33 15 10K 6A D C818 C846 C847 C855 C850 TX48 100nF 100nF 100nF 10uF 25V 25V 25V 25V 8A 75R 9A C832 25V 10nF VCC2V5 C831 G PHY1_LED_0 R264 PHY1_LED_1 R248 1uF 16V VCC3V3_AUX AVCC3V3_1 10A 1000pF 2kV SHIELD GND 13A 11A 1nF MH1 MH2 SH1 SH2 FB35 O 100E12A 100E14A 120_100MHz C835 C836 C259 C274 C837 100nF 25V 100nF 100nF 100nF 10uF 25V 25V 25V 25V GND_LAN PORT--1 [11] CONFIGURATION MAPPING C885 C886 C888 C887 100nF 100nF 100nF 10uF 25V 25V 25V 25V VCC3V3_AUX BIT 1,0 PHY1_LED_1 0E R563 NU 0E 30 R576 4.99K 1% 29 TP88 RSET TSTPT VSS XTAL_OUT 57 3 C845 33pF 50V PHY1_MDI3_P [12] [12] [12] [12] PIN 2 4 PHY1_INT# OUT R558 Y8 ABM3B-25.000MHZ-B2-T SOC_SGMII0_TXN SOC_SGMII0_TXP SOC_SGMII0_RXN SOC_SGMII0_RXP IN IN OUT OUT PHY1_LED_0 PHY1_LED_1 14 13 12 CONFIG C C833 CLK125 34 4.7uF 1uF 25V 16V VCC2V5 HSDAC_N HSDAC_P 9 10uF 25V DVDD1V0_1 TX35 PHY1_MDI3_N 7A R570 0E NU 100nF 25V 100nF 25V R557 TP87 4A 7 TX4+ PHY1_MDI3_N PHY1_MDI3_P PHY1_MDI2_N PHY1_MDI2_P PHY1_MDI1_N PHY1_MDI1_P PHY1_MDI0_N PHY1_MDI0_P 17 18 21 22 23 24 27 28 R579 1% NU 1M 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 10uF 25V 25V 25V 25V 25V 25V 25V 25V 25V TX26 4 TX3+ 100nF 25V TX_CLK TX_CTRL TXD[3] TXD[2] TXD[1] TXD[0] C839 C840 C834 C819 C271 C272 C273 C265 C827 C269 C841 C838 PHY1_MDI2_N 5A MDI[3]_N MDI[3]_P MDI[2]_N MDI[2]_P MDI[1]_N MDI[1]_P MDI[0]_N MDI[0]_P RX_CLK RX_CTRL RXD[3] RXD[2] RXD[1] RXD[0] 53 56 55 54 51 50 0E 0E 0E 0E 0E 0E PHY1_MDI1_P VCC1V8_TCT MDC MDIO 46 43 48 47 45 44 2A 3 TX2+ RESETn 7 8 PHY1_MDC_2V5 I N PHY_MDIO_2V5 BI PHY1_MDI0_P TX12 PHY1_MDI1_N 3A AVDD18_OUT DVDD_OUT 16 [12] [10,12,26,29] DVDD1V0_1 220nF 10V REGCAP1 REGCAP2 R652 13.7K REG_IN D AVDD33_1 AVDD33_2 4.7K 1%PHY_RSTz_2V5 R651 AVDDC18 IN AVDD18_1 AVDD18_2 AVDD18_3 AVDD18_4 PHY_RSTz 35 U77 [27] 3 19 26 38 C848 1 J9A XMH-TRJG17020AENL VSS 00 LED[0] 01 LED[1] 10 LED[2] C844 33pF 50V C VCC1V8 Unused VDDO VCC1V8_TCT FB34 NU 120_100MHz FB8 120_100MHz 11 C815 NU 100nF 25V PHY ADDRESS :- 0X0 ETHERNET PHY 2 AVCC3V3_2 AVDD1V8_2 VCC2V5 DVDD1V0_2 [12] [10,12,26,29] 16 7 8 PHY2_MDC_2V5 I N PHY_MDIO_2V5 BI 46 43 48 47 45 44 R514 R500 R507 R509 R515 R530 VCC1V8 0E 0E 0E 0E 0E 0E TP83 TP85 53 56 55 54 51 50 31 32 TP77 9 CONFIG 1 1 CONFIG 1 0 PHY Address[0] = 0 VDDO_LEVEL = 2.5V CONFIG 0 1 PHY Address[0] = 1 VDDO_LEVEL = 2.5V C212 C211 C734 C204 C209 C773 C774 C759 C208 C748 C778 C776 6 42 VDDO_SEL 10 11 49 52 J9B XMH-TRJG17020AENL MDI[3]_N MDI[3]_P MDI[2]_N MDI[2]_P MDI[1]_N MDI[1]_P MDI[0]_N MDI[0]_P MDC MDIO 4.7uF 1uF 25V 16V DVDD1V0_2 C786 C787 C735 C794 C792 TX12 100nF 100nF 100nF 10uF 25V 25V 25V 25V PHY2_MDI3_N PHY2_MDI3_P PHY2_MDI2_N PHY2_MDI2_P PHY2_MDI1_N PHY2_MDI1_P PHY2_MDI0_N PHY2_MDI0_P 17 18 21 22 23 24 27 28 1uF 16V B TX26 PHY2_MDI1_P4B VCC3V3_AUX FB32 120_100MHz PHY2_MDI2_N5B 4 TX3+ TX35 PHY2_MDI2_P6B VCC1V8_TCT PHY2_MDI3_N7B 7 TX4+ 88E1514 SIN_N SIN_P SOUT_N SOUT_P TX_CLK TX_CTRL TXD[3] TXD[2] TXD[1] TXD[0] 2 1 5 4 C732 C733 100nF 25V 100nF 25V IN IN OUT OUT SOC_SGMII1_TXN SOC_SGMII1_TXP SOC_SGMII1_RXN SOC_SGMII1_RXP [12] [12] [12] [12] LED[0] LED[1] LED[2]/INTn 100nF 25V PHY2_LED_0 PHY2_LED_1 14 13 12 OUT CLK125 10K PHY2_INT# SH3 SH4 C809 VCC2V5 G PHY2_LED_0 R265 PHY2_LED_1 R249 [11] 1000pF 2kV SHIELD GND 13B 11B 1nF C762 C763 C175 C177 C188 C195 C210 C764 100nF 25V 100nF 100nF 100nF 100nF 100nF 100nF 10uF 25V 25V 25V 25V 25V 25V 25V VCC2V5 75R 9B C810 25V 10nF AVCC3V3_2 TX48 PHY2_MDI3_P8B R556 0E NU C811 HSDAC_N HSDAC_P 10uF 25V 1 TX1+ PHY2_MDI1_N3B O 10B C889 C890 C892 C891 GND_LAN 100E12B 100E14B 100nF 100nF 100nF 10uF 25V 25V 25V 25V PORT--2 VCC3V3_AUX VCC3V3_AUX XTAL_IN 1 CONFIG 33 RSET TSTPT XTAL_OUT 15 R498 30 R551 29 0E PHY2_LED_0 4.99K 1% Project TP79 K2E EVM VSS Y7 ABM3B-25.000MHZ-B2-T Designed for TI by eInfochips Title 57 3 C784 33pF 50V AVDD1V8_2 R508 NU 0E 34 4 PHY Address[0] = 0 VDDO_LEVEL = 3.3V PHY Address[0] = 1 VDDO_LEVEL = 3.3V 3 TX2+ 2 A 0 RESETn RX_CLK RX_CTRL RXD[3] RXD[2] RXD[1] RXD[0] GND_LAN Assignment PHY2_MDI0_P2B R496 NU 0 Value PHY2_MDI0_N1B R553 1% 1M CONFIG CONFIG Bit0 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 10uF 25V 25V 25V 25V 25V 25V 25V 25V 25V VDDO_1 VDDO_2 VDDO_3 39 40 37 41 REGCAP1 REGCAP2 20 25 36 REG_IN DVDD1V0_2 CONFIG Bit1 220nF 10V AVDD18_OUT DVDD_OUT PHY_RSTz_2V5 AVDD33_1 AVDD33_2 3 19 26 38 AVDDC18 B AVDD18_1 AVDD18_2 AVDD18_3 AVDD18_4 U73 35 C788 DVDD_1 DVDD_2 AVDD1V8_2 PIN C783 33pF 50V SGMII ETHERNET PHY Size C PHY ADDRESS :- 0X1 Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 26 of 37 A 5 4 3 2 1 MMC_GAPU BMC INTERFACE VCC3V3_MP SMB_SCL_IPMBL SMB_SDA_IPMBL R5 R8 33K 33K MMC_PS_N0 R10 10K R289 3K 1% R287 3K 1% R285 3K 1% R288 0E NU R286 0E NU R284 0E NU MMC_GA0 1% 1% MMC_GA1 MMC_GA2 U1 LM3S2D93-IQC80_0 From SOC UART0 TX MCU_PA0_U0RX BMC UART0 BMC SPI0 I2C1 ICDI BMC SPI0 CS1~CS4 MCU_PA1_U0TX MCU_SPI0_CLK MCU_SPI0_CS0z MCU_SPI0_MISO MCU_SPI0_MOSI MCU_EXP_SCL MCU_EXP_SDA OUT OUT OUT IN OUT OUT BI [28] [28] [28] [28] [24] [31] [11] [11] MCU_JTAG_TCK MCU_JTAG_TMS MCU_JTAG_TDI MCU_JTAG_TDO MCU_SPI0_CS1z LM10011_EN MCU_SPI0_CS3z MCU_SPI0_CS4z IN BI IN OUT OUT OUT OUT OUT [25] [25] MCU_SPI1_CLK MCU_SPI1_CS0z OUT OUT [25] [18] [18] [28] [26] MCU_SPI1_MOSI SOC_I2C_EN PW_SEQ_I2C_EN PW_SEQ_RSTz PHY_RSTz OUT OUT OUT OUT OUT SPI1 to LCD R40 R39 R290 R319 MMC_ENABLE_N IN OUT [18] NOR_WPz R318 PCIECLK_MCU_PD OUT R312 OUT PCIECLK_OE OUT [28,31] PMBUS_CTL [11,28,31] PMBUS_ALERT I N [11] SPI_GPIO_RESET OUT [19] [19] GPIO to PMBUS 80 79 78 77 25 24 23 22 MCU_SPI0_CS3z MCU_SPI0_CS4z 74 75 95 96 6 5 2 1 0E 19 18 17 16 41 40 37 36 0E [10] NOR FLASH 0E 0E 0E 0E SPI_GPIO_RESET MCU_BOOTSELECT 14 87 39 ATTENTIONz POWER_RESETz RESET [15,36] C TRGRSTZ IN MCU_RESETz VBAT 64 OSC1 32.768KHz 4 2 VCC GND C10 OUT OE 3 1 MCUXOSC0_R R22 MCUXOSC0 22E VBAT Y1 100nF 25V C17 50V 10pF 52 53 MCUOSC0 48 49 MCUOSC1 16MHz PA0/U0Rx PA1/U0Tx PA2/SSI0CLK PA3/SSI0Fss PA4/SSI0Rx PA5/SSI0Tx PA6 PA7 PB0 PB1 PB2/I2C0SCL PB3/I2C0SDA PB4 PB5 PB6 PB7 PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 LM3S2D93-IQC80 LQFP 100P PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 R28 AMC MMC 10 MAIN_POWER_START MAIN_POWER_START OUT 11 MAIN_POWER_GOOD IN MAIN_POWER_GOOD 12 SOC_POWER_START OUT SOC_POWER_START 13 SOC_POWER_GOOD IN SOC_POWER_GOOD 97 OUT EXP_GPIO_EN [11] 98 99 VCC3V3_MP_ALT_DET 100 OUT LCD_RSTz [25] 47 61 R16 0E MCU_SPI0_CS5z 60 MCU_SPI0_CS6z 59 SPI_GPIO_INT0 58 SPI_GPIO_INT1 46 SPI_GPIO_INT2 43 SPI_GPIO_INT3 42 DIP_SW_B0 86 DIP_SW_B1 85 DIP_SW_B2 84 DIP_SW_B3 83 76 MMC_PS_N0 63 62 MMC_RED_LED 15 MMC_BLUE_LED OUT OUT OUT OUT IN IN IN IN [28] [28] [28] [28] VCC3V3_MP_ALT VCC3V3_MP R292 10K LCD Control DSP_PMBUS_EN [11,19] LCD_A0 [25] MCU_SPI0_CS5z [11] MCU_SPI0_CS6z [11] SPI_GPIO_INT0 [11] SPI_GPIO_INT1 [11] SPI_GPIO_INT2 [11] SPI_GPIO_INT3 [11] VCC3V3_MP_ALT_DET MCU_RESET_SWz R291 0E NU BMC SPI0 [28] 10K 51 9 21 45 57 69 82 94 54 33 D2 1 VCC3V3_MP VCC3V3_MP_ALT C303 D1 100nF 25V 3 IN PCIECLK_MUX_SEL MMC_PS_N0 [10] C313 2.2uF 10V C300 100nF 25V 6 B Y C GND 4 C297 100nF 25V MCU_RESETz 2 [19] CN1(1-2) RST XOSC0 XOSC1 WAKE OSC0 OSC1 VBAT 50 MCU_WAKEz 55 VBAT STC02SYAN CN1 NC_2 NC_1 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 GNDA GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 LDO VDDC_1 VDDC_2 U42 SN74LVC2G157DCUT 8 A VCC 7 B G 6 Y A/B 5 GND Y VCC3V3_MP 71 70 R315 R314 R316 R313 [28] C319 C325 C339 C337 C323 10nF 25V 10nF 25V 100nF 25V 100nF 25V 2.2uF 10V 10K 10K 10K 10K SW1 SDA04H1SBD ON 8 1 2 7 3 6 4 5 DIP_SW_B0 DIP_SW_B1 DIP_SW_B2 DIP_SW_B3 R296 R295 R294 R293 100E 100E 100E 100E Budget 150mA [Note]1.D3, D5 should be placed on edge of PCB. 2.D4, D6 should be placed inside of PCB. D5 2 VCC3V3_AUX 1 R89 120E 5%_1/16W R 7 38 88 MCU_PA0_U0RX MCU_UART0_Detect VCC3V3_MP 73 8 20 32 44 56 68 81 93 C IN 1 2 3 HIB VDDA 1 2 3 4 [28] MCU_U0RX IN CP2105_MCU_U0RX I N [18] R9 10K KP-1608EC 3 4 Close to BMC MCU_SRSTN_R VCC3V3_MP R299 U36 4.7K 1% SN74LVC1G11DCKR 5 VCC 1 A R307 10K SOC Bootmode GPIO OUT IN D I2C0 VCC3V3_MP 100nF 25V VCC3V3_MP_AMC 1 [10] [10] BMC UART1 TSW-103-23-T-S 3 2 TP1 SMB_SCL_IPMBL SMB_SDA_IPMBL MMC_GA0 [10] MMC_GA1 [10] MMC_GA2 [10] [18] VCC3V3_MP C312 B OUT BI IN IN IN SOC_UART0_TXD_3V3 IN VCC3V3_MP Power for BMC Close to BMC MMC_GAPU 0E C16 50V 10pF VCC3V3_MP PMEG1020EH 2A MCU_U1RXR7 MCU_U1TX PJ0 PJ1 PJ2 NC_3 2 66 67 72 65 92 91 90 89 [11,19] C318 C338 C298 10nF 25V 100nF 25V 2.2uF 10V SOC_RESETSTATZ R75 IN 510E1 1% 2 [18,28] [11,23,24] [23] [11,23,24] [11,23,24] [18] [18] D 26 27 28 29 30 31 34 35 Q6 2N3904 0.2A Note:LED Color is RED VCC3V3_AUX D6 2 PMEG1020EH 2A 1 R377 B 120E G 3 KP-1608MGC PLLLOCK_LED PLLLOCK_LED R365 IN 510E1 1% 2 [11] Q14 2N3904 0.2A Note:LED Color is GREEN VCC3V3_MP R38 10K CN4 D3 VCC3V3_MP 1 MCU_BOOTSELECT TSW-102-23-T-S 2 R32 49.9E R KPA-1606EC 3 1 2 MMC_RED_LED R27 510E1 1% 2 CN4(1-2) STC02SYAN Q3 2N3904 0.2A Note:LED Color is RED VCC3V3_MP D4 1 2 R47 120E R VCC3V3_MP VCC3V3_MP MMC_BLUE_LED R211 ATTENTIONz 100E BMC_RESET R179 10K R181 100E STC02SYAN POWER_RESETz 3 4 C60 25V 10nF R297 Note:PUSH Buttons Color is BLACK Note:PUSH Buttons Color is RED 1 2 3 100E MCU_RESET_SWz RST_BMC1 PTS635SL25SMTR LFS TSW-103-23-T-S C299 25V 10nF <Characteristic> EVQ-PF304R Q11 2N3904 0.2A Project K2E EVM Size Note:PUSH Buttons Color is BLACK 4 Designed for TI by eInfochips Title C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 Note:LED Color is BLUE BMC 1 EVQ-PF206K POWER_RESETz MCU_WAKEz 2 RST_PWR1 2 2 SH1 SH2 C102 25V 10nF 1 1 RST_ATTN1 510E1 1% R298 10K CN6 A R328 2 R205 10K CN6(2-3) WAKE Power RESET KPA-1606QBC-D 3 VCC3V3_MP Attention 3 2 Sheet 1 27 of 37 A 5 4 3 2 1 BMC UART BMC JTAG VCC3V3_MP VCC3V3_MP D VCC3V3_MP R305 10K [27] MCU_JTAG_TDO [27] MCU_JTAG_TDI MCU_SRSTN_R 1 3 5 7 9 0E BSC_JTAG_TMS MCU_JTAG_TMS BI [27] [27] R311 CN3 FTSH-105-01-F-DV-K-P-TR 2 R304 4 R303 6 R302 8 R301 10 R300 VCC3V3_MP D BSC_JTAG_TMS BSC_JTAG_TCK BSC_JTAG_TDO BSC_JTAG_TDI BSC_JTAG_SRSTN 22E 22E 22E 22E 22E R322 4.7K R326 4.7K BSC_JTAG_TDO IN U47 MAX3221ECPWR 12 16 BSC_JTAG_TDI OUT BSC_JTAG_SRSTN OUT 10 pos (50 mil pitch) connector [27] [18,27] MCU_U0RX MCU_PA1_U0TX IN OUT R331 R333 0E 0E MCU_UART_RX 9 MCU_UART_TX 11 R332 C328 100nF 25V 2 4.7K 4 VCC3V3_MP C324 100nF 25V 3 C11 U3 SN74LVC2G125DCUR 8 VCC 2 C12 10pF 50V R24 10K 5 1 7 1A 1Y 2A 2Y 6 R20 0E OUT MCU_JTAG_TCK C340 1uF 16V 100nF 25V VCC3V3_MP 15 VCC R360 4.7K 1% ROUT 8 RIN DIN DOUT C1+ C329 100nF 25V 7 V- MCU_UART0_Detect OUT C344 100nF 25V 1 14 EN# GND INVALID# RS232_TX 5 22-23-2041 COM2 4 3 2 1 6 C2- V+ 13 [27] C2+ C1- RS232_RX [27] 3 GND BSC_JTAG_TCK 10 100nF 25V FORCEON FORCEOFF# C336 1OE# 2OE# C 4 C VCC3V3_MP Q1 MCP9700AT-E/LT 4 VDD GND C315 VCC3V3_MP FB1 2 100nF 25V Power Sequencing (UCD9090) SOC_TEMP1 3 1 5 VOUT NC1 NC2 Close to SoC 220_100MHz C1 C2 C8 C9 100nF 25V 4.7uF 25V 100nF 25V 4.7uF 25V VCC0V75 VCC1V8 VCC3V3_AUX VCC0V85 VPP1V8 VCC1V5 CVDD1 VCC5V CVDD B R62 R63 3K 0E 0E U4 CVDD_MON VCC0V85_MON VCC5_MON VCC3_AUX_MON CVDD1_MON VCC1V8_MON VCC1V5_MON VCC0V75_MON VPP1V8_MON SOC_TEMP1 POWER DETECT VCC3V3_MP R321 R320 2K R335 R334 2K [18,19] [18,19] PW_SEQ_SCL I N PW_SEQ_SDA BI Slave I2C Address = 0x68 ( Internal ADDR[7:5] = 0b110 [27] [27] MAIN_POWER_START SOC_POWER_START IN IN PMBUS_CLK PMBUS_DAT R36 0E R30 0E R33 90.9K R325 90.9K PW_SEQ_RSTz R324 NU 0E 0E 0E MON1 MON2 MON3 MON4 MON5 MON6 MON7 MON8 MON9 MON10 MON11 2.2K 2.2K R59 0E R58 0E PMBUS_ALERT PMBUS_CTL R23 R19 1 2 38 39 40 41 42 45 46 48 37 TCK/GPIO18 TDO/GPIO19 TDI/GPIO20 TMS/GPIO21 TRST GPIO1 GPIO2 GPIO3 GPIO4 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 UCD9090RGZT 8 9 19 20 44 43 MAIN_POWER_START_R 22 SOC_POWER_START_R 23 PMBUS_CLK PMBUS_DATA PMBUS_ALERT PMBUS_CNTRL PMBUS_ADDR0 PMBUS_ADDR1 FPWM1/GPIO5 FPWM2/GPIO6 FPWM3/GPIO7 FPWM4/GPIO8 FPWM5/GPIO9 FPWM6/GPIO10 FPWM7/GPIO11 FPWM8/GPIO12 PWM1/GPI1 PWM2/GPI2 PMBUS1 1 2 3 4 5 PMBUS_CLK PMBUS_DAT PMBUS_ALERT PMBUS_CTL OUT BI OUT OUT 32 PMBUS_CLK [31] PMBUS_DAT [31] PMBUS_ALERT [11,27,31] PMBUS_CTL [27,31] AVSS1 AVSS2 A 10K 10K 10K MAIN_POWER_GOOD THERMAL_VIA13 THERMAL_VIA14 THERMAL_VIA15 THERMAL_VIA16 THERMAL_VIA17 THERMAL_VIA18 THERMAL_VIA19 THERMAL_VIA20 THERMAL_VIA21 THERMAL_VIA22 THERMAL_VIA23 THERMAL_VIA24 THERMAL_VIA25 27 28 29 30 31 JTAG_TCK JTAG_TDO TP5 JTAG_TDI TP6 JTAG_TMS TP2 TP3 TP4 R659 10K POWER ENABLE B 4 5 6 7 18 21 24 25 26 R61 R337 R60 R336 R43 R26 R17 R11 R12 0E 0E 0E 0E 0E 0E 0E 0E 0E 10 11 12 13 14 15 16 17 R57 R56 R55 0E 0E 0E 3 62 63 64 65 66 67 68 69 70 71 72 73 74 OUT OUT OUT OUT OUT OUT OUT OUT OUT 9090FPWM4 R50 33E 1% 9090FPWM6 9090FPWM7 9090FPWM8 R338 NU 10K C345 10nF R658 25V CVDD_EN [31] VCC0V85_EN [31] VCC5V_EN [30] VCC3V3_AUX_EN [30,31] CVDD1_EN [31] VCC1V8_EN [31] MAIN_POWER_GOOD [27] SOC_POWER_GOOD [27] VCC0V75_EN [30] OUT OUT OUT USB_VBUS_EN [13] VCC1V5_EN [30] VCC3V3_EN [30] OUT FAN_PWM IN PW_SEQ_RSTz VCC3V3_MP PMBus Address Pins PMBus Address OPEN 11 10 9 8 7 6 5 4 SHORT [30] [27] 10K PMBus RESISTANCE (K ohm) -200 154 118 90.9 69.8 53.6 41.2 31.6 -- Project K2E EVM 36 47 PMBus Head THERMAL_PAD THERMAL_VIA1 THERMAL_VIA2 THERMAL_VIA3 THERMAL_VIA4 THERMAL_VIA5 THERMAL_VIA6 THERMAL_VIA7 THERMAL_VIA8 THERMAL_VIA9 THERMAL_VIA10 THERMAL_VIA11 THERMAL_VIA12 DVSS RESET 49 50 51 52 53 54 55 56 57 58 59 60 61 R13 R14 R15 35 R18 1.3K 0E 34 R21 0E C327 C326 10nF 100nF 25V 25V BPCAP R323 R25 0E 33 R29 0E V33A R41 0E V33D R49 VCC3V3_MP BPCAP VCC3V3_MP CN5 9090FPWM4 9090FPWM6 9090FPWM7 9090FPWM8 MAIN_POWER_START_R SOC_POWER_START_R GND_3 TSW-105-23-T-S FB3 120_100MHz 1 2 3 4 5 6 NU TSW-106-23-T-S GND_3 Title MCU_MISC Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 Designed for TI by eInfochips 2 Sheet 1 28 of 37 A 5 4 3 Note : J4 connector close to AMC Interface. Note : USB_D+ USB_DUSB_ID USB_VBUS GNDF1 GNDF2 GNDF3 GNDF4 GNDF5 GNDF6 GNDF7 GNDF8 GNDF9 GNDF10 USB_RXUSB_RX+ USB_TXUSB_TX+ USB_CLKUSB_CLK+ USB_RESREF USB_DRVVBUS PWRA1 PWRB1 PWRA2 PWRB2 GNDG1 GNDG2 GNDG3 GNDG4 GNDG5 GNDG6 GNDG7 GNDG8 GNDG9 GNDG10 PS# SDA MP SCL GNDH1 GNDH2 GNDH3 GNDH4 GNDH5 GNDH6 GNDH7 GNDH8 GNDH9 GNDH10 TCK TDO TDI TMS REF0CLKP REF0CLKN REF1CLKP REF1CLKN G9 H9 G10 H10 [12] [12] [12] [12] Tx1_3+ Tx1_3Rx1_3+ Rx1_3- A7 B7 A8 B8 HyperLink0_TXP2 IN HyperLink0_TXN2 IN HyperLink0_RXP2 HyperLink0_RXN2 OUT OUT HyperLink0_TXP2 HyperLink0_TXN2 HyperLink0_RXP2 HyperLink0_RXN2 [12] [12] [12] [12] A9 B9 A10 B10 HyperLink0_TXP3 IN HyperLink0_TXN3 IN HyperLink0_RXP3 HyperLink0_RXN3 OUT OUT HyperLink0_TXP3 HyperLink0_TXN3 HyperLink0_RXP3 HyperLink0_RXN3 [12] [12] [12] [12] E5 F5 E6 F6 GB1 GB2 GB3 GB4 GB5 GB6 GB7 GB8 GB9 GB10 E7 F7 E8 F8 E9 F9 E10 F10 C3 D3 C4 D4 HyperLink0_RXFLCLK IN HyperLink0_RXFLDAT HyperLink0_TXFLCLK I N OUT HyperLink0_TXFLDAT OUT HyperLink0_RXFLCLK HyperLink0_RXFLDAT HyperLink0_TXFLCLK HyperLink0_TXFLDAT C5 D5 C6 D6 HyperLink0_RXPMCLK OUT HyperLink0_RXPMDAT OUT HyperLink0_TXPMCLK HyperLink0_TXPMDAT I N IN HyperLink0_RXPMCLK HyperLink0_RXPMDAT HyperLink0_TXPMCLK HyperLink0_TXPMDAT [12] [12] [12] [12] [12] [12] [12] [12] C7 D7 C8 D8 C9 D9 C10 D10 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 GE1 GE2 GE3 GE4 GE5 GE6 GE7 GE8 GE9 GE10 G3 H3 G4 H4 G5 H5 G6 H6 G7 H7 G8 H8 A1 B1 A2 B2 GC1 GC2 GC3 GC4 GC5 GC6 GC7 GC8 GC9 GC10 VCC3V3_AUX VCC12 uRTM_PS# R188 4.7K 1% C1 uRTM_PS#_R R189 0E uRTM_PS# uRTM_PS# [11] OUT D1 SOC_SDA_RTM R187 0E EXP_SDA2_3V3 [10,18,29] BI C2 R190 NU 0E VCC3V3_MP_AMC D2 SOC_SCL_RTM R186 0E EXP_SCL2_3V3 [10,18,29] IN E1 F1 E2 F2 GF1 GF2 GF3 GF4 GF5 GF6 GF7 GF8 GF9 GF10 GG1 GG2 GG3 GG4 GG5 GG6 GG7 GG8 GG9 GG10 GH1 GH2 GH3 GH4 GH5 GH6 GH7 GH8 GH9 GH10 G1 H1 G2 H2 G9 H9 G10 H10 GNDF1 GNDF2 GNDF3 GNDF4 GNDF5 GNDF6 GNDF7 GNDF8 GNDF9 GNDF10 GNDG1 GNDG2 GNDG3 GNDG4 GNDG5 GNDG6 GNDG7 GNDG8 GNDG9 GNDG10 GNDH1 GNDH2 GNDH3 GNDH4 GNDH5 GNDH6 GNDH7 GNDH8 GNDH9 GNDH10 D A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 IN IN OUT OUT uTCA_SGMII4_TX_DP uTCA_SGMII4_TX_DN uTCA_SGMII4_RX_DP uTCA_SGMII4_RX_DN [12] [12] [12] [12] IN IN OUT OUT uTCA_SGMII5_TX_DP uTCA_SGMII5_TX_DN uTCA_SGMII5_RX_DP uTCA_SGMII5_RX_DN [12] [12] [12] [12] IN IN OUT OUT uTCA_SGMII6_TX_DP uTCA_SGMII6_TX_DN uTCA_SGMII6_RX_DP uTCA_SGMII6_RX_DN [12] [12] [12] [12] IN IN OUT OUT uTCA_SGMII7_TX_DP uTCA_SGMII7_TX_DN uTCA_SGMII7_RX_DP uTCA_SGMII7_RX_DN [12] [12] [12] [12] A9 B9 PHY_MDIO_2V5 RTM_MDC_2V5 BI IN R623 GNDC1 GNDC2 GNDC3 GNDC4 GNDC5 GNDC6 GNDC7 GNDC8 GNDC9 GNDC10 GNDE1 GNDE2 GNDE3 GNDE4 GNDE5 GNDE6 GNDE7 GNDE8 GNDE9 GNDE10 Tx3_3+ Tx3_3Rx3_3+ Rx3_3- Tx0_4+ Tx0_4Rx0_4+ Rx0_4- GNDB1 GNDB2 GNDB3 GNDB4 GNDB5 GNDB6 GNDB7 GNDB8 GNDB9 GNDB10 GNDD1 GNDD2 GNDD3 GNDD4 GNDD5 GNDD6 GNDD7 GNDD8 GNDD9 GNDD10 Tx2_3+ Tx2_3Rx2_3+ Rx2_3- MDIO MDCLK Channel 4 E3 F3 E4 F4 GNDA1 GNDA2 GNDA3 GNDA4 GNDA5 GNDA6 GNDA7 GNDA8 GNDA9 GNDA10 XFI interface GA1 GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 GA10 Channel 3 HyperLink0_TXP1 HyperLink0_TXN1 HyperLink0_RXP1 HyperLink0_RXN1 SGMII interface HyperLink0_TXP1 IN HyperLink0_TXN1 IN HyperLink0_RXP1 HyperLink0_RXN1 OUT OUT Tx1_4+ Tx1_4Rx1_4+ Rx1_4Tx2_4+ Tx2_4Rx2_4+ Rx2_4Tx3_4+ Tx3_4Rx3_4+ Rx3_4XFIMDIO XFIMDCLK Tx0_5+ Tx0_5Rx0_5+ Rx0_5- Channel 5 RXPMCLK2 RXPMDAT2 TXPMCLK2 TXPMDAT2 A5 B5 A6 B6 AIF interface RXFCLK2 RXFLDAT2 TXFCLK2 TXFLDAT2 Tx0_3+ Tx0_3Rx0_3+ Rx0_3- Tx1_5+ Tx1_5Rx1_5+ Rx1_5Tx2_5+ Tx2_5Rx2_5+ Rx2_5Tx3_5+ Tx3_5Rx3_5+ Rx3_5Tx0_6+ Tx0_6Rx0_6+ Rx0_6- Channel 6 RXPMCLK1 RXPMDAT1 TXPMCLK1 TXPMDAT1 Channel 3 GNDE1 GNDE2 GNDE3 GNDE4 GNDE5 GNDE6 GNDE7 GNDE8 GNDE9 GNDE10 HyperLink interface RXFLCLK1 RXFLDAT1 TXFLCLK1 TXFLDAT1 [12] [12] [12] [12] PCIe interface Channel 1 Channel 2 HyperLink interface Tx3_2+ Tx3_2Rx3_2+ Rx3_2- HyperLink0_TXP0 HyperLink0_TXN0 HyperLink0_RXP0 HyperLink0_RXN0 Tx1_6+ Tx1_6Rx1_6+ Rx1_6Tx2_6+ Tx2_6Rx2_6+ Rx2_6Tx3_6+ Tx3_6Rx3_6+ Rx3_6- Channel 7 GH1 GH2 GH3 GH4 GH5 GH6 GH7 GH8 GH9 GH10 Tx2_2+ Tx2_2Rx2_2+ Rx2_2- HyperLink0_TXP0 IN HyperLink0_TXN0 IN HyperLink0_RXP0 HyperLink0_RXN0 OUT OUT Fabric interface GG1 GG2 GG3 GG4 GG5 GG6 GG7 GG8 GG9 GG10 Tx3_1+ Tx3_1Rx3_1+ Rx3_1- Tx1_2+ Tx1_2Rx1_2+ Rx1_2- Channel 1 B GF1 GF2 GF3 GF4 GF5 GF6 GF7 GF8 GF9 GF10 GNDC1 GNDC2 GNDC3 GNDC4 GNDC5 GNDC6 GNDC7 GNDC8 GNDC9 GNDC10 GNDD1 GNDD2 GNDD3 GNDD4 GNDD5 GNDD6 GNDD7 GNDD8 GNDD9 GNDD10 Tx2_1+ Tx2_1Rx2_1+ Rx2_1- A3 B3 A4 B4 SHIELD GND GE1 GE2 GE3 GE4 GE5 GE6 GE7 GE8 GE9 GE10 GNDB1 GNDB2 GNDB3 GNDB4 GNDB5 GNDB6 GNDB7 GNDB8 GNDB9 GNDB10 SHIELD GND GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 Tx1_1+ Tx1_1Rx1_1+ Rx1_1- Tx0_2+ Tx0_2Rx0_2+ Rx0_2- USB interface GC1 GC2 GC3 GC4 GC5 GC6 GC7 GC8 GC9 GC10 GNDA1 GNDA2 GNDA3 GNDA4 GNDA5 GNDA6 GNDA7 GNDA8 GNDA9 GNDA10 Other interface C HyperLink interface Tx0_1+ Tx0_1Rx0_1+ Rx0_1- GB1 GB2 GB3 GB4 GB5 GB6 GB7 GB8 GB9 GB10 J2 connector close to Key socket. J2 ATCA D GA1 GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 GA10 1 A10 B10 C10 D10 E9 F9 E10 F10 G9 H9 G10 H10 C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 100E 120-pin Expansion Header the interfaces on the 120-pin header are all 1.8V LVCMOS except for the UART which is 3.3V LVCMOS CN7 BB_60x2V_S0.5mm [10,12,26] [12] H11 C874 10pF50V IN IN OUT OUT SOC_XFI_TX_DP0 SOC_XFI_TX_DN0 SOC_XFI_RX_DP0 SOC_XFI_RX_DN0 [13] [13] [13] [13] IN IN OUT OUT SOC_XFI_TX_DP1 SOC_XFI_TX_DN1 SOC_XFI_RX_DP1 SOC_XFI_RX_DN1 [13] [13] [13] [13] NPTH VCC1V8 I2C LAYOUT NOTE: Place R623, R653, C874, C896 close to J2 connector C9 D9 BI IN F2 E2 F1 E1 R653 100E EXP_XFI_MDIO_2V5 EXP_XFI_MDC_2V5 [12] [12] EMIF C896 10pF50V [10,18,29] [10,18,29] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] F4 E4 F3 E3 EXP_SDA2_3V3 EXP_SCL2_3V3 BUFF_EMIFD0 BUFF_EMIFD1 BUFF_EMIFD2 BUFF_EMIFD3 BUFF_EMIFD4 BUFF_EMIFD5 BUFF_EMIFD6 BUFF_EMIFD7 BUFF_EMIFD8 BUFF_EMIFD9 BUFF_EMIFD10 BUFF_EMIFD11 BUFF_EMIFD12 BUFF_EMIFD13 BUFF_EMIFD14 BUFF_EMIFD15 BI OUT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BUFF_EMIFCE1Z BUFF_EMIFCE2Z BUFF_EMIFCE3Z BUFF_EMIFBE0Z BUFF_EMIFBE1Z BUFF_EMIFOEZ BUFF_EMIFWEZ F6 E6 F5 E5 IN IN IN IN IN IN IN VCC5V F8 E8 F7 E7 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 61 63 65 67 69 [17] SOC_EMIFWAIT1 OUT 71 [18] SOC_TIMO0 IN 73 OUT [18] SOC_TIMI0 75 [18] SOC_TIMO1 IN 77 OUT [18] SOC_TIMI1 79 [18] SOC_SPI2_DOUT IN 81 R54 22E OUT [18] SOC_SPI2_DIN 83 [18] SOC_SPI2_CS0 I N 85 [18] SOC_SPI2_CS1 I N 87 [18] SOC_SPI2_CS2 I N 89 [18] SOC_SPI2_CS3 I N 91 [18] SOC_SPI2_CLK I N 93 [18] SOC_UART1_RX_3V3 OUT 95 [18] SOC_UART1_TX_3V3 IN 97 [18] SOC_UART1_RTS_3V3 IN 99 [18] SOC_UART1_CTS_3V3 OUT TSRX_CLK0N 101 [13] TSRX_CLK0N IN TSRX_CLK0P103 [13] TSRX_CLK0P IN TSRX_CLK1N105 [13] TSRX_CLK1N IN TSRX_CLK1P107 [13] TSRX_CLK1P IN TSPUSHEVt0_E109 TSPUSHEVT0_E OUT TSPUSHEVt1_E111 OUT TSPUSHEVT1_E TSCOMPOUT_E113 TSCOMPOUT_E IN TSSYNCEVT_E 115 TSSYNCEVT_E IN 117 119 VCC3V3_AUX BUFF_EMIFRNW IN EMIF TIMI G1 H1 G2 H2 G3 H3 G4 H4 SPI G5 H5 G6 H6 UART SOC_UART(3.3V) G7 H7 G8 H8 [13] [13] [13,29] [13] A10 B10 C10 D10 E9 F9 E10 F10 G9 H9 G10 H10 VCC1V8 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN BI BI NPTH BUFF_EMIFA00 BUFF_EMIFA01 BUFF_EMIFA02 BUFF_EMIFA03 BUFF_EMIFA04 BUFF_EMIFA05 BUFF_EMIFA06 BUFF_EMIFA07 BUFF_EMIFA08 BUFF_EMIFA09 BUFF_EMIFA10 BUFF_EMIFA11 BUFF_EMIFA12 BUFF_EMIFA13 BUFF_EMIFA14 BUFF_EMIFA15 BUFF_EMIFA16 BUFF_EMIFA17 BUFF_EMIFA18 BUFF_EMIFA19 BUFF_EMIFA20 BUFF_EMIFA21 BUFF_EMIFA22 BUFF_EMIFA23 EXP_GPIO_00 EXP_GPIO_01 [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [11] [11] C EMIF VCC5V 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 EXP_TP0 98 EXP_TP1 100EXP_TP2 102 104 106 108 110 112 114 116 118 120 VCC3V3_AUX [17] H1 VCC3V3_AUX BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI TP9 R42 R34 EXP_GPIO_02 EXP_GPIO_03 EXP_GPIO_04 EXP_GPIO_05 EXP_GPIO_06 EXP_GPIO_07 EXP_GPIO_08 EXP_GPIO_09 EXP_GPIO_10 EXP_GPIO_11 EXP_GPIO_12 EXP_GPIO_13 EXP_GPIO_14 EXP_GPIO_15 EXP_GPIO_16 [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] GPIO B 0E MCU_RESETSTATz I N MCU_RESETSTATz 0E EXT_PS# EXT_PS# [11] OUT BD_PRESENT [11] OUT OUT BD_ID0 [11] BD_ID1 [11] OUT OUT BD_ID2 [11] I N RSV_CLKN [24] I N RSV_CLKP [24] OUT TSCOMPOUT_E [13,29] VCC3V3_AUX H2 VCC3V3_AUX H12 Project K2E EVM A EXT_PS# R35 4.7K 1% Designed for TI by eInfochips Title uTCA AND EXPANSION Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 [11] H3 H4 H5 H6 H7 H8 H9 H10 J4 ATCA 2 3 2 Sheet 1 29 of 37 A 5 4 3 VCC12@5A INPUT DC FAN Connector for SOC 12V to VCC3V3_MP_ALT Generation F1 TP61 FAN1 22-23-2041 C797 1uF 25V 3 2 R254 CT7 D12 PJ-044BH VCC3V3_MP_ALT + 2.2K I(hold) = 6A I(trip) = 12A Trip time= 16s SMBJ12A IN FAN_PWM VCC12 [28] TP8 FB2 120_100MHz 3 C798 25V 1uF C275 100uF 25V 22uF 20V 3V3_MP @ 150mA Q2 C13 25V 100nF VIN C14 25V 1uF VOUT1 VOUT2 D10 2 4 D C5 6.3V 100uF TLV1117-33CDCY 0.8A 1 D 4 3 2 1 RGEF600-2 ADJ/GND VCC12 Voltage BreakDown = 13.3V J11 1 1 VCC12 TVS Over Current Protection VCC12_AMC 2 LED VOUT = 0.8 * (R1/R2 + 1) = 0.8 * (53.6/10 + 1) = ~5V 12V to 5V Generation VCC3V3_AUX R215 U25 TPS54620RGYR C138 25V 22uF C137 25V 4.7uF 4 5 C139 25V 100nF PVIN1 PVIN2 6 [28] VCC5V_EN C149 25V 10nF R216 1% PH2 PH1 GND1 GND2 EPAD 53.6K C134 100nF 25V 12 11 L6 R221 10E NU VSENSE 5V @ 3A 2.2uH,5A 53.6K C131 25V 100nF 8 10K VDD33 C467 [28] VCC3V3_EN IN B2 ON B1 GND 100nF 25V C REFERENCE CAPACITOR = 2.2uH R217 2.2K Vin = 10.8V to 13.2V Fsw = 900KHz VCC1V8 to VPP1V8 Generation C152 25V 10nF VCC1V8 VPP1V8 3.3V_AUX to 2.5V Generation A2 TP7 VCC3V3_AUX TP95 TP40 TP41 TP62 TP52 TP48 TP38 TP24 VPP1V8 C478 1uF 16V VCC2V5 [11] Q15 TPS73701DRBT 8 R649 VCC3V3_AUX_EN I N EN NC1 GND EPAD VOUT FB NC3 NC2 R647 1% R1 C884 25V 10uF 100nF 25V B1 2.5V @ 0.8A C883 25V 100nF Distribute these TP in board 39.2K 1.5V to 0.75V Generation B R650 NU R648 1% 10K 36.5K VCC3V3_AUX R2 VCC3V3_AUX C775 C772 R549 10uF 25V VCC3V3_AUX 1K 1 VCC0V75_EN 2 7 IN C114 25V 4.7uF C112 25V 100nF 6 10 IN 9 1 R610 4.7K 1% C105 25V 10nF R212 1% 68.1K 2 3 15 PVIN1 PVIN2 VIN PWRGD BOOT PH2 PH1 EN SS/TR RT/CLK GND1 GND2 EPAD 14 13 VCC1V5 C117 L2 COMP VLDOIN EN PGND REFOUT C765 C758 100nF 10uF 25V 25V VCC0V75 EPAD TP84 0.75V @ 3A 3 4 C766 C767 C768 5 10uF 25V CT8 + 10uF 25V 10uF 25V 220uF 2.5V 11 Rrt =48000 * Fsw(kHz)^(-0.997) - 2 =48000 * 700^(-0.997) - 2 =~68 Kohms OUTPUT CAPACITOR CALCULATION Cout = 2 * delta(Iout) / ( Fsw*delta(Vout) = 2 * 1 / (700kHz*0.125) = ~38uF Project R209 1% REFERENCE CAPACITOR = 100uF Title 10K INDUCTOR CALCULATION L = (Vin - Vout)/(Iout * Kind) *(Vout / (Vin * Fsw)) = (12 - 1.5)/(4.5 * 0.3) * (1.5 / (12 * 700KHz)) = 7.78 * 0.18u = ~ 1.38uH 8.87K 7 C121 10V 22uF C122 6.3V 100uF 8 Vin = 10.8V to 13.2V R208 1% 768E C103 K2E EVM Designed for TI by eInfochips POWER SUPPLY--1 Size C Document Number Rev 16_00175_02 2.01 REFERENCE CAPACITOR = 1.2uH 27nF 50V 5 1.5V @ 4.5A 1.2uH,11.1A R207 10E C106 100nF 25V R204 NU NU 1% Snubber Circuit VSENSE TP44 100nF 25V 12 11 REFIN 9 TP46 10K U22 TPS54620RGYR 4 5 PGOOD VOSNS 6 VOUT = 0.8 * (R1/R2 + 1) = 0.8 * (8.87/10 + 1) = ~1.5V R213 TP78 10K VIN VCC0V75REF R529 100nF 25V 10K VCC12 U74 TPS51200DRCT 10 VO [28] C780 C779 12V to 1.5V Generation R532 4.7uF 100nF 25V 25V C785 R550 25V 1K 10nF VCC1V5 A GND 10K 3 7 6 Vout = (R1+R2)/R2*1.204 = (39.2k+36.5k)/36.5k*1.204 = 2.50V VCC1V5_EN ON 1 VCC1V5 [28] B2 R432 1K VCC2V5_EN C895 25V 100nF C113 25V 22uF IN GND EPAD1 EPAD2 EPAD3 EPAD4 EPAD5 [28,31] VIN SOC_VPPB_EN 8 12 13 14 15 16 B 5 2 4 9 C881 25V 100nF TP45 U63 TPS22913BYZVR A1 VIN VOUT C518 C882 25V 10uF TP39 U62 TPS22913BYZVR A1 VIN VOUT C455 INDUCTOR CALCULATION L = (Vin - Vout)/(Iout * Kind) * (Vout / (Vin * Fsw)) = (12 - 5)/(3 * 0.3) * (5/ (12 * 900KHz)) = 7.78 * 0.46u = ~ 3.6uH 7 VDD33 A2 1uF 16V C128 25V 22uF R218 1% COMP VCC3V3_AUX OUTPUT CAPACITOR CALCULATION Cout = 2 * delta(Iout) / ( Fsw*delta(Vout)) = 2 * 1 / (900kHz*0.25) = ~9uF REFERENCE CAPACITOR = 22uF C148 100nF 25V R219 1% NU Snubber Circuit SS/TR RT/CLK 2 3 15 VCC5V TP50 14 13 EN 9 1 R609 4.7K 1% C VIN 10 IN TP49 10K PWRGD BOOT 3V3_AUX to VDD33 Generation Rrt = 48000 * Fsw(kHz)^(-0.997) - 2 = 48000 * 900^(-0.997) - 2 = ~52.5 Kohms VCC12 Date: Wednesday, May 14, 2014 4 3 2 Sheet 1 30 of 37 A 5 4 3 [11,27,28,31] [27,28] 12V to CVDD Generation(TPS544C24) VCC12 CT5 + C842 (4.7nF) must connect very close to VIN pins of TPS544C24 0E 0E PMBUS_CLK PMBUS_DAT CVDD_EN R589 0E R580 R583 0E 0E CT4 C268 C267 C266 C270 C842 100uF 20V 22uF 25V 22uF 25V 22uF 25V 4.7uF 25V 4.7nF 25V IN BI BP3 1E R594 2K VOUTS- 34 NU 4 EN MODE 6 SET R590 182K R611 0E 35 8.45K C858 2.2nF 50V 10 9 8 7 IN IN IN IN VDDCMON_R R545 10E 32 VSSCMON_R R547 10E R546 100E 7 R263 C277 100nF 25V 0E IN VDDCMON [21] IN VSSCMON [21] D TP51 C849 2.2uF 0E LM10011_VID1S LM10011_VID1C LM10011_VID1B LM10011_VID1A FB TPS544C24 COMP BP6 28 BP3 27 CVDD CVDD SYNC/RESET# AGND R275 12 11 10 9 8 L12 CVDD(1V) @ 18A Snubber 220nH,30.7A CT1 Circuit R262 10E C276 50V 10pF NU NU 3 2 R266 R271 39 R278 10K 14K 14K + D15 B340A-13-F 1000uF 2.5V BP3 CT3 CT2 + + 1000uF 2.5V 680uF 2.5V C225 C219 C206 C257 GNDC 47uF 6.3V 22uF 10V 10uF 25V 1uF 16V BP6 AGND BP3 R277 NU C279 2.2uF [19] [19] [19] [19] SW5 SW4 SW3 SW2 SW1 ADDR0 ADDR1 40 VIDS VIDC VIDB VIDA Place R545 and R547 very close to the SoC CVDD power pins 31 TP93 100pF 50V RT TSNS/SS VSET 0E IN CVDD_EN [28] R608 4.7K 1% 37 30 20K DAP 5 GND R588 0E NU IDAC_OUT 1 IN VCC3V3_AUX VDD R603 LAYOUT NOTE: R544 100E 10K DIFFO AGND PGND9 PGND8 PGND7 PGND6 PGND5 PGND4 PGND3 PGND2 PGND1 R592 R268 R279 127K 6.81K Fsw = 1MHz AGND 11 R276 0E IDAC_OUT 2 33 C859 2.2nF 50V R280 R587 6.81K EPAD 93.1K U35 LM10011SD 3 NU VOUTS+ 36 38 26 20 19 18 17 16 15 14 13 AGND R593 NOTE: R593 must be unpopulated in PMBus AGND mode and VCNTL mode. 41 4.7uF 25V C857 C296 25V 100nF AGND NOTE: R268 will be 51.1K in PMBus mode LM10011_MODE C PGOOD BOOT VCC3V3_AUX LM10011_EN VIN1 VIN2 VIN3 VIN4 VIN5 VDD C281 R267 must connect to VIN plane very close to VIN pins of TPS544C24 [27] DATA CLK CNTL SMBALRT# VCC12 LAYOUT NOTE: CVDD TP86 U34 21 22 23 24 25 29 D R267 1 + 100uF 20V 4 5 1 6 LAYOUT NOTE: [28,31] [28,31] 2 R577 R584 PMBUS_ALERT OUT PMBUS_CTL IN AGND R612 0E C LAYOUT NOTE: Currently, AGND and PGND are NOT shorted in schematic, to keep 2 seperate grounds in layout design file. However, they should be shorted in layout design file ONLY at SINGLE point, i.e.: Pin 38 can be directly connected to Thermal Pad with thicker trace VDDD R282 10K LM26430(Quad Switcher) [11,27,28,31] [28,31] [28,31] PMBUS_ALERT IN PMBUS_DAT PMBUS_CLK BI IN R258 NU 0E R255 NU 0E R259 NU 0E TP63 43 42 44 41 VCC12 CT6 C283 25V 1uF + 100uF 20V C263 100nF 25V C261 25V 1uF C264 C262 C260 100nF 25V 10uF 25V 10uF 25V 22 SCL SDA CLK_OUT I2CALERT U33 5 6 30 31 PVIN1 PVIN2 PVIN3 PVIN4 CB1 SW1_1 SW1_2 SW1_3 1 C256 100nF 25V 2 3 4 CVDD1 L11 R272 B [28] [28,30] [28] [28] CVDD1_EN VCC3V3_AUX_EN VCC1V8_EN VCC0V85_EN 10K17 48 13 27 34 IN IN IN IN R604 R605 R606 R607 4.7K 4.7K 4.7K 4.7K 1% 1% 1% 1% NU 100nF 25V VIN PGOOD VFB1 ENSW1 ENSW2 ENSW3 ENSW4 CB2 SW2_1 SW2_2 SW2_3 VDDD TP94 R575 R567 C854 10uF 25V VDDG C853 4.7uF 25V VDDA C852 3.3uF 6.3V VDDD 0E 23 10K 39 18 19 20 VFB2 VDDG VDDA VDDD CB3 LM26430 C821 560pF R561 28.7K 16V C823 22pF50V 46 SW3 15 22uF 25V 22uF 25V C244 22uF 25V C246 560pF 16V R257 2.49K R261 9 10 11 13.7K VCC3V3_AUX3V3 L14 3.3uH,4A C294 C293 C291 100nF 25V 22uF 25V 22uF 25V 22uF 25V 100pF 50V R269 28 C280 100nF 25V VCC1V8 GND2 GND3 GND4 0E R273 43.2K 14 L13 GND1 R281 C290 29 B VCC3V3_AUX @ 2A C289 AGND1 13.7K 1V8 VCC1V8 @ 2A 3.3uH,4A C285 C286 C287 C288 C292 100nF 25V VF3 C282 560pF R586 100K 16V C851 6.8pf 50V C247 12 C278 100nF 25V COMP1 AGND1 C252 47 CE RESET_N AGND1 CVDD1 (0.95V) @ 2.5A C243 VDDD CVDD1 2.2uH,5A CB4 COMP2 SW4_1 22uF 25V 22uF 25V 22uF 25V R274 8.87K 82pF 50V 26 R270 32 6.98K VCC0V85 0V85 33 C254 100nF 25V L10 0.85V @ 1.85A 2.2uH,5A C248 C250 C251 C249 C245 AGND1 100nF 25V C284 50V 1nF R582 54.9K C856 12pF 25 50V VFB4 I2CADDR SS1/PG1 SS2/PG2 SS3/PG3 SS4/PG4 RCLOCK_SYNC 38 PGND1 PGND2 7 8 EPAD C822 22pF50V AGND1 COMP4 21 R560 26.1K 49 C820 50V 1nF 36 AGND AGND1 A 22uF 25V COMP3 R566 35 45 16 24 37 4 R256 2.7K 43.2K 1% K2E EVM Designed for TI by eInfochips Title 40 POWER SUPPLY--2 R569 383K Fsw = ~450 KHz Size C Document Number Rev 16_00175_02 2.01 AGND1 Date: Wednesday, May 14, 2014 Slave I2C Address = 0x69 5 430pF 50V Project 10nF25V 10nF25V 10nF25V 10nF25V 10K AGND1 22uF 25V R260 C830 C295 C843 C829 LAYOUT NOTE: Follow Layout Instruction guidelines 22uF 25V 3 2 Sheet 1 31 of 37 A 5 4 3 2 1 U15-6 VERSION XDS_VCC3V3 U15-1 F4 RSVD/RTC_ALARM/UART2_CTSn/GP0[8]/DEEPSLEEPn A3 AHCLKX/USB_REFCLKIN/UART1_CTSn/GP0[10] B1 B2 C5 C4 ACLKX/GP0[14] AFSX/GP0[12] AXR11/FSX1/GP0[3] AXR12/FSR1/GP0[4] R98 VER0 470E SPI1_SCS[0] SPI1_WPn E19 F18 F19 E18 SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12 SPI1_SCS[1]/EPWM1A/GP2[15]/TM64P2_IN12 SPI1_SCS[2]/UART1_TXD/SATA_CP_POD/GP1[0] SPI1_SCS[3]/UART1_RXD/SATA_LED/GP1[1] TP17 BI BI CPLD_TXD1 CPLD_RXD1 [36] [36] R90 R91 R92 R96 2.2K NU 2.2K NU 2.2K 2.2K NU VER3 F16 F17 G18 G16 SPI1_SCS[4]/UART2_TXD/I2C1_SDA/GP1[2] SPI1_SCS[5]/UART2_RXD/I2C1_SCL/GP1[3] SPI1_SCS[6]/I2C0_SDA/TM64P3_OUT12/GP1[4] SPI1_SCS[7]/I2C0_SCL/TM64P2_OUT12/GP1[5] A1 A2 C2 D5 ACLKR/GP0[15] AHCLKR/UART1_RTSn/GP0[11] AFSR/GP0[13] AMUTE/UART2_RTSn/GP0[9] D R368 R381 47E 47E TP16 TP22 VER2 D VER1 VER0 F3 E1 E2 E3 AXR0/ECAP0_APWM0/GP8[7]/MII_TXD[0]/CLKS0 AXR1/DX0/GP1[9]/MII_TXD[1] AXR2/DR0/GP1[10]/MII_TXD[2] AXR3/FSX0/GP1[11]/MII_TXD[3] D1 D3 C1 D2 AXR4/FSR0/GP1[12]/MII_COL AXR5/CLKX0/GP1[13]/MII_TXCLK AXR6/CLKR0/GP1[14]/MII_TXEN AXR7/EPWM1TZ[0]/GP1[15] AXR8/CLKS1/ECAP1/APWM1/GP0[0] AXR9/DX1/GP0[1] AXR10/DR1/GP0[2] AXR13/CLKX1/GP0[5] AXR14/CLKR1/GP0[6] AXR15/EPWM0TZ[0]/ECAP2_APWM2/GP0[7] H16 G19 G17 H17 SPI1_ENAn/GP2[12] SPI1_CLK/GP2[13] SPI1_SIMO/GP2[10] SPI1_SOMI/GP2[11] R105 47E SPI1_CLK SPI1_SIMO SPI1_SOMI R76 R77 R78 R87 2.2K 2.2K 2.2K NU 2.2K REV-B D17 E16 SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12 SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12 E4 C3 D4 R107 R102 R106 B3 B4 A4 VER1 VER2 VER3 470E 470E 470E TP23 TP19 TP21 D16 E17 D18 C19 SPI0_SCS[2]/UART0_RTSn/GP8[1]/MII_RXD[0]/SATA_CP_DET SPI0_SCS[3]/UART0_CTSn/GP8[2]/MII_RXD[1]/SATA_MP_SWITCH SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2] SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3] C17 D19 C16 C18 SPI0_ENAn/EPWM0B/MII_RXDV SPI0_CLK/EPWM0A/GP1[8]/MII_RXCLK SPI0_SOMI/EPWMSYNCI/GP8[6]/MII_RXER SPI0_SIMO/EPWMSYNC0/GP8[5]/MII_CRS POWER GROUP A C C AM1802BZWTD3 POWER GROUP A AM1802BZWTD3 XDS_USB_VBUS XDS_VCC3V3 FB4 220_100MHz U15-10 N18 PWR GROUP B USB0_DRVVBUS 6 M19 XDS_USB_DP R384 3 M14 NC.M14 1uF 16V N17 USB0_VDDA12 PWR GROUP B USB0_ID P16 VBUS DD+ GND_1 GND_2 D7 GREEN 54819-0519 J3 FB16 120_100MHz 10KV XDS_VBUS XDS_USB_GND XDS_USB_GND XDS_VCC3V3 R342 10K G 1 EMULED2 S R104 R103 2.2K 2.2K R346 10K R352 10K R355 10K Project K2E EVM 1 2 3 4 CS DO WP GND VCC HOLD SCLK DI 8 7 6 5 Designed for TI by eInfochips Title SPI_HOLDn SPI1_CLK SPI1_SIMO XDS200_1 R348 W25X10BV Size 128K BYTE C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 Q7 NTA4153N C347 25V 100nF U5 2.2K D Q8 NTA4153N S [33] XDS_VCC3V3 A SPI1_SCS[0] SPI1_SOMI SPI1_WPn D 1 G EMULED1 2 [33] R345 10K D9 GREEN R398 1.5K AM1802BZWTD3 XDS_VCC3V3 D8 GREEN B D14 TPD4S012DRYR XDS_VCC3V3 C389 220nF 10V 0E 1 2 3 4 5 R373 470E 2 XDS_VBUS XDS_USB_DM XDS_USB_DP R372 470E 3 USB0_DP XDS_USB_DM 2 R156 1.5K XDS_USB_VBUS M18 3 USB0_DM C418 C398 10nF 25V R371 470E RV1 PTH2 PTH1 USB0_VDDA18 4 C433 C424 1nF 100nF 50V 25V 10nF25V 7 N19 4 N14 2 B 150K C51 1 NC.N16 USB0_VBUS FB19 3 0.47uF V5.5MLA0603H R162 K18 2 N16 XDS_1V8 1 10nF 25V 1 USB0_VDDA33 10uF 25V 2 1uF 16V 6 10nF 25V C55 1 C408 C409 5 C410 C407 1nF 100nF 50V 25V C52 2 90 ohm differential pairs Differential Pair USB0_VDDA33 FB17 3 0.47uF 2 1 1 4 XDS_VCC3V3 4 3 2 Sheet 1 32 of 37 A 5 4 3 2 1 U15-2 EMA_A[23]/MMCSD0_CLK/GP4[7] EMA_A[22]/MMCSD0_CMD/GP4[6] EMA_A[21]/MMCSD0_DAT[0]/GP4[5] EMA_A[20]/MMCSD0_DAT[1]/GP4[4] EMA_A[19]/MMCSD0_DAT[2]/GP4[3] EMA_A[18]/MMCSD0_DAT[3]/GP4[2] EMA_A[17]/MMCSD0_DAT[4]/GP4[1] EMA_A[16]/MMCSD0_DAT[5]/GP4[0] XDS_VCC3V3 R97 10K B18 R101 10K B19 EMA_WAIT[0]/GP3[8] EMA_WAIT[1]/GP2[1] E9 A10 B10 A11 C10 E11 B11 E12 R84 R85 GP4-4 GP4-3 GP4-2 GP4-1 GP4-0 R83 470E OUT 470E OUT OUT 22E EMULED2 [32] EMULED1 [32] CPLD_RESETn [36] BI [36] RN2 4 3 2 1 EMA_A9 EMA_A8 EMA_A11 EMA_A10 RN4 4 3 2 1 CPLD_BIO_0 RPACK4-22 5 6 7 8 CPLD_BIO_3 CPLD_BIO_2 CPLD_BIO_1 CPLD_BIO_4 BI BI BI BI [36] [36] [36] [36] EMA_D[0..15] XDS_VCC3V3 EMA_D[0..15] D EMA_D15 EMA_D14 EMA_D13 EMA_D12 EMA_D11 EMA_D10 EMA_D9 EMA_D8 E6 C7 B6 A6 D6 A7 D9 E10 EMA_D7 EMA_D6 EMA_D5 EMA_D4 EMA_D3 EMA_D2 EMA_D1 EMA_D0 D7 C6 E7 B5 E8 B8 A8 C9 EMA_D[15]/GP3[7] EMA_D[14]/GP3[6] EMA_D[13]/GP3[5] EMA_D[12]/GP3[4] EMA_D[11]/GP3[3] EMA_D[10]/GP3[2] EMA_D[9]/GP3[1] EMA_D[8]/GP3[0] EMA_A[15]/MMCSD0_DAT[6]/GP5[15] EMA_A[14]/MMCSD0_DAT[7]/GP5[14] EMA_A[13]/GP5[13] EMA_A[12]/GP5[12] EMA_A[11]/GP5[11] EMA_A[10]/GPIO5[10] EMA_A[9]/GP5[9] EMA_A[8]/GP5[8] EMA_D[7]/GP4[15] EMA_D[6]/GP4[14] EMA_D[5]/GP4[13] EMA_D[4]/GP4[12] EMA_D[3]/GP4[11] EMA_D[2]/GP4[10] EMA_D[1]/GP4[9] EMA_D[0]/GP4[8] EMA_A[7]/GP5[7] EMA_A[6]/GP5[6] EMA_A[5]/GP5[5] EMA_A[4]/GP5[4] EMA_A[3]/GP5[3] EMA_A[2]/GP5[2] EMA_A[1]/GP5[1] EMA_A[0]/GP5[0] EMA_BA[1]/GP2[9] EMA_BA[0]/GP2[8] EMA_CLK/GP2[7] EMA_SDCKE/GP2[6] EMA_CASn/GP2[4] EMA_RASn/GP2[5] C11 A12 D11 D13 B12 C12 D12 A13 EMA_A12 EMA_A11 EMA_A10 EMA_A9 EMA_A8 B13 E13 C13 A14 D14 B14 D15 C14 EMA_A7 EMA_A6 EMA_A5 EMA_A4 EMA_A3 EMA_A2 EMA_A1 EMA_A0 EMA_A4 EMA_A6 EMA_A5 EMA_A7 A15 C15 EMA_BA1 EMA_BA0 B7 D8 A9 A16 R283 R476 R481 R596 EMA_A2 EMA_A0 EMA_A3 EMA_A1 22E 22E 22E 22E MEM_CLK MEM_CKE MEM_CASn MEM_RASn EMA_A12 EMA_BA0 EMA_BA1 RPACK4-22 5 6 7 8 C866 C865 C864 C863 C862 C861 C860 22uF 10V 100nF 100nF 100nF 100nF 100nF 100nF 25V 25V 25V 25V 25V 25V MEM_A9 MEM_A8 MEM_A11 MEM_A10 RN3 4 3 2 1 RPACK4-22 5 6 7 8 MEM_A4 MEM_A6 MEM_A5 MEM_A7 RN1 4 3 2 1 RPACK4-22 5 6 7 8 MEM_A2 MEM_A0 MEM_A3 MEM_A1 RN9 4 3 2 1 RPACK4-22 MEM_A12 5 MEM_BA0 6 MEM_BA1 7 8 MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 CPLD ADDRESS ON 32-BIT BOUNDARY BI BI BI BI CPLD_A2 CPLD_A0 CPLD_A3 CPLD_A1 U78 MT48LC4M16A2B4-75:G A8 VDD1 DQ0 B9 VDD2 DQ1 B8 VDD3 DQ2 C9 VDDQ1 DQ3 C8 VDDQ2 DQ4 D9 VDDQ3 DQ5 D8 VDDQ4 DQ6 E9 DQ7 E1 A0 DQ8 D2 A1 DQ9 D1 A2 DQ10 C2 A3 DQ11 C1 A4 DQ12 B2 A5 DQ13 B1 A6 DQ14 A2 A7 DQ15 A8 F3 A9 CKE F2 A10 CLK G9 CS A11 A3 BA0 VSSQ1 B7 BA1 VSSQ2 C3 WE VSSQ3 D7 RAS VSSQ4 A1 CAS VSS1 E3 DQML VSS2 J1 DQMH VSS3 NC1 NC2 A9 E7 J9 A7 B3 C7 D3 H7 H8 J8 J7 J3 J2 H3 H2 H1 G3 H9 MEM_A11 G2 MEM_BA0 G7 MEM_BA1 G8 MEM_WEn F9 MEM_RASn F8 MEM_CASn F7 MEM_WE_DQM0n E8 MEM_WE_DQM1n F1 E2 G1 [36] [36] [36] [36] TP92 MEM_D0 MEM_D1 MEM_D2 MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_D7 MEM_D8 MEM_D9 MEM_D10 MEM_D11 MEM_D12 MEM_D13 MEM_D14 MEM_D15 RN5 4 3 2 1 RPACK4-22 5 EMA_D0 6 EMA_D1 7 EMA_D2 8 EMA_D3 MEM_D7 MEM_D6 MEM_D5 MEM_D4 RN6 4 3 2 1 RPACK4-22 5 EMA_D7 6 EMA_D6 7 EMA_D5 8 EMA_D4 MEM_D11 MEM_D10 MEM_D9 MEM_D8 RN7 4 3 2 1 RPACK4-22 5 EMA_D11 6 EMA_D10 7 EMA_D9 8 EMA_D8 MEM_D15 MEM_D13 MEM_D14 MEM_D12 RN8 4 3 2 1 RPACK4-22 5 EMA_D15 6 EMA_D13 7 EMA_D14 8 EMA_D12 MEM_CKE MEM_CLK MEM_CS0n XDS_VCC3V3 R598 10K MEM_D0 MEM_D1 MEM_D2 MEM_D3 MEM_D0 MEM_D1 CPLD_D0 CPLD_D1 BI BI D [36] [36] R362 10K C C EMA_CS[0]n/GP2[0] EMA_CS[2]n/GP3[15] EMA_CS[3]n/GP3[14] EMA_CS[4]n/GP3[13] EMA_CS[5]n/GP3[12] A18 B17 A17 F9 B16 R597 22E R81 22E MEM_CS0n CPLD_CSn BI [36] XDS_VCC3V3 R363 R72 EMA_OEn/GP3[10] EMA_WEn/GP3[11] EMA_WE_DQM[0]n/GP2[3] EMA_WE_DQM[1]n/GP2[2] EMA_A_RWn/GP3[9] POWER GROUP B B15 B9 C8 A5 D10 R82 R79 R599 R600 22E 22E 22E 22E 10K 10K MEM_OEn MEM_WEn MEM_WE_DQM0n MEM_WE_DQM1n CPLD_RDn CPLD_WEn BI BI [36] [36] XDS_USB_VBUS XDS_1V2 U20 TPS650006RTET AM1802BZWTD3 C70 22uF 10V C99 C71 100nF 25V 1nF 50V 6 13 16 VINDCDC VINLDO1 VINLDO2 SW 5 L1 LQM2HPN2R2MJ0L NU FB_DCDC 9 C100 22pF 50V R202 C86 22uF 10V 0E C87 100nF 25V R199 NU 10.2K XDS_1V8 XDS_USB_VBUS R203 R191 R192 B XDS_USB_VBUS XDS_USB_VBUS XDS_VCC3V3 C435 100nF 25V C444 100nF 25V FB_LDO1 12 11 R194 0E C85 22uF 10V R196 NU 100K GND 3 4 MR# CT VDD RESET# GND 15 XDS_USB_VBUS 6 1 FB_LDO2 OUT XDS_SYS_RESETn [34] R195 10K TPS65000_PG# 3 2 7 PG# MODE 14 R185 R180 AGND NC Y SENSE EPAD A 3 VLDO2 4 1 5 4 100nF 25V 0E C69 22uF 10V NU 100K C61 100nF 25V 10 2 100nF 25V U19 TPS3808G33DBVR B C82 XDS_VCC3V3 C67 U59 SN74LVC1G04DCKR 5 VCC PGND TPS65000_PG# C442 EN_DCDC EN_LDO1 EN_LDO2 17 100nF 25V 8 1 2 2.49K 1% 2.49K 1% 10K VLDO1 C68 100nF 25V U61 1 2 C 1 2 3 XDS_1V8 R1 NU Project R415 12.1K REF K2E EVM Designed for TI by eInfochips Title 4 5 TLV431ACDBVR Optional - Advisory NU 2.1.7, Set to operate as 1.86V Zener. A A XDS200_2 R2 NU R417 24.3K VO = 1.24*(1+R1/R2) 18.2K ~ 2.0V 22.1K ~ 1.91V 24.3K ~ 1.86V Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 33 of 37 A 5 4 3 2 1 U15-4 U15-5 U15-9 U15-3 R5 W10 U11 V10 U10 T12 T10 T11 T13 D W11 W12 V12 V13 U13 V14 U14 U15 DDR_D[15] DDR_D[14] DDR_D[13] DDR_D[12] DDR_D[11] DDR_D[10] DDR_D[9] DDR_D[8] DDR_A[13] DDR_A[12] DDR_A[11] EMB_A[10] DDR_A[9] DDR_A[8] DDR_D[7] DDR_D[6] DDR_D[5] DDR_D[4] DDR_D[3] DDR_D[2] DDR_D[1] DDR_D[0] DDR_A[7] DDR_A[6] DDR_A[5] DDR_A[4] DDR_A[3] DDR_A[2] DDR_A[1] DDR_A[0] DDR_BA[2] DDR_BA[1] DDR_BA[0] T14 V11 W13 R10 DDR_DQS[0] DDR_CLKP DDR_DQS[1] DDR_CLKN DDR_CSn DDR_DQM[0] DDR_CKE DDR_DQM[1] DDR_RASn DDR_CASn R11 R12 DDR_WEn XDS_BOOTMODE[7] XDS_BOOTMODE[6] XDS_BOOTMODE[5] XDS_BOOTMODE[4] XDS_BOOTMODE[3] XDS_BOOTMODE[2] XDS_BOOTMODE[1] XDS_BOOTMODE[0] T5 V4 T4 W4 T6 U4 U6 W5 V5 U5 V6 W6 T7 U7 [36] [36] [36] [36] CPLD_TDO CPLD_TDI CPLD_TMS CPLD_TCK IN IN IN IN R170 P4 R3 R2 R1 T3 T2 T1 U3 47E U8 T9 V8 DDR_VREF W8 VP_DOUT[15]/LCD_D[15]/UPP_XD[7]/GP7[7]/BOOT[7] VP_DOUT[14]/LCD_D[14]/UPP_XD[6]/GP7[6]/BOOT[6] VP_DOUT[13]/LCD_D[13]/UPP_XD[5]/GP7[5]/BOOT[5] VP_DOUT[12]/LCD_D[12]/UPP_XD[4]/GP7[4]/BOOT[4] VP_DOUT[11]/LCD_D[11]/UPP_XD[3]/GP7[3]/BOOT[3] VP_DOUT[10]/LCD_D[10]/UPP_XD[2]/GP7[2]/BOOT[2] VP_DOUT[9]/LCD_D[9]/UPP_XD[1]/GP7[1]/BOOT[1] VP_DOUT[8]/LCD_D[8]/UPP_XD[0]/GP7[0]/BOOT[0] P15 VP_DIN[15]_VSYNC/UHPI_HD[7]/UPP_CHA_D[7] VP_DIN[14]_HSYNC/UHPI_HD[6]/UPP_CHA_D[6] VP_DIN[13]_FIELD/UHPI_HD[5]/UPP_CHA_D[5] VP_DIN[12]/UHPI_HD[4]/UPP_CHA_D[4] VP_DIN[11]/UHPI_HD[3]/UPP_CHA_D[3] VP_DIN[10]/UHPI_HD[2]/UPP_CHA_D[2] VP_DIN[9]/UHPI_HD[1]/UPP_CHA_D[1] VP_DIN[8]/UHPI_HD[0]/UPP_CHA_D[0]/GP6[5] USB1_VDD33 USB1_DM USB1_DP P14 P18 P19 USB1_VDD18 AM1802BZWTD3 U18 V16 R14 W16 V17 W17 W18 W19 VP_DOUT[7]/LCD_D[7]/UPP_XD[15]/GP7[15] VP_DOUT[6]/LCD_D[6]/UPP_XD[14]/GP7[14] VP_DOUT[5]/LCD_D[5]/UPP_XD[13]/GP7[13] VP_DOUT[4]/LCD_D[4]/UPP_XD[12]/GP7[12] VP_DOUT[3]/LCD_D[3]/UPP_XD[11]/GP7[11] VP_DOUT[2]/LCD_D[2]/UPP_XD[10]/GP7[10] VP_DOUT[1]/LCD_D[1]/UPP_XD[9]/GP7[9] VP_DOUT[0]/LCD_D[0]/UPP_XD8/GPIO7[8] MMCSD1_DAT[7]/LCD_PCLK/GP8[11] MMCSD1_DAT[6]/LCD_MCLK/GP8[10] MMCSD1_DAT[5]/LCD_HSYNC/GP8[9] MMCSD1_DAT[4]/LCD_VSYNC/GP8[8] W14 VP_DIN[7]/UHPI_HD[15]/UPP_CHA_D[15]/RMII_TXD[1] VP_DIN[6]/UHPI_HD[14]/UPP_CHA_D[14]/RMII_TXD[0] VP_DIN[5]/UHPI_HD[13]/UPP_CHA_D[13]/RMII_TXEN VP_DIN[4]/UHPI_HD[12]/UPP_CHA_D[12]/RMII_RXD[1] VP_DIN[3]/UHPI_HD[11]/UPP_CHA_D[11]/RMII_RXD[0] VP_DIN[2]/UHPI_HD[10]/UPP_CHA_D[10]/RMII_RXER VP_DIN[1]/UHPI_HD[9]/UPP_CHA_D[9]/RMII_MHZ_50_CLK VP_DIN[0]/UHPI_HD[8]/UPP_CHA_D[8]/RMII_CRS_DV D NOT USED VP_CLKIN1/UHPI_HDS1n/GP6[6] VP_CLKIN0/UHPI_HCSn/GP6[7]/UPP_2xTXCLK W7 H3 K3 J3 G1 V9 V7 VP_CLKIN2/MMCSD1_DAT[3]/GP6[4] VP_CLKOUT2/MMCSD1_DAT[2]/GP6[3] VP_CLKIN3/MMCSD1_DAT[1]/GP6[2] MMCSD1_DAT[0]/UPP_CHB_CLK/GP8[15] W9 G2 J4 U9 U17 W15 T15 U16 MMCSD1_CLK/UPP_CHB_START/GP8[14] MMCSD1_CMD/UPP_CHB_ENABLE/GP8[13] T8 K4 VP_CLKOUT3/GP6[1] U12 UHPI_HCNTL0/UPP_CHA_CLK/GP6[11] UHPI_HCNTL1/UPP_CHA_START/GP6[10] UHPI_HRWn/UPP_CHA_WAIT/GP6[8] UHPI_HHWIL/UPP_CHA_ENABLE/GP6[9] TP34 R6 G3 DDR_ZP LCD_AC_ENB_CSn/GP6[0] V15 F1 F2 H4 G4 DDR_DQGATE0 DDR_DQGATE1 U2 U1 V3 V2 V1 W3 W2 W1 V18 V19 U19 T16 R18 R19 R15 P17 R16 R17 T18 XDS_VCC3V3 UPP_CHB_WAIT/GP8[12] R166 10K T17 UHPI_HINTn/GP6[12] UHPI_HRDYn/GP6[13] CLKOUT/UHPI_HDS2n/GP6[14] RESETOUTn/UHPI_HASn/GP6[15] C C XDS_VCC3V3 TP35 DBG_TRSTn POWER GROUP C AM1802BZWTD3 NOT USED R409 0E AM1802BZWTD3 J5 DBG_TMS DBG_TDI EMU_TVD DBG_TDO DBG_RTCK DBG_TCK POWER GROUP C AM1802BZWTD3 1 3 5 7 9 11 13 15 17 19 DBG_SRST 2 4 6 8 10 12 14 16 18 20 HEADER 10X2 CTI-20 BOOTMODE: SPI1-FLASH ^B0001100 BOOT MODE XDS_VCC3V3 XDS_VCC3V3 B B XDS_VCC3V3 U15-8 R397 10K [33] XDS_SYS_RESETn R396 IN K14 0E OSCIN L19 OSCIN C50 RESETn R395 J17 470E R375 10K 33pF 50V Y3 24MHz XDS_VCC3V3 DBG_SRST R169 1K 1% NMIn OSCOUT PWR GROUP B OSCVSS K19 L18 OSCOUT C43 33pF 50V OSCVSS R158 1K 1% R152 1K 1% NU R168 1K 1% NU R110 10K NU XDS_BOOTMODE[3] XDS_BOOTMODE[7] XDS_BOOTMODE[2] XDS_BOOTMODE[6] XDS_BOOTMODE[1] XDS_BOOTMODE[5] XDS_BOOTMODE[0] R379 100E XDS_VCC3V3 DBG_TMS L16 DBG_TDI M16 DBG_TDO J18 DBG_TCK J15 DBG_RTCKR140 22E RTCK/GP8[0]K17 R374 10K J16 R114 10K K16 R125 10K NU R141 10K NU XDS_BOOTMODE[4] TRSTn TMS RTC_XI J19 RTC_XI C37 18pF 50V 18pF 50V R176 1K 1% NU 1 L17 TDI 2 3 TDO TCK RTC_XO H19 RTC_XO 4 C360 22pF DBG_TRSTN R148 10K NU 32.768KHz Y2 C32 R159 1K 1% NU R153 1K 1% R175 1K 1% R111 1K 1% R149 1K 1% R126 1K 1% R142 1K 1% RTCK/GP8[0] EMU0 VSS_RTC H18 VSS_RTC EMU1 Project AM1802BZWTD3 K2E EVM A Designed for TI by eInfochips Title XDS200_3 Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 34 of 37 A 5 4 3 2 1 XDS_1V2 U15-15 XDS_1V2 XDS_1V2 U15-12 C375 10V 22uF C381 25V 100nF C380 25V 100nF C390 25V 100nF E15 G7 G8 G13 H6 H7 H10 H11 H12 C366 25V 100nF CVDD.1 CVDD.2 CVDD.3 CVDD.4 CVDD.5 CVDD.6 CVDD.7 CVDD.8 CVDD.9 CVDD.10 CVDD.11 CVDD.12 CVDD.13 CVDD.14 CVDD.15 CVDD.16 CVDD.17 CVDD.18 H13 J6 J12 K6 K12 L12 M8 M9 N8 M2 N4 P1 P2 SATA_VDD.1 SATA_VDD.2 SATA_VDD.3 SATA_VDD.4 SATA_REFCLKP SATA_REFCLKN N2 N1 XDS_1V2 D P3 C376 10V 22uF C369 25V 100nF C386 25V 100nF C393 25V 100nF SATA_TXP J1 D SATA_VDDR SATA_TXN C367 25V 100nF J2 AM1802BZWTD3 N3 SATA_REG SATA_RXN XDS_VCC3V3 XDS_VCC3V3 C402 25V 100nF C400 25V 100nF C359 25V 100nF C365 25V 100nF C363 25V 100nF F5 G5 H5 F15 G14 G15 C372 25V 100nF DVDD3318_A.1 DVDD3318_A.2 DVDD3318_A.3 DVDD3318_A.4 DVDD3318_A.5 DVDD3318_A.6 XDS_VCC3V3 C388 25V 100nF C383 25V 100nF C373 25V 100nF C384 25V 100nF C394 25V 100nF J5 K13 L4 L13 M13 N13 P5 P6 P12 R4 C395 25V 100nF E14 F6 F7 F8 F10 F11 F12 F13 G9 J14 K15 H1 H2 K1 K2 L3 M1 DVDD3318_C.1 DVDD3318_C.2 DVDD3318_C.3 DVDD3318_C.4 DVDD3318_C.5 DVDD3318_C.6 DVDD3318_C.7 DVDD3318_C.8 DVDD3318_C.9 DVDD3318_C.10 C C379 25V 100nF C399 25V 100nF C370 25V 100nF C377 25V 100nF F14 G6 G10 G11 G12 J13 K5 L6 P13 R13 XDS_1V2 A19 H8 H9 H15 J7 J8 J9 J10 J11 K7 K8 K9 K10 K11 L5 DVDD18.1 DVDD18.2 DVDD18.3 DVDD18.4 DVDD18.5 DVDD18.6 DVDD18.7 DVDD18.8 DVDD18.9 DVDD18.10 RVDD.1 RVDD.2 RVDD.3 C378 25V 100nF C392 25V 100nF AM1802BZWTD3 VSS.1 VSS.2 VSS.3 VSS.4 VSS.5 VSS.6 VSS.7 VSS.8 VSS.9 VSS.10 VSS.11 VSS.12 VSS.13 VSS.14 VSS.15 VSS.16 VSS.17 VSS.18 VSS.19 VSS.20 VSS.21 VSS.22 VSS.23 VSS.24 VSS.25 VSS.26 VSS.27 VSS.28 VSS.29 VSS.30 L7 L8 L9 L10 L11 M4 M5 M6 M7 M10 M11 N5 N11 N12 P11 C USB_CVDD AM1802BZWTD3 M12 XDS_1V2 XDS_1V2 RSV2(VPP) T19 TP32 U15-16 PLL0_VDDA12 FB18 3 0.47uF L15 N15 AM1802BZWTD3 2 C385 25V 100nF M3 XDS_1V2 E5 H14 N7 1 C382 25V 100nF NC.M3 NOT USED U15-13 XDS_1V8 C364 25V 100nF SATA_VSS.1 SATA_VSS.2 SATA_VSS.3 SATA_VSS.4 SATA_VSS.5 SATA_VSS.6 U15-11 AM1802BZWTD3 XDS_1V8 C387 25V 100nF DVDD3318_B.1 DVDD3318_B.2 DVDD3318_B.3 DVDD3318_B.4 DVDD3318_B.5 DVDD3318_B.6 DVDD3318_B.7 DVDD3318_B.8 DVDD3318_B.9 DVDD3318_B.10 DVDD3318_B.11 L1 4 C396 10V 22uF SATA_RXP XDS_VCC3V3 U15-7 L2 C421 25V 10nF C422 25V 100nF PLL0_VDDA12 RTC_CVDD L14 PLL1_VDDA12 XDS_1V8 FB5 NU DDR_DVDD18 220_100MHz B M17 M15 FB15 U15-14 PLL0_VSSA12 B PLL1_VSSA12 BLM31PG500SN1L DDR PHY DOES NOT REQUIRE POWER IF NOT USED, PER DATA SHEET, BUT NOT A TYPICAL USE CASE. N6 N9 N10 P7 P8 DDR_DVDD18.1 DDR_DVDD18.2 DDR_DVDD18.3 DDR_DVDD18.4 DDR_DVDD18.5 AM1802BZWTD3 DDR_DVDD18.6 DDR_DVDD18.7 DDR_DVDD18.8 DDR_DVDD18.9 DDR_DVDD18.10 P9 P10 R7 R8 R9 AM1802BZWTD3 NOT USED Project K2E EVM A Designed for TI by eInfochips Title XDS200 POWER Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 35 of 37 A 5 4 3 2 1 D D XDS200 CPLD XDS_VCC3V3 C349 25V 100nF XDS_1V8 C362 25V 100nF C350 10V 2.2uF C354 25V 100nF XDS_VCC3V3 CPLD_D0 CPLD_D1 CPLD_BIO_4 CPLD_BIO_0 CPLD_BIO_1 CPLD_BIO_2 BI BI BI BI BI BI uTDI uTMS uTRSTn uTCK 44 43 42 41 40 39 38 37 36 35 34 [33] [33] [33] [33] [33] [33] XDS_VCC3V3 [32] [32] CPLD_TXD1 CPLD_RXD1 BI BI R349 R364 47E 47E CPLD_BIO_3 CPLD_BIO_4 [33] [33] [33] CPLD_BIO_3 CPLD_A0 CPLD_A1 BI BI BI [33] [33] CPLD_A2 CPLD_A3 BI BI [33] [34] [34] [34] CPLD_CSn CPLD_TDI CPLD_TMS CPLD_TCK BI IN IN IN 1 2 3 4 5 6 7 8 9 10 11 IO12_7 IO12_8 IO2_9 GND1 IO12_10 IO12_11 VCCIO1 IO12_12 TDI TMS TCK IO21_5 IO21_6 IO21_7 IO21_8 IO21_9 IO21_10 IO21_11 VCCIO2 GND3 TDO IO21_12 XDS_1V8 33 32 31 30 29 28 27 26 25 24 23 uEMU0 uEMU1 uSRSTn uTMSK uEXP0 uEXP1 uEXP2 XDS_VCC3V3 R122 0E NU R123 0E R657 uEXP3 IN CPLD_TDO [34] IO12_13 IO12_14 IO12_15 VCC18 IO12_16 GND2 I_2 IO21_16 IO21_15 IO21_14 IO21_13 XDS_VCC3V3 R350 2.2K R351 1K uRTCK uTDO SPARE0 SPARE1 uTDIS BI BI BI R347 1K 1% TP27 470E TP28 uEXP2 R121 470E TP29 uEXP3 R124 470E TP31 uTRSTn R376 uTMS R369 uTMSK 12 13 14 15 16 17 18 19 20 21 22 CPLD_RDn CPLD_RESETn CPLD_WEn 470E R120 C XC2C64A-5-VQ44 10K [33] [33] [33] R119 uEXP1 U9 IO12_6 IO12_5 IO12_4 IO12_3 IO12_2 IO12_1 IO21_1 IO21_2 IO21_3 VCCAUX IO21_4 C uEXP0 XDS_1V8 R118 47E T_TRST_N 47E T_TMS OUT XDS200_TRST# OUT XDS200_TMS OUT XDS200_TDI [15] XDS_VCC3V3 [15] 10K R367 uTDI R366 47E T_TDI uTDIS R370 47E T_TDIS C358 uTDO R380 47E T_TDO 1nF 50V uTCK R382 47E T_TCK uRTCK R383 47E T_RTCK uSRSTn R117 470E T_SRST_N uEMU0 R115 470E T_EMU0 uEMU1 R116 470E T_EMU1 NU [15] 10K IN OUT IN XDS200_TDO XDS200_TCK [15] XDS_RTCK [15] OUT TRGRSTZ OUT XDS200_EMU0 [15] OUT XDS200_EMU1 [15] TP15 REV-B [15] [15,27] TP20 TP18 XDS_VCC3V3 1% B B CPLD_TCK CPLD_TMS CPLD_TDI CPLD_TDO 1 TP14 T-hole TP13 TP12 TP11 TP30 TP10 NU R354 10K R356 1K 1% XDS_VCC3V3 Project K2E EVM A Designed for TI by eInfochips Title XDS EMULATION Size C Document Number Rev 16_00175_02 2.01 Date: Wednesday, May 14, 2014 5 4 3 2 Sheet 1 36 of 37 A 5 4 3 2 1 K2E EVM - REVISION HISTORY 1.0 DATE CHANGE DESCRIPTION PCB REV. SCH. REV. 1.0 Released to Fabrication AUTHOR 15-NOV-2013 eInfochips 03-JAN-2014 eInfochips 21-JAN-2014 eInfochips 25-FEB-2014 eInfochips D D 1.01 1) LM26430: Pin#39 and #44 swapped - R575 marked as NU 2) CDCM6208V1: CLK_RSTz connection near to U17 is corrected - R601/R602 added on U17.Sec input - SGMIICLKP/N shifted to Y5 from Y1 3) BMC: DSP_PMBUS_EN changed to PF0 from PE2 4) XDS200: Added a SDRAM & related circuitry - U20 part# changed to TPS650006, fixed version of TPS65000, Changed R185, R194, R202 to 0E and Marked R180, R196, R199, C100 as NU 5) Power: R603 added, R604 - R610 added and marked them as NU 1) Power: R611, R612 (NU) added on LM10011 Mode pin 2) TA: IC part# changed to TPS544C24 in place of TPS544B24 - R268 changed to 127K, R590 changed to 215K, R587 changed to 6.81K - TP added near to R547 on VSSCMON signal - RC Snubber package size changed 3) LM26430: TP added on CE pin 4) CP2105: Added support for Self-Power operation 1.02 2.0 1) 2) 3) 4) 5) 6) 7) 1.03 C LEDs: R47,R71 and R73 values changed to 120E Added AC termination on MDC and MDIO (NU) signals near AMC EDGE connector and RTM connector Configured PHY1 and PHY2 to operate at 2.5V I/O. Added 2.5V LDO for PHY I/O Added buffer on SGMII and XFI MDC signals and added pull-up on MDIO signals U79 added for PMBUS_ALERT signal connection to SoC SoC RSVxxx pin net names changed 1.04 - Released for Fabrication 05-MAR-2014 eInfochips 2.0 - Block Diagram, aesthetical changes made 10-MAR-2014 eInfochips 2.01 - 24-APR-2014 eInfochips Added 10K pull up resistor on “MMC_EN_N” signal Mounted 4.7K pull down resistors on R606,R607,R604,R609,R610,R608 Removed 10K pull up resistor and added 10K pull down resistor on “uTDIS” signal at XDS200 CPLD. Added 10K pull down resistor on "MAIN_POWER_GOOD" signal Changed R590 resistor value to 182K C B B Front panel and ESD Strip Dummy Components DM9 AMC Hole STC02SYAN Power Adaptor LAN cable Thermal Module DM11 DM12 R1 10M 5% R2 TRIP1 1 1 DM13 4 DM14 NU 0E 10M 5% Board Screw Board Screw Board Screw Board Screw DM10 DM5 NU 0E R4 H4 H6 UART Custom Cable R3 DM17 H27P35-MTH TRIP3 DM8 3 DM7 CN9(1-2)1 TRIP2 DM4 2 DM3 TRIP1 DM2 1 DM6 DM1 H107x17-NPTH <Characteristic> ESD1 AMC-ESD-B USB miniB cable Universal Travel Adaptor Board Stud USB Memory Stick Board Stud Board Stud Board Stud Project A DM15 GoldTech_SOCKET Mounting Holes KEY ZONE NU H2 H3 CN2 1 1 DM18 Screw Hold FM5 FM6 FM3 FM2 Fiducial Fiducial Fiducial Fiducial FM1 FM4 Fiducial Fiducial 1 H35-NPTH <Characteristic> H35-NPTH <Characteristic> H5 H1 Title NPTH Size C Document Number Rev 16_00175_02 2.01 1 H35-NPTH <Characteristic> 5 Designed for TI by eInfochips REVISION HISTORY 2 Board Screw 1 K2E EVM On Board Fiducials 4 H35-NPTH <Characteristic> 5223957-3 <Characteristic> Date: Wednesday, May 14, 2014 3 2 Sheet 1 37 of 37 A