MD2131DB2 Demonstration Board User's Guide

Supertex inc.
MD2131DB2
MD2131 Ultrasound Beamforming
Transmitter Demoboard with Coupled Inductor
Introduction
beamforming phase angles and apodization amplitudes.
The MD2131 is a high speed, arbitrary waveform, push-pull
source driver. It is designed for medical ultrasound imaging
and HIFU beamforming applications. It also can be used
in NDT, sonar and other ultrasound phase-array focusing
beamforming applications.
The integrated circuit (IC) consists of the CMOS digital
logic input circuits, an 8-bit current DAC for the waveform
amplitude control, and four PWM current sources. These
current sources are constructed with the high speed inphase and quadrature current switch matrix and the built-in
sine and cosine angle-to-vector look-up table. The angular
resolution of the vector table is 7.5 degrees per step with a
total range of 48 steps. There are four logic input signals to
control the in-phase and quadrature PWM push-pull current
source’s output timing frequency cycle in the burst and
waveform envelope.
The MD2131’s output stage is designed to drive two
depletion mode, high voltage, Supertex DN2625 MOSFETs
as a source driver. The MOSFET drains are connected to a
center-taped or coupled-inductor, then to the high voltage
supply. One of the DN2625 drains then can capacitor coupled
to the ultrasound transducer piezo load via a cable. The
MD2131 has a high speed serial data interface that quickly
updates the data register’s per-scan-line for changing the
General Description
This MD2131DB2 datasheet describes how the demoboard
is to used to generate the ultrasound transmit beamforming waveform with the Gaussian profile, and the adjustable
frequency, amplitude and phase angle. It also provides information about how to design a user application circuit and
PCB using the Supertex MD2131 and DN2625 devices.
The MD2131DB2 circuit uses two depletion-mode MOSFETs
in the push-pull mode to drive the center tapped, coupled,
RF power inductor. The two depletion-mode MOSFETs are
packaged in a single 5x5mm DFN package. The sources
of the MOSFETs are directly driven by the MD2131’s two
outputs, whose maximum peak sinking current is up to
3.0A. These current source outputs are controlled by the
MD2131’s internal angular vector switch matrix and the inphase and quadrature PWM input signals.
All of the MD2131’s logic control signals are generated by
two small CPLD programmable logic circuits clocked by an
on-board 160MHz crystal oscillator. The CPLD circuits not
only generate accurate timing for the high speed PWM control waveforms, but also the serial data and clock to set and
change the waveform amplitude DAC and phase angle data
registers.
Demoboard Block Diagram
+3.3V
VCC
EXTRG
CPLD
OSC
CLKIN
DIS
Wave
Freq
Ampl
Phase
ENA
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VCCIO
EXTRG
EXCLK
160MHz
+2.5V JTAG
EN
IA
QA
IB
QB
SDI
SDO
SCK
CS
LD
PHO
DAC
PWR
EN
+2.5V +5.0V
VLL
VDD PB
MD2131
GND
RFB PA
+5.0V +3.3V
XDCX
DN2625
+70 to 100V
VPP
C7
L1
6.8µH
3A
DN2625
+5.0V +3.3V
Transformer vs.
Coupled Inductor
Supertex inc.
www.supertex.com
MD2131DB2
The external clock input can be used if the on-board oscillator is disabled. The external trigger input can be used
to synchronize the burst waveforms’ launch timing. There
are five push buttons for enabling and selecting the output
wave-form frequency, phase angle and amplitude. Four
color LEDs indicate the power, chip enable and waveform
parameter selection states.
High speed PCB trace design practices that are compatible with operating speed of about 100 to 200 MHz are used
for the demoboard PCB layout. The internal circuitry of the
MD2131 can operate at quite a high frequency, with the primary speed limitation being load capacitance. Because of
this high speed, and the high transient currents that result
when driving even very small inductive loads, ringing and
even oscillations are possible. The supply voltage bypass
capacitors and the MOSFET gate decoupling capacitors
should be as close to the pins as possible. The capacitor’s
ground pin pads should have low inductance feed-through
connections that are connected directly to a solid ground
plane. The VDD and VPP supplies can draw fast transient
currents of up to 3.5A, so they should be provided with a low
impedance bypass capacitor at the chip’s pins. A ceramic
capacitor of 0.1 to 1.0μF may be used. Minimize the trace
length to the ground plane, and insert a ferrite bead in the
power supply lead to the capacitor to prevent resonance in
the power supply lines.
The MD2131DB2 output waveforms can be displayed by using an oscilloscope and the high impedance probe at the
TP13 test point. It also can use an SMA to BNC, 50Ω, coaxial cable to directly connect to an oscilloscope, with an attenuation of 5:1 if R10 is 200Ω. A cable can also be used to
directly drive the user’s transducer. Jumper J4 can be used
to select whether or not to connect the on-board equivalent
load, which is formed by a 220pF capacitor in parallel with a
1.0kΩ resistor.
Circuit Design & PCB Layout
The thermal pad at the bottom of the MD2131 package must
be connected to the VSUB pin on the PCB. The VSUB is
connected to the IC’s substrate. It is important to make sure
that the VSUB is well grounded. A proper supply voltage
power-up sequence is needed to test the circuit. To prevent
any supply voltage polarity reversing, the circuit also has the
protection of Schottky diodes D7, D8 and D9.
When using multiple MD2131 ICs in applications that are
sensitive to jitter and noise, insert another ferrite bead between VDD, and decouple each chip supply separately. Pay
particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance, not only on the supply pins but also on the CA/B and KA/B compensation pins.
Very closely placed surface mount components are highly
recommended. Be aware of the parasitic coupling from the
high voltage outputs to the input signal terminals of MD2131.
This feedback may cause oscillations or spurious waveform
shapes on the edges of signal transitions. Since the input
operates with signals down to 2.5V, even small coupling voltages may cause problems. The use of a solid ground plane
and good power and signal layout practices will prevent this
problem. Also ensure that the circulating ground return current from a capacitive load cannot react with common inductance to create noise voltages in the input logic circuitry.
Due to the high current and high current slew rate nature
of this common gate, source driven and push-pull circuit
topology, the two cascading N-channel MOSFETs need to
have very low lead inductance. The DN2625D MOSFET is
designed for this application and works seamlessly with the
MD2131. In particular, a good PCB layout design needs to
shorten the traces between the MD2131 output pins and
DN2625D source pins. It is also necessary to connect all
three pairs of pins between them for the high current carrying capacity. Furthermore, because of the high di/dt in the
output current of the MD2131, it is also necessary to have
the Schottky diodes D5 and D6 from the driver output pins
to the +5.0V power supply line as the clamping diodes. Note
that the diodes must have enough speed and peak current
capability. The RC snubber circuits of R8-C5 and R15-C28
at the output pins can effectively dump the current pulse
edge ringing.
This MD2131DB2 beamforming demoboard should be powered up with multiple DC power supplies with current limiting
functions. The power supply voltages and current limits used
in the testing are listed on page 11. There are examples of
the MD2131DB2 demoboard input and output waveform and
measurements shown in Figures 1 to 3.
PCB designers need to pay attention to some of the connecting traces as high voltage and high speed traces. In particular, low capacitance to the ground plane and more trace
spacing need to be applied in this situation.
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Supertex inc.
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MD2131DB2
Select the Coupled Inductor and Output Ca- Demo Load Emulation Circuitry
pacitor
The 3.3µH inductor L2 is part of the demo load emulation
The a center-taped or coupled-inductor is needed for the
push-pull output circuit working. The inductor serves at least
two functions: the differential current-mirroring of the two
DN2625 output drain signals from one arm to the other, very
similar to the transformer functions. But the AC coupling and
isolation barrier to the ultrasound probe is provide by a high
voltage capacitor C40 to the cable and transducer element.
circuit, along with 220pF capacitor C19 and 1k resistor R13.
These three components are only here as an 8 to12MHz
circuitry to emulate the transducer PZT element, and their
values are selected only to work well with the programmed
demo waveforms in the CPLD devices when the demoboard
was tested. These components should be disconnected
when user’s transducer is connected to the output SMA connector J4.
The MD2131 PWM clock may operate at a 40 to 160MHz
frequency range, however the coupled inductor only needs
to work in the frequency band of the ultrasound being transmitted. Beside the bandwidth consideration, the inductor
also needs enough peak current capacity and coupling efficiency at RF to make sure the ferrite magnetic core will not
be saturated, and it must have low leakage inductance. The
output coupling capacitor must be of the high voltage type.
In the case of 100V VPP, a 200V or higher working voltage
rating is necessary.
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Supertex inc.
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MH2
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
3
2
3
2
CC
DD
EE
FF
GG
HH
II
JJ
KK
LL
MM
NN
MH3
36
40
32
29
28
33
8
38
42
1
41
34
TP2 TP3
R7
50
MH4
VCC
U3
XC9572XL_VQ44
AA 44
1
39
EXTRG
43
CLKIN
J3
EXTRG
R2
50
BB 37
4
GND
17
GND
25
GND
PH0
DAC
PWR
NC1
NC2
NC3
NC4
NC5
MH1
2
3
5
6
7
26
NC9
NC8
NC7
NC6
EN
C6
0.1
2
SDI
SDO
SCK
CS
LD
VCCIO
31
30
27
35
15
LED1
LED2
PWR
VCC
VCC
TMS
TDI2
TDO2
TCK
10
9
24
11
C29
0.1
16
23
14
13
22
3
SDI
SDO
SCK
CS
LD
EN
TP20
VCC
C8
0.1
C7
0.1
18
20
19
21
12
OUT
GND
X1
FXO-HC73-160
1
4
EN
VCC
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
36
40
32
29
28
33
8
38
42
1
41
34
C1
0.1
VLL
VCC
R17 33k
R22 200
2
1
SW1
TP4 TP5
C
D
E
F
G
H
I
J
K
L
M
N
37
J2
EX = 0
C31 0.1
R19 33k
R24 200
R18 33k
R23 200
D4
YLW
VCC
U2
XC9572XL_VQ44
A 44
B
4
GND
17
GND
25 GND
SW3
J6
JTAG
R3
1k
D1
YLW
R4
1k
D2
RED
R5
1k
D3
GRN
14
23
16
22
18
20
19
21
12
C10
0.1
VCC
D7A
D7B
VDD
LD
CS
SCK
SDO
SDI
EN
EN
TP1
TP10
21
EN
15
IB
13 QB
14
IA
12
QA
C12
0.1
TP21 VLL
3
+
R27
0
J7
C2
0.1
+ C33
10
16V
U4
2 LM4040
1
(+3.3V)
(+5.0V)
VCC VGG VDD
C24
0.1
R14
200
20 LD
9 DGND
TP15 11
SDI
18 SDO
TP14
10 SCK
TP18
19 CS
C32
10
16V
VDD
R6
1k
PWR
TP16
TP6
TP12
TP7
TP9
TP8
C11
0.1
DAC
C20
0.1
U 13
V
X
Y
Z
IB
QB
IA
QA
EN
C9
0.1
PH0
1
2
35
VCC
26
VCC 15
VCC
TMS
TDI1
TDO1
TCK
10
9
24
11
1
2
3
4
5
6
R1
1k
SW2
C30 0.1
R25 200
R20 33k
SW5
C38 0.1
SW4
C37 0.1
43
CLKIN
39
EXTRG
31
30
27
2
3
5
6
7
R21 33k
R26 200
C35 0.1
1
2
6
1
NC12
NC11
NC10
1
2
3
WAV
FRE
PHASE
AMPL
ENA
1
2
4
C13
27nF
C3
0.1
C4
0.1
U1
MD2131K7
C14
27nF
VDD
D9
B1100-13
D8A
C26
27nF
C25
27nF
R16
49.9k
41
VSUB
4
GND
2
GND
8
VLL
VREF
22
16
VDD
5
VDD
26
VDD
7
GND
23
RFB
40
C2A
C3B
6
1
17 AGND
1
2
3
4
5
6
C3A
GND
24
VDD
TP17
TP11
PA
1
R8
1.0
1W
7
8
9
10
11
12
C16
0.1
M1B
DN2625DK6
D5B
C5
3.3nF
VDD
C36
1µ
100V
(+70 to 100V)
VPP
C21
27nF
C27
0.1
C28
3.3nF
R15
1.0
1W
3
VCC
C22
0.1
16
15
14
13
PB 34
M1A 6
PB 33
PB DN2625DK6
5
PB 32
3
D6A
D6B
GND
GND
VSUB
VSUB
29
27
36
35
PA 39
38
PA
37
PA
D5A
C15
27nF
C39
0.1
1
1
28
C2B
31
1
25
1
KA
3
C1A
KB
C1B
30
1
6
3
4
4
4
2
2
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3
4
2
C40
10nF
250V
OUT1
8-11MHz
Demo Load
R12
100
1W 1
R9
100
1W
L1
6.8µH
3 3A
1
OUT2
U5
ADP3339AKC-2.5RL7
IN
C23
0.1
(+3.3V)
VGG
D2
VPP
R11
0
C18
1µ
100V
D1
C17
0.1
(+3.3V)
VGG
2
4
+
4
3
2
3
(+2.5V)
VLL
1
D8B
R13
1k
1W
R10
200
R28
0
OUT1
TP19
C19
220p
250V
C34
10
16V
2
4
J4
L2
3.3µH 3A
1
3
TP13
J5
XDCR-A
Circuit Schematic
4
J1
EXCLK
MD2131DB2
Supertex inc.
www.supertex.com
MD2131DB2
PCB Layout
MD2131DB2
Actual Dimensions: 10.2cm x 7.6cm (4.00” x 3.00”)
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MD2131DB2
MD2131DB2 Waveforms
Figure 1:
The output waveforms of 12-sample/cycle at 12.45MHz, 135deg, DAC = 255, VPP = 100V,
220pF//1kΩ load.
Figure 2:
The output waveforms of 16-sample/cycle at 10MHz, 45deg, DAC = 255, VPP = 100V, 220pF//1kΩ
load.
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MD2131DB2
MD2131DB2 Waveforms
Figure 3:
The output waveforms of 20-sample/cycle at 8.0MHz, 135deg, DAC = 255, VPP = 100V,
220pF//1kΩ load.
Output Waveform Frequency Selection Table
Samples / Cycle of Ultrasound Output Waveform
Output
Frequency
12 s/c
16 s/c
20 s/c
Frequency
13.3MHz
10.0MHz
8.0MHz
Note:
fCLKIN = 160MHz
Output Waveform Phase Angle Selection Table
Phase Angle Steps (PHASE Button)
0
1
0
(power on, LED1 on)
7.5
... ...
24
... ...
180
47
48
352.5
360
Note
Output
Phase Angle Degree
Output Waveform Amplitude Selection Table
Amplitude Steps (AMPL Button)
0
1
0
16
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... ...
8
... ...
128
(power on,
LED2 on)
7
15
16
240
255
Note
DAC Register Value
Supertex inc.
www.supertex.com
MD2131DB2
Board Connector and Test Pin Description
CPLD
Pin #
Signal Name Description
U2, 3 - 15, 26, 35
VCC
CPLD logic power supply +3.3V
U2, 3 - 26
VLL
CPLD, VCCIO and MD2131 logic power supply +2.5V
U2, 3 - 4, 17, 25
GND
Logic power ground 0V
U2 - 2
WAV
Run or stop demo waveform phase
U2 - 3
FRE
Selecting frequency: 8,10 and 13.3MHz
U2 - 5
PHASE
Single step phase change, angle stepping:0, 7.5, 15…360
U2 - 6
AMPL
Single step amplitude change, DAC stepping: 15, 31…255
U2 - 7
ENA
U2 - 18
IA
Output signal to MD2131 IA
U2 - 19
IB
Output signal to MD2131 IB
U2 - 20
QA
Output signal to MD2131 QA
U2 - 21
QB
Output signal to MD2131 QB
U3 - 31
LED1
Output signal yellow, PH0 LED is on when phase = 0
U3 - 30
LED2
Output signal yellow, DAC LED is on when DAC = 127
U3 - 27
PWR
Output signal LED green, indicates +3.3V power supply on
U2, 3 - 10
TMS
Test mode select of JTAG
U2, 3 - 9
TDI
Test data in of JTAG, two CPLD in daisy chain
U2, 3 - 24
TDO
Test data out of JTAG, two CPLD in daisy chain
U2, 3 - 11
TCK
Test clock of JTAG
U2, 3 - 43
CLK
CPLD clock input
U2, 3 - 39
EXTRG
U2, 3 - 12
EN
Output signal LED red, indicates MD2131 is enabled
U3 - 22
SDI
Output signal to MD2131 SDI
U3 - 16
SDO
Input signal from MD2131 SDO
U3 - 23
SCK
Output signal to MD2131 SCK
U3 - 14
CS
Output signal to MD2131 CS
U3 - 13
LD
Output signal to MD2131 LD
All remaining pins
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Control MD2131 EN pin
External trigger signal input to control waveform timing
NC or Reserved
8
Supertex inc.
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MD2131DB2
CPLD Programming Connector
JTAG Pin #
Signal Name
Description
J6 - 1
TMS
Test mode select of CPLD
J6 - 2
TDI
Test data In of CPLD
J6 - 3
TDO
Test data out of CPLD
J6 - 4
TCK
Test clock of CPLD
J6 - 5
GND
Logic power supply ground 0V for programming only
J6 - 6
VCC
Logic power supply +3.3V for programming only
Test Signal Connector
SMA &
Jumper
Signal Name Description
External clock input when on-board oscillator is disabled, or output the clock when it is
enabled
J1
EXCLK
J2
OSC_EN
J3
EXTRG
External trigger signal input, 0V to 3.3V square wave, 10KHz to 40KHz only
J4
Load JP
Jumper for on-board RC load to MD2131DB2 high voltage output and XDCR connector
J5
XDCR
Jumper for on-board oscillator, short = disable, open = enabled
MD2131DB2 waveform output, for SMA-cable to oscilloscope, high voltage!
0 to +/-350Vp-p max
Power Supply Connector
Power
Supply Pin #
Signal Name Description
J7 - 1
VCC
J7 - 2
GND
J7 - 3
VDD
J7 - 4
GND
J7 - 5
VPP
+3.3V, CPLD control logic supply voltage with current limit to 250mA
Ground reference, 0V
+5.0V MD2131 positive supply voltages with current limit to 50mA
Ground reference, 0V
+70 to100V, the high voltage supply with current limit to 30mA
Voltage Supply Power-Up Sequence
Step
Signal Name Description
1
VDD
+5.0, MD2131 positive supply voltages
2
VCC
+3.3V, MOSFET gate biasing and CPLD control logic supply voltage
3
VPP
+70V to 100V, the high voltage supply
4
EN
Logic Active
Enable logic control, active-high signal to MD2131
1
EN
Logic Active
Disable logic control, active-high signal to MD2131
2
VPP
+70V to 100V, the high voltage supply, off
3
VDD
+5.0V, MD2131 positive supply voltages with all input signals LOW, off
4
VCC
+3.3, CPLD control logic supply voltage with EN = 0, off
Power-Down
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MD2131DB2
MD2131DB2 Bill of Materials
Reference
Description
Manufacturer’s
Part Number
Manufacturer
C1 - C12
Capacitor, 0.1µF, 25V, ceramic, X7R, 0603
ECJ-1VB1E104K
Panasonic
C13, C14, C15
Capacitor, 0.027µF 50V ceramic, X7R 0603
ECJ-1VB1H273K
Panasonic
C18, C36
Capacitor, ceramic, 1.0µF 100V X7R 20% 1210
C3225X7R2A105M
TDK
C19
Capacitor, ceramic, 220pF 200V NP0 0805
ECJ-2YC2D221J
Panasonic
C32, C33, C34
Capacitor, 10µF 16V ELECT WT SMD
UWT1C100MCL1GB
Nichicon
C5, C28
Capacitor, ceramic, 3300pF, 10%, 100V, X7R, 0603
06031C332KAT2A
AVX
D1, D4
LED: yellow, diff, 0805, SMD
SML-LXT0805YW-TR
Lumex
D2
LED: red, diff, 0805, SMD
SML-LXT0805IW-TR
Lumex
D3
LED: green, diff, 0805, SMD
SML-LXT0805GW-TR
Lumex
D9
Diode Schottky, 100V, 1.0A, SMA
B1100-13
Diodes Inc.
D5 - D8
Diode Schottky, dual, 30V, SOT-363
BAT54DW-7
Diodes Inc.
L1
6.8µH coupled inductor (6x6x3.5mm)
LPD6235-682MEB
Coil Craft
L2
3.3µH 3A (as part of dummy load)
7447785003
Würth
M1
Dual depletion 250V 3.0A N-MOSFET, 5x5mm,
8-Lead DFN package
DN2625DK6-G
Supertex Inc.
R1
RES 1.00kΩ 1/16W 1% 0603 SMD
ERJ-3EKF1001V
Panasonic
R2, R7
RES 49.9Ω 1/16W 1% 0603 SMD
ERJ-3EKF49R9V
Panasonic
R3 - R6, R10,
R14, R22 - R26
RES 200Ω 1/16W 1% 0603 SMD
ERJ-3EKF2000V
Panasonic
R8, R15
RES 1.0Ω 1W 1% 2512 SMD
ERJ-1TRQF1R0U
Panasonic
R9, R12
RES 100 OHM 1W 1% 2512 SMD
ERJ-1TNF1000U
Panasonic
R11, R27
PCB copper short
NA
NA
R13
RES 1kΩ 1W 1% 2512 SMD
ERJ-1TYF102U
Panasonic
R16
RES 49.9kΩ 1/16W 1% 0603 SMD
ERJ-3EKF4992V
Panasonic
R17, R18, R19,
R20, R21
RES 33.2kΩ 1/16W 1% 0603 SMD
ERJ-3EKF3322V
Panasonic
R28
PCB copper short
NA
NA
U1
IC ultrasound beamforming source driver
5x5mm 40-Lead QFN package
MD2131K7-G
Supertex Inc.
U2, U3
IC CPLD, 72 MCELL, C-Temp, 44-VQFP
XC9572XL-5VQ44C
Xilinx
U4
IC precision reference micropower ref, SOT-23
LM4040DEM3-2.5
National
U5
IC voltage regulator, 1.5A, 2.5V, SOT-223
ADP3339AKC-2.5
ADI
X1
Oscillator clock, 160.000MHZ, 3.3V, SMD
JITO-2-DC3AE-160
FOX
Electronics
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to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
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