Supertex inc. HV7355DB1 150V, 1.5A, Unipolar Ultrasound Pulser Demoboard General Description The HV7355 is a monolithic eight-channel, high-speed, high voltage, unipolar ultrasound transmitter pulser. This integrated, high performance circuit is in a single, 8x8x0.9mm, 56-lead QFN package. The HV7355 can deliver guaranteed ±1.5A source and sink current to a capacitive transducer with 0 to +150V peak voltage. It is designed for medical ultrasound imaging and ultrasound material NDT applications. It can also be used as a high voltage driver for other piezoelectric or capacitive MEMS transducers, or for ATE systems and pulse signal generators as a signal source. The HV7355’s circuitry consists of controller logic circuits, level translators, gate driving buffers and a high current and high voltage MOSFET output stage. The output stages of each channel are designed to provide peak output currents typically over ±1.5A for pulsing, with up to 150V swings. The upper limit frequency of the pulser waveform is dependent upon the load capacitance. With different capacitance load conditions the maximum output frequency is about 20MHz. This demoboard datasheet describes how to use the HV7355DB1 to generate the basic high voltage pulse waveform as an ultrasound transmitting pulser. The HV7355 circuit uses DC-coupling from a 3.3V logic input to output TX0~7 internally, therefore the chip needs three sets of voltage supply rails: VLL (+3.3V), VDD/VSS (+/-5.0V) and VPP (up to +150V). The VPP high voltage supply can be changed rather quickly, compared to the capacitor gatecoupled driving pulsers. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier. The control signal logic-high voltage should be the same as the VLL voltage of the IC, and the logic-low should be referenced to GND. The HV7355DB1 output waveforms can be displayed using an oscilloscope by connecting the scope probe to the test points TX0~7 and GND. The soldering jumper can select whether or not to connect the on-board dummy load, a 330pF capacitor paralleling with a 2.5kΩ resistor. The test points can be used to connect the user’s transducer to easily evaluate the pulser. Block Diagram +5.0V +3.3V +5.0 to 150V +3.3V AVDD VLL EN EXCLK MC OSC CLKIN 40MHz JTAG LR PWR VSS VDD CWD CPF VPF VPP VPP LT IN0 Waveform Generator CPLD EN VDD VDD Q0 VPF TX0 VDD R2 LT C4 330pF RGND VDD 6 R3 2.5k VPP VPP GND LT IN7 WAVE FREQ SEL EN CW/RTZ CW LR RTZ PWR EN VDD Q7 SET LE Q[7:0] Data Latch CS Shift Register SCK Q7 D0 SDO SDI VPF TX7 VDD LT TX7 RGND RGND SUB VSUB Dummy Load GND VSS -5.0V Doc.# DSDB-HV7355DB1 B070314 Supertex inc. www.supertex.com HV7355DB1 The PCB Layout Techniques This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 3.3V, even small coupling voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Also ensure that the circulating ground return current from a capacitive load cannot react with common inductance to create noise voltages in the input logic circuitry. The large thermal pad at the bottom of the HV7355 package is internally connected to the IC’s substrate (VSUB). This thermal pad should be connected to 0V or GND externally on the PCB. The designer needs to pay attention to the connecting traces on the outputs TX0~7, as the high-voltage and high-speed traces. In particular, controlled-impedance to the ground plane and more trace spacing needs to be applied in this situation. Testing the Integrated Pulser The HV7355 pulser demoboard should be powered up with a DC power supplie that has current limiting functions. High-speed PCB trace design practices that are compatible with about 50 to 100MHz operating speeds are used for the demo board PCB layout. The internal circuitry of the HV7355 can operate at quite a high frequency, with the primary speed limitation being load capacitance. Because of this high speed and the high transient currents that result when driving capacitive loads, the supply voltage bypass capacitors and the driver to the FET’s gate-coupling capacitors should be as close to the pins as possible. The GND pin should have low inductance feed-through via connections that are connected directly to a solid ground plane. The VDD, VSS, VPP and CPP voltage-supply and/or bypass capacitor pins can draw fast transient currents of up to 2.0A, so they should be provided with a low-impedance bypass capacitor at the chip's pins. A ceramic capacitor of 1.0 to 2.0µF may be used. Only VPP to GND capacitors need be high voltage. CPF to VPP capacitors only need be low voltage. Minimize the trace length to the ground plane, and insert a ferrite bead in the power supply lead to the capacitor to prevent resonance in the power supply lines. For applications that are sensitive to jitter and noise when using multiple HV7355 ICs, insert another ferrite bead between each chips supply line. To meet the typical loading conditions, the on-board dummy load 330pF//2.5kΩ should be connected to the high voltage pulser output through the solder jumper when using an oscilloscope’s high impedance probe. To evaluate different loading conditions, the values of the RC within the current and power limit of the device may be changed. In order to drive the user’s piezo transducers with a cable, one should match the output load impendence properly to avoid cable and transducer reflections. A 70 to 75Ω coaxial cable is recommended. The coaxial cable end should be soldered to TX0~7 and GND directly with very short leads. If a user’s load is being used, the on-board dummy load should be disconnected by cutting the small shorting copper trace in between the zeroΩ resistor’s (R2, R12 etc.) pads. They are shorted by factory default. All of the on-board test points are designed to work with the high impedance probe of the oscilloscope. Some probes may have limited input voltage. When using the probe on these high voltage test-points, make sure that VPP voltages do not exceed the probe limit. Using the high impendence oscilloscope probe for the on-board test points, it is important to have short ground leads to the circuit board ground plane. Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of the HV7355’s high voltage power stages is very low, to obtain better waveform integrity at the load terminals after long cables, in some cases it may be desirable to add a small value resistor in series with the outputs TX0~7. This will, of course, reduce the output voltage slew rate at the terminals of a capacitive load. Be aware of the parasitic coupling from the outputs to the input signal terminals of the HV7355. Doc.# DSDB-HV7355DB1 B070314 2 Supertex inc. www.supertex.com 2 C30 0.22 VCC J2 EXCLK J1 C31 0.22 R40 200 C32 0.22 SW2 R26 33k R41 200 SCK SDI SDO SCK CLK R5 1.0k YLW C34 0.22 R28 33k C33 0.22 R42 200 VCC R51 50 R50 50 R49 50 R48 50 R47 50 R8 1.0k R7 1.0k VCC RED D7 GRN D6 W4 ZE;794ZNaXS66 SW4 R27 33k R6 1.0k YLW SW3 TP30 39 40 43 TP13 TP18 3 R20 50 R15 50 R14 1.0k OUT R20 50 R25 33k 1 SW1 2 3 GND EX=0 40MHz X1 2 1 4 EN VCC 1 C18 0.22 VCC R4 1.0k RED 31 D5 R43 200 C35 0.22 SW5 R29 33k IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 C1 022 R45 200 R30 1.0 VCC MH2 TP40 R22 50 R23 50 R36 50 R39 50 R45 50 R46 50 22 21 19 18 14 13 MH3 MH4 MH1 4 5 6 HEADER 6 J4 1 2 3 R38 1.0 C22 0.22 CS SET MC TP3 R35 1.0 R9 1.0k MC LE SET CS SCK SDI TP28 TP25 TP19 TP16 EN LE VPP R21 50 37 VCC R17 50 38 C3 022 VDD VSS R31 1.0 JTAG J3 TP10 TP12 C2 022 1 2 3 4 5 6 TP6 TP9 8 7 6 5 4 3 2 13 15 11 14 9 12 10 1 6 TP2 4 3 C12 1µ D20B VSS SDO MC LE SET CS SCK SDI IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 EN D20A VDD TP17 TP29 TP27 TP22 TP20 1 56 C19 0.22 VCC C14 1µ VDD C13 1µ TP8 48 D4 32 SET 30 WAV 2 FRE 3 SEL 5 ENA 6 MOD 7 LE 4 GND 17 GND 25 GND MC 29 CS 28 EN 35 VCC 26 VCC 15 VCC 1 6 JX9577 D22A VCC 4 3 D22B VDD VSS TP36 VCC C36 1µ C8 1µF TP5 C5 1µF TP35 18 D3 BAT54DW-7 10 TMS 9 TDI 24 TDO 11 TCK 16 VLL 55 GND 57 23 AVDD GND 54 BAT54DW-7 VDD VSS 53 44 RGND 25 RGND 46 RGND BAT54DW-7 17 VDD BAT54DW-7 CPF 49 CPF 21 VPP 20 VPP 2 1 VPP D17 VPP 26 RGND 47 52 VPP 27 RGND 51 VPP RGND B1100-13 C27 C9 1µF 1µF 160V 160V VPP 19 VDD 2 1 D15 VPP TP15 TX7 TX7 TX6 TX6 TX5 TX5 TX4 TX4 TX3 TX3 TX2 TX2 TX1 TX1 TX0 TX0 VPP 50 VPP RGND 24 3 45 RGND 22 VPP Doc.# DSDB-HV7355DB1 B070314 B1100-13 28 29 30 31 32 33 34 35 36 37 38 39 40 41 43 42 TP37 TP24 TP26 TP7 TP32 TP23 VCC = +3.3V VDD/VSS = +/-5.0V VPP = +5.0 to +150V VZ9 VZ8 VZ7 VZ6 VZ5 VZ4 VZ3 VZ2 C6 C28 1µF 1µF 160V 160V TP11 TP1 C37 330pF 250V 0 R53 C23 330pF 250V 0 R52 C24 330pF 250V 0 R37 C7 330pF 250V 0 R10 C29 330pF 250V 0 R23 C21 330pF 250V 0 R18 C20 330pF 250V 0 R12 C4 330pF 250V 0 R2 TP38 R34 2.55k 1W R32 2.55k 1W TP33 TP39 R54 2.55k 1W TP21 R11 2.55k 1W TP34 R24 2.55k 1W TP31 R19 2.55k 1W TP14 R13 2.55k 1W TP4 R3 2.55k 1W HV7355DB1 HV7355DB1 Schematic Supertex inc. www.supertex.com HV7355DB1 HV7355DB1 PCB and Board Layout Actual Board Size: 72.4mm x 68.4mm Power Connector Description 1 VCC +3.3V Logic voltage input for VLL and CPLD. (100mA) 2 GND 3 VDD +5.0V HV7355 positive VDD supply. (25mA) 4 VSS -5.0V HV7355 negative VSS supply. (-25mA) 5 GND 6 VPP 0V, Ground 0V, Ground +10 to +150V positive high voltage supply. (5mA) Voltage Supply Power-Up and Operation Sequence 1 +VCC 2 +VDD / -VSS 3 +VPP +3.3V positive logic supply voltage for HV7355’s VLL and CPLD VCC. ±5.0V positive and negative VDD and VSS power supply. +10 to +150V positive high voltage. Note: Power-down in reverse order Push Button Operations WAV FREQ Toggle select pulse B-mode waveforms: None, 1-cycle, 3-cycles, 7-cycles. Toggle select frequency: 20, 10, 5, 2.5, 1.25 and 0.625MHz when X1 oscillator is 40MHz. SEL Toggle select. Increases the off-time between 2 consecutive pulses. EN Toggle ON or OFF HV7355 chip enable MODE Toggle select between B-mode and CW. LED Indicator SET Set the latch registers of serial interface, when high, all latches are set to logic high. LE Latch enable when low, data can be latched into the registers of serial interface. MC Mode control, high indicates B-mode and low indicates CW. PWR HV7355 VLL 3.3V and CPLD chip VCC power supply indicator. EN HV7355 chip enable signal indicator. Power state initially is OFF until EN is pushed. Doc.# DSDB-HV7355DB1 B070314 4 Supertex inc. www.supertex.com HV7355DB1 Typical Waveforms Figure 1. Input logic and TX output waveforms of 5.0MHz (0 to +150V with 330pF//2.5kΩ load) Figure 2. Rise and fall time at 0 to +150V (with 330pF//2.5kΩ load) Doc.# DSDB-HV7355DB1 B070314 5 Supertex inc. www.supertex.com HV7355DB1 Typical Waveforms (cont.) Figure 3. Multiple channel at 5.0MHz (0 to +150V with 330pF//2.5kΩ load) Figure 4. FFT Plot of Second Harmonic Distortion (HD2) -36dB at 5.0MHz, VPP = 150V (with 330pF//2.5kΩ load) Doc.# DSDB-HV7355DB1 B070314 6 Supertex inc. www.supertex.com HV7355DB1 Typical Waveforms (cont.) Figure 5. Output Waveform at 10MHz and VPP = 120V (with 330pF//2.5kΩ load) Figure 6. Output Waveform at 2.5MHz and VPP = 120V (with 330pF//2.5kΩ load) Doc.# DSDB-HV7355DB1 B070314 7 Supertex inc. www.supertex.com HV7355DB1 Typical Waveforms (cont.) Figure 7. Output Waveform at 20MHz at VPP = 75V (with 330pF//2.5kΩ load) Figure 8. Power on EN chip enable to VPF setting time Doc.# DSDB-HV7355DB1 B070314 8 Supertex inc. www.supertex.com HV7355DB1 Bill of Materials Component Description Manufacturer Part Number C1 - C3, C18, C19, C22, C30 - C35 CAP CER 0.22µF 16V X7R 10% 0603 TDK C1608X7R1C224K C4, C7, C20 - C24, C29, C37 CAP CER 330pF 200V X7R 0603 Panasonic ECJ-1VB2D331K C5, C8, C12, C13, C14, C36 CAP CER 1.0µF 16V X7R 0603 TDK C1608X7R1C105M C6, C9, C27, C28 CAP CER 1µF 100V X7R 20% 1210 TDK C3225X7R2A105M D3, D7 LED THIN 635NM RED DIFF 0805 SMD Lumex SML-LXT0805IW-TR D4, D5 LED THIN 585NM YEL DIFF 0805 SMD Lumex SML-LXT0805YW-TR D6 LED THIN 565NM GRN DIFF 0805 SMD Lumex SML-LXT0805GW-TR D15, D17 DIODE SCHOTTKY 100V 1A SMA Diodes Inc. B1100-13 D20, D22 DIODE SCHOTTKY DUAL 30V SOT-363 Diodes Inc. BAT54DW-7 J1 CONN HEADER 2POS .100 VERT GOLD Molex 22-28-4023 J2 CONN JACK END LAUNCH PCB GOLD SMA Johnson 142-0711-821 J3 CONN HEADER 6POS .100 VERT GOLD Molex 22-28-4063 J4 CONN HEADER 10POS .100 VERT GOLD Tyco 1-640454-0 R2, R10, R12, R18, R23, R37, R52, R53 Solder Gap (SHORT) NA NA R3, R11, R13, R19, R24, R32, R34, R54 RES 2.55kΩ 1W 1% 2512 SMD Panasonic ERJ-1TNF2551U R4, R5, R6, R7, R8, R9, R14 RES 1.00kΩ 1/16W 1% 0603 SMD Panasonic ERJ-3EKF1001V R15 - R17, R20 - R22, R33, R36, R39, R45 - R51 RES 49.9Ω 1/16W 1% 0603 SMD Panasonic ERJ-3EKF49R9V R25, R26, R27, R28, R29 RES 33.2kΩ 1/16W 1% 0603 SMD Panasonic ERJ-3EKF3322V R30, R31, R35, R38 RES 1.00Ω 1/10W 1% 0603 SMD Rohm MCR03EZPFL1R00 R40, R41, R42, R43, R44 RES 200Ω 1/16W 1% 0603 SMD Panasonic ERJ-3EKF2000V SW1, SW2, SW3, SW4, SW5 SWITCH LT 4.7MMX3.5MM 100GF SMD Panasonic EVQ-P2002M TP3, TP15 TEST POINT PC MULTI PURPOSE BLK Keystone 5011 U2 IC CPLD 72 MCELL C-TEMP 44-VQFP Xilinx XC9572XL-5VQ44C U3 IC HV7355K6-G 4-ch RTZ Supertex Inc. HV7355K6-G X1 OSC CLOCK 40.000MHz 3.3V SMD CTS CB3LV-3C-40.0000-T Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSDB-HV7355DB1 B070314 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com