HGTD8P50G1, HGTD8P50G1S 8A, 500V P-Channel IGBTs March 1997 Features Package JEDEC TO-251AA • 8A, 500V • 3.7V VCE(SAT) • Typical Fall Time - 1800ns EMITTER COLLECTOR GATE • High Input Impedance (FLANGE) COLLECTOR • TJ = +150oC Description JEDEC TO-252AA The HGTD8P50G1 and the HGTD8P50G1S are P-channel enhancement-mode insulated gate bipolar transistors (IGBTs) designed for high voltage, low on-dissipation applications such as switching regulators and motor drives. This P- channel IGBT can be paired with N-Channel IGBTs to form a complementary power switch and it is ideal for half bridge circuit configurations. These types can be operated directly from low power integrated circuits. (FLANGE) COLLECTOR GATE EMITTER PACKAGING AVAILABILITY PART NUMBER PACKAGE Symbol BRAND HGTD8P50G1 TO-251AA G8P50G HGTD8P50G1S TO-252AA G8P50G C NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., HGTD8P50G1S9A. G E The development type number for these devices is TA49015. Absolute Maximum Ratings TC = +25oC, Unless Otherwise Specified Collector-Emitter Breakdown Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BVCES Emitter-Collector Breakdown Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BVECS Collector Current Continuous At TC = +25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC25 At TC = +90oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC90 Collector Current Pulsed (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICM Gate-Emitter Voltage Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGES Gate-Emitter Voltage Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGEM Switching SOA at TC = +25oC, VCL = -350V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SSOA No Snubber, Figure 17 - Circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . With 0.1µF Capacitor, Figure 17 - Circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation Total at TC = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Power Dissipation Derating TC > +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Lead Temperature for Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (0.125" from case for 5s) NOTE: HGTD8P50G1/G1S -500 10 UNITS V V -12 -8 A A -18 ±20 ±30 A V V -3 -18 66 0.53 -40 to +150 +260 A A W W/oC oC oC 1. TJ = 25oC, VCL = 350V, RGE = 25Ω, Figure 17 - Circuit 2 (C1 = 0.1µF) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 3649.3 Specifications HGTD8P50G1, HGTD8P50G1S Electrical Specifications TC = +25oC, Unless Otherwise Specified PARAMETERS SYMBOL Collector-Emitter Breakdown Voltage BVCES ICE = -250µA VCL = -600V Emitter-Collector Breakdown Voltage BVECS Collector-Emitter Leakage Current Collector-Emitter Saturation Voltage ICES VCE(SAT) TEST CONDITIONS MIN TYP MAX UNIT VGE = 0V -500 - - V IEC = 1mA VGE = 0V 10 - - V VCE = BVCES TC = +25oC - - -250 µA VCE = 0.8 BVCES TC = +150oC - - -1.0 mA ICE = -3.0A VGE = -15V TC = +25oC - -2.5 -2.9 V TC = +150oC - -2.3 -2.8 V TC = +25oC - -3.0 -3.7 V TC = +150oC - -3.3 -4.0 V -4.5 -6.0 -7.5 V - - ±100 nA ICE = IC90 VGE = -15V Gate-Emitter Threshold Voltage VGE(TH) ICE = -1.0mA Gate-Emitter Leakage Current IGES VGE = ±20V Gate-Emitter Plateau Voltage VGE(PL) IC = 3A VCE = 0.5 BVCES - -7.0 - V On-State Gate Charge QG(ON) IC = 3A, VCE = 0.5 BVCES VGE = -15V - 16 25 nC VGE = -20V - 22 30 nC ICE = -3A, VGE = -15V VCE = -350V RG = 25Ω TJ = +150oC Fig. 17, Circuit 1 - 45 - ns - 85 - ns - 480 680 ns tFI - 1800 2500 ns EOFF - 0.8 - mJ - 100 200 ns - 3500 4000 ns - 1.3 - mJ -3 - - A - 1.75 1.90 oC/W Current Turn-On Delay Time Current Rise Time Current Turn-off Delay Time Current Fall Time Turn-Off Energy (Note 1) Current Turn-Off Delay Time Current Fall Time Turn-Off Energy (Note 1) Latching Current Thermal Resistance tD(ON)I RL = 113Ω tRI tD(OFF)I tD(OFF)I L = 100µH L = 100µH ICE = -8A, VGE = -15V VCE = -350V RG = 25Ω TJ = +150oC Fig. 17, Circuit 2 C1 = .022µF tFI EOFF IL VCE = VGE L = 100µH VGE = -15V RG = 25Ω TJ = +25oC VCE = -350V Fig. 17, Circuit 1 RθJC NOTE: 1. Turn-Off Energy Loss (EOFF) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the collector current equals zero (ICE = 0A). The HGTD8P50G1 and HGTD8P50G1S were tested per JEDEC standard No. 24-1 Method for Measurement of Power Device Turn-Off Switching Loss. This test method produces the true total Turn-Off Energy Loss. Turn-On losses include diode losses. 2 HGTD8P50G1, HGTD8P50G1S PULSE DURATION = 250µs, DUTY CYCLE < 0.5% PULSE DURATION = 250µs, DUTY CYCLE < 0.5%, VCE = -10V -20 ICE , COLLECTOR-EMITTER CURRENT (A) -16 TC = -40oC -12 TC = +150oC o TC = +25 C -8 -4 0 -4 -12 -8 -10 -6 VGE , GATE-TO-EMITTER VOLTAGE (V) -14 -20 VGE = -15V -9.0V -12 ICE , COLLECTOR-EMITTER CURRENT (A) ICE , DC COLLECTOR CURRENT (A) -12 -10 VGE = -15V -6 -4 -2 25 50 75 100 125 -8.0V -8 -4 -7.0V -6.5V 0 0 -4 -6 -8 -2 VCE , COLLECTOR-EMITTER VOLTAGE (V) 150 PULSE DURATION = 250µs, DUTY CYCLE < 0.5%, VGE = -15V -20 TC = +25oC -16 TC = -40oC -12 TC = +150oC -8 -4 0 0 TC , CASE TEMPERATURE (oC) FIGURE 3. MAXIMUM DC COLLECTOR CURRENT AS A FUNCTION OF CASE TEMPERATURE -1 -3 -4 -5 -6 -2 VCE , COLLECTOR-EMITTER VOLTAGE (V) TJ = +25oC, VGE = -15V, IG(REF) = -0.391mA VCE, COLLECTOR-EMITTER VOLTAGE (V) 700 600 CIES C, CAPACITANCE (pF) -15 -400 500 400 VCE = -400V VCE = -400V GATE-EMITTER VOLTAGE -200 300 200 COES 100 CRES 0 -7.5 VCE = -100V COLLECTOR-EMITTER VOLTAGE 0 -5 -10 -15 -20 -7 FIGURE 4. COLLECTOR-EMITTER SATURATION VOLTAGE FREQUENCY = 1MHz 0 -10 FIGURE 2. SATURATION CHARACTERISTICS -14 0 -10V -16 FIGURE 1. TRANSFER CHARACTERISTICS -8 -12V -25 20 VCE , COLLECTOR-EMITTER VOLTAGE (V) FIGURE 5. CAPACITANCE AS A FUNCTION OF COLLECTOREMITTER VOLTAGE IG(REF) IG(ACT) TIME (µs) 80 IG(REF) IG(ACT) FIGURE 6. NORMALIZED SWITCHING WAVEFORMS AT CONSTANT GATE CURRENT. (REFER TO APPLICATION NOTES AN7254 AND AN7260) 3 0 VGE , GATE-EMITTER VOLTAGE (V) ICE , COLLECTOR-EMITTER CURRENT (A) Typical Performance Curves HGTD8P50G1, HGTD8P50G1S Typical Performance Curves (Continued) TJ = +150oC, RG = 25Ω, L = 100µH WOFF , TURN-OFF SWITCHING LOSS (mJ) TJ = +150oC VCE(SAT) , SATURATION VOLTAGE (V) -10 -5 VGE = -10V VGE = -15V -1 0 -2 -4 -6 -8 -10 -12 ICE , COLLECTOR-EMITTER CURRENT (A) 10 FIG. 17, CIRCUIT 1 VCE = -350V, VGE = -15V 1.0 VCE = -200V, VGE = -15V 0.1 -1 -14 FIGURE 7. SATURATION VOLTAGE AS A FUNCTION OF COLLECTOR-EMITTER CURRENT -4 -5 TJ = +150oC, TC = +75oC, VGE = -15V, RGE = 25Ω, L = 100µH 100 fMAX , OPERATING FREQUENCY (kHz) 1.0 tD(OFF)I , TURN-OFF DELAY TIME (µs) -3 FIGURE 8. TURN-OFF SWITCHING LOSS AS A FUNCTION OF COLLECTOR-EMITTER CURRENT TJ = +150oC, VCE = -350V, VGE = -15V, L = 100µH RGE = 50Ω RGE = 25Ω 0.5 FIG. 17, CIRCUIT 1 0.1 -1 -2 -3 -4 ICE , PEAK COLLECTOR-EMITTER CURRENT (A) ICE , PEAK COLLECTOR-EMITTER CURRENT (A) FIG. 17, CIRCUIT 1 3 VCE = -200V 2 VCE = -350V 1 -4 fMAX1 = 0.05/tD(OFF)I fMAX2 = (PD - PC)/EOFF PD = ALLOWABLE DISSIPATION PC = CONDUCTION DISSIPATION (DUTY FACTOR = 50%) RθJC = 1.9oC/W 10 -5 -10 FIGURE 10. OPERATING FREQUENCY AS A FUNCTION OF COLLECTOR-EMITTER CURRENT AND VOLTAGE 4 -3 VCE = -350V ICE , PEAK COLLECTOR-EMITTER CURRENT (A) 5 -2 50 -1 TJ = +150oC, VGE = -15V, RG = 25Ω, L = 100µH -1 FIG. 17, CIRCUIT 1 -5 FIGURE 9. TURN-OFF DELAY AS A FUNCTION OF COLLECTOREMITTER CURRENT tFI , FALL TIME (µs) -2 ICE , PEAK COLLECTOR-EMITTER CURRENT (A) -5 ICE , COLLECTOR-EMITTER CURRENT (A) TJ = 25oC, VGE = -15V, RG = 25Ω, L = 100µH -25 FIG. 17, CIRCUIT 2 -20 -15 -10 VCE = -350V -5 0 10-5 10-4 10-3 10-2 10-1 C1, SNUBBER CAPACITANCE (µF) FIGURE 11. FALL TIME AS A FUNCTION OF COLLECTOREMITTER CURRENT FIGURE 12. LATCHING CURRENT AS A FUNCTION OF SNUBBER CAPACITANCE 4 100 HGTD8P50G1, HGTD8P50G1S Typical Performance Curves (Continued) VCE = VGE, ICE = 1.0mA VCE = -350V, VGE = -15V, RG = 25Ω, L = 100µH VTH , GATE THRESHOLD VOLTAGE (V) ICE , PEAK COLLECTOR-EMITTER CURRENT (A) -7 FIG. 17, CIRCUIT 1 -6 -5 -4 -3 -50 0 50 100 TC , CASE TEMPERATURE (oC) 6.5 6.0 5.5 5.0 4.5 -40 150 FIGURE 13. LATCHING CURRENT AS A FUNCTION OF JUNCTION TEMPERATURE 120 0 40 80 TC , CASE TEMPERATURE (oC) 160 FIGURE 14. GATE THRESHOLD VOLTAGE AS A FUNCTION OF JUNCTION TEMPERATURE TC = 25oC, VGE = -15V, RG = 25Ω, L = 100µH 15 t1 0.1 10-1 PDS 0.05 t2 0.02 10-2 ICE , PEAK COLLECTOR-EMITTER CURRENT (A) 0.5 0.2 RESPONSE (oC/W) ZθJC , NORMALIZED THERMAL 100 0.01 SINGLE PULSE NOTES: 1. DUTY FACTOR, D = t1/t2 2.PEAK TJ = (PDS x ZθJC x RθJC) + TA 10-3 10-5 10-4 10-3 10-2 10-1 100 12 9 FIG. 17, CIRCUIT 1 6 3 0 101 0 t1 , RECTANGULAR PULSE DURATION (s) 100 200 400 300 VCE , COLLECTOR-EMITTER (V) FIGURE 15. IGBT NORMALIZED TRANSIENT THERMAL IMPEDANCE, JUNCTION TO CASE FIGURE 16. LATCHING CURRENT AS A FUNCTION OF COLLECTOR-EMITTER VOLTAGE Test Circuits CIRCUIT 2 CIRCUIT 1 L = 100µH L = 100µH D1 = GSI TranZorb - VCC = 350V D1 + RG = 25Ω RG = 25Ω C1 FIGURE 17. INDUCTIVE SWITCHING TEST CIRCUITS 5 VCC = 350V + 500 HGTD8P50G1, HGTD8P50G1S Operating Frequency Information Handling Precautions for IGBTs Operating frequency information for a typical device (Figure 10) is presented as a guide for estimating device performance for a specific application. Other typical frequency vs collector current (ICE) plots are possible using the information shown for a typical unit in Figure 7, Figure 8 and Figure 9. The operating frequency plot (Figure 10) of a typical device shows fMAX1 or fMAX2 whichever is smaller at each point. The information is based on measurements of a typical device and is bounded by the maximum rated junction temperature. Insulated Gate Bipolar Transistors are susceptible to gateinsulation damage by the electrostatic discharge of energy through the devices. When handling these devices, care should be exercised to assure that the static charge built in the handler’s body capacitance is not discharged through the device. With proper handling and application procedures, however, IGBTs are currently being extensively used in production by numerous equipment manufacturers in military, industrial and consumer applications, with virtually no damage problems due to electrostatic discharge. IGBTs can be handled safely if the following basic precautions are taken: fMAX1 is defined by fMAX1 = 0.05/tD(OFF)I. tD(OFF)I deadtime (the denominator) has been arbitrarily held to 10% of the onstate time for a 50% duty factor. Other definitions are possible. tD(OFF)I is defined as the time between the 90% point of the trailing edge of the input pulse and the point where the collector current falls to 90% of its maximum value. Device Turn-Off delay can establish an additional frequency limiting condition for an application other than TJMAX. tD(OFF)I is important when controlling output ripple under a lightly loaded condition. fMAX2 is defined by fMAX2 = (PD PC)/EOFF . The allowable dissipation (PD) is defined by PD = (TJMAX - TC)/RθJC . The sum of device switching and conduction losses must not exceed Pd. A 50% duty factor was used (Figure 10) and the conduction losses (Pc) are approximated by Pc = (VCE • ICE)/2. EOFF is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the collector current equals zero (ICE = 0A). 1. Prior to assembly into a circuit, all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conductive material such as “†ECCOSORBD LD26” or equivalent. 2. When devices are removed by hand from their carriers, the hand being used should be grounded by any suitable means - for example, with a metallic wristband. 3. Tips of soldering irons should be grounded. 4. Devices should never be inserted into or removed from circuits with power on. 5. Gate Voltage Rating - Never exceed the gate-voltage rating of VGEM. Exceeding the rated VGE can result in permanent damage to the oxide layer in the gate region. 6. Gate Termination - The gates of these devices are essentially capacitors. Circuits that leave the gate opencircuited or floating should be avoided. These conditions can result in Turn-On of the device due to voltage buildup on the input capacitor due to leakage currents or pickup. The switching power loss (Figure 10) is defined as fMAX2 • EOFF . Turn-On switching losses are not included because they can be greatly influenced by external circuit conditions and components. 7. Gate Protection - These devices do not have an internal monolithic zener diode from gate to emitter. If gate protection is required an external zener is recommended. † Trademark Emerson and Cumming, Inc. INTERSILT CORPORATION PRODUCT IS COVERED BY ONE OR MORE OF THE FOLLOWING U.S. PATENTS: 4,364,073 4,417,385 4,430,792 4,443,931 4,466,176 4,516,143 4,532,534 4,567,641 4,587,713 4,598,461 4,605,948 4,618,872 4,620,211 4,631,564 4,639,754 4,639,762 4,641,162 4,644,637 4,682,195 4,684,413 4,694,313 4,717,679 4,743,952 4,783,690 4,794,432 4,801,986 4,803,533 4,809,045 4,809,047 4,810,665 4,823,176 4,837,606 4,860,080 4,883,767 4,888,627 4,890,143 4,901,127 4,904,609 4,933,740 4,963,951 4,969,027 6 HGTD8P50G1, HGTD8P50G1S TO-251AA 3 LEAD JEDEC TO-251AA PLASTIC PACKAGE E b2 H1 INCHES A SYMBOL A1 D MAX NOTES A 0.086 0.094 2.19 2.38 - SEATING PLANE 0.018 0.022 0.46 0.55 3, 4 L1 c 2 MILLIMETERS MIN A1 L 1 MAX TERM. 4 b1 b MIN 3 b 0.028 0.032 0.72 0.81 3, 4 b1 0.033 0.040 0.84 1.01 3 b2 0.205 0.215 5.21 5.46 3, 4 c 0.018 0.022 0.46 0.55 3, 4 D 0.270 0.290 6.86 7.36 - E 0.250 0.265 6.35 6.73 - e 0.090 TYP 2.28 TYP 5 e1 0.180 BSC 4.57 BSC 5 H1 0.035 0.045 0.89 1.14 - e1 J1 0.040 0.045 1.02 1.14 6 L 0.355 0.375 9.02 9.52 - Lead 1 Gate L1 0.075 0.090 1.91 2.28 2 Lead 2 Collector Lead 3 Emitter Term. 4 Collector J1 e NOTES: 1. These dimensions are within allowable dimensions of Rev. C of JEDEC TO-251AA outline dated 9-88. 2. Solder finish uncontrolled in this area. 3. Dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder plating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimension: Inch. 8. Revision 2 dated 10-95. 7 HGTD8P50G1, HGTD8P50G1S TO-252AA SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE INCHES A E SYMBOL A1 b2 H1 SEATING PLANE D L2 1 L 3 b1 b e e1 L3 A 0.086 0.094 2.19 2.38 - 0.018 0.022 0.46 0.55 4, 5 b 0.028 0.032 0.72 0.81 4, 5 b1 0.033 0.040 0.84 1.01 4 b2 0.205 0.215 5.21 5.46 4, 5 b3 0.190 - 4.83 - 2 0.018 0.022 0.46 0.55 4, 5 0.270 0.290 6.86 7.36 - c E 0.250 0.265 6.35 6.73 J1 e e1 0.118 (3.0) 0.063 (1.6) 0.090 (2.3) 0.090 (2.3) MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS Lead 3 Source Term. 4 Collector 0.090 TYP 0.180 BSC 0.035 0.045 - 2.28 TYP 7 4.57 BSC 7 0.89 1.14 - J1 0.040 0.045 1.02 1.14 - L 0.100 0.115 2.54 2.92 - L1 0.020 - 0.51 - 4, 6 L2 0.025 0.040 0.64 1.01 3 L3 0.170 - 4.32 - 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. B of JEDEC TO-252AA outline dated 9-88. 2. L3 and b3 dimensions establish a minimum mounting surface for terminal 4. 3. Solder finish uncontrolled in this area. 4. Dimension (without solder). 5. Add typically 0.002 inches (0.05mm) for solder plating. 6. L1 is the terminal length for soldering. 7. Position of lead to be measured 0.090 inches (2.28mm) from bottom of dimension D. 8. Controlling dimension: Inch. 9. Revision 5 dated 10-95. BACK VIEW Gate NOTES c 0.070 (1.8) Lead 1 MAX D 0.265 (6.7) 0.063 (1.6) MIN A1 H1 b3 MILLIMETERS MAX L1 0.265 (6.7) TERM. 4 MIN 8 HGTD8P50G1, HGTD8P50G1S TO-252AA 16mm TAPE AND REEL 22.4mm 1.5mm DIA. HOLE 4.0mm 2.0mm 13mm 1.75mm C L 16mm 330mm 50mm 8.0mm 16.4mm USER DIRECTION OF FEED COVER TAPE GENERAL INFORMATION 1. USE "9A" SUFFIX ON PART NUMBER. 2. 2500 PIECES PER REEL. 3. ORDER IN MULTIPLES OF FULL REELS ONLY. 4. MEETS EIA-481 REVISION "A" SPECIFICATIONS. Revision 5 dated 10-95 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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