74LVC245A-Q100; 74LVCH245A-Q100 Octal bus transceiver; 3-state Rev. 2 — 10 February 2014 Product data sheet 1. General description The 74LVC245A-Q100; 74LVCH245A-Q100 are 8-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The 74LVCH245A-Q100 bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Inputs accept voltages up to 5.5 V High-impedance when VCC = 0 V Bus hold on all data inputs (74LVCH245A-Q100 only) Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) NXP Semiconductors 74LVC245A-Q100; 74LVCH245A-Q100 Octal bus transceiver; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74LVC245AD-Q100 Temperature range Name Description Version 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm 74LVCH245AD-Q100 74LVC245APW-Q100 74LVCH245APW-Q100 74LVC245ABQ-Q100 74LVCH245ABQ-Q100 SOT764-1 4. Functional diagram 1 DIR OE 2 B0 3 19 3EN1 3EN2 1 14 18 3 17 13 4 16 5 15 6 14 7 13 8 12 A6 12 A7 B7 11 9 mna174 Fig 1. 2 A5 B6 9 G3 2 B5 8 15 A4 B4 7 1 16 A3 B3 6 17 A2 B2 5 18 A1 B1 4 19 A0 Logic diagram 74LVC_LVCH245A_Q100 Product data sheet 11 mna175 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 2 of 16 74LVC245A-Q100; 74LVCH245A-Q100 NXP Semiconductors Octal bus transceiver; 3-state 5. Pinning information 5.1 Pinning 1 terminal 1 index area 74LVC245A-Q100 74LVCH245A-Q100 20 VCC DIR 74LVC245A-Q100 74LVCH245A-Q100 A0 2 19 OE A1 3 18 B0 A2 4 17 B1 DIR 1 20 VCC A0 2 19 OE A1 3 18 B0 A3 5 16 B2 6 15 B3 17 B1 A3 5 16 B2 A5 7 A4 6 15 B3 A6 8 A5 7 14 B4 A6 8 13 B5 A7 9 A7 9 12 B6 GND 10 11 B7 14 B4 GND(1) 13 B5 12 B6 B7 11 4 GND 10 A2 A4 aaa-003143 Transparent top view aaa-003142 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 3. Pin configuration for SO20 and TSSOP20 Fig 4. Pin configuration for DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description DIR 1 direction control A0 to A7 2, 3, 4, 5, 6, 7, 8, 9 data input/output GND 10 ground (0 V) B0 to B7 18, 17, 16, 15, 14, 13, 12, 11 data input/output OE 19 output enable input (active LOW) VCC 20 supply voltage 74LVC_LVCH245A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 3 of 16 74LVC245A-Q100; 74LVCH245A-Q100 NXP Semiconductors Octal bus transceiver; 3-state 6. Functional description Table 3. Function selection[1] Inputs Inputs/outputs OE DIR An Bn L L An = Bn inputs L H inputs Bn = An H X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA output HIGH or LOW [2] 0.5 VCC + 0.5 V output 3-state [2] 0.5 +6.5 V - 50 mA VO > VCC or VO < 0 V IO output current VO = 0 V to VCC ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature Ptot total power dissipation Tamb = 40 C to +125 C [3] 65 +150 C - 500 mW [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO20 package: above 70 C derate linearly with 8 mW/K. For TSSOP20 package: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 package: above 60 C derate linearly with 4.5 mW/K. 74LVC_LVCH245A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 4 of 16 NXP Semiconductors 74LVC245A-Q100; 74LVCH245A-Q100 Octal bus transceiver; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Min Typ Max Unit 1.65 - 3.6 V functional 1.2 - 3.6 V 0 - 5.5 V output HIGH or LOW 0 - VCC V output 3-state 0 - 5.5 V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VCC = 1.2 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Product data sheet Max Min Unit Max VCC = 1.2 V 1.08 - - 1.08 - V 0.65 VCC - - 0.65 VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V - 0.12 V VCC = 1.2 V - - 0.12 VCC = 1.65 V to 1.95 V - - 0.35 VCC - 0.35 VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V IO = 100 A; VCC = 1.65 V to 3.6 V VCC 0.2 - - VCC 0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V - - 0.55 - 0.8 V VI = VIH or VIL VI = VIH or VIL input leakage VI = 5.5 V or GND; current VCC = 3.6 V 74LVC_LVCH245A_Q100 40 C to +125 C VCC = 1.65 V to 1.95 V IO = 24 mA; VCC = 3.0 V II Typ[1] [2] - 0.1 All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 5 - 20 A © NXP B.V. 2014. All rights reserved. 5 of 16 NXP Semiconductors 74LVC245A-Q100; 74LVCH245A-Q100 Octal bus transceiver; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions [3] 40 C to +125 C Unit Min Typ[1] Max Min Max - 0.1 5 - 20 A IOZ OFF-state VI = VIH or VIL; output current VO = 5.5 V or GND; VCC = 3.6 V IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0.0 V - 0.1 10 - 20 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V - 0.1 10 - 40 A ICC additional supply current per input pin; VI = VCC 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 4.0 - - - pF CI/O input/output capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 10 - - - pF IBHL bus hold LOW current VCC = 1.65; VI = 0.58 V 10 - - 10 - A 30 - - 25 - A [4][5] VCC = 2.3; VI = 0.7 V 75 - - 60 - A 10 - - 10 - A 30 - - 25 - A VCC = 3.0; VI = 2.0 V 75 - - 60 - A bus hold LOW overdrive current VCC = 1.95 V 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A 500 - - 500 - A bus hold HIGH overdrive current VCC = 1.95 V 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A 500 - - 500 - A VCC = 3.0; VI = 0.8 V IBHH IBHLO IBHHO bus hold VCC = 1.65; VI = 1.07 V HIGH current V = 2.3; V = 1.7 V CC I VCC = 3.6 V VCC = 3.6 V [4][5] [4][6] [4][6] [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. [2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. [3] For I/O ports, the parameter IOZ includes the input leakage current. [4] Valid for data inputs of bus hold parts only (74LVCH245A-Q100). Note that control inputs do not have a bus hold circuit. [5] The specified sustaining current at the data input holds the input below the specified VI level. [6] The specified overdrive current at the data input forces the data input to the opposite input state. 74LVC_LVCH245A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 6 of 16 NXP Semiconductors 74LVC245A-Q100; 74LVCH245A-Q100 Octal bus transceiver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter propagation delay tpd enable time ten 40 C to +85 C Conditions Min Max Min Max - 17.0 - - - ns VCC = 1.65 V to 1.95 V 1.5 6.5 14.6 1.5 16.9 ns VCC = 2.3 V to 2.7 V 1.0 3.4 7.6 1.0 8.7 ns VCC = 2.7 V 1.5 3.4 7.3 1.5 9.5 ns VCC = 3.0 V to 3.6 V 1.5 2.9 6.3 1.5 8.0 ns - 22.0 - - - ns VCC = 1.65 V to 1.95 V 1.9 8.3 19.5 1.9 22.5 ns VCC = 2.3 V to 2.7 V 1.5 4.6 10.7 1.5 12.4 ns VCC = 2.7 V 1.5 4.8 9.5 1.5 12.0 ns 1.5 3.7 8.5 1.5 11.0 ns - 12.0 - - - ns VCC = 1.65 V to 1.95 V 2.9 5.5 12.3 2.9 14.2 ns VCC = 2.3 V to 2.7 V 1.0 3.1 7.1 1.0 8.2 ns VCC = 2.7 V 1.5 3.9 8.0 1.5 10.0 ns VCC = 3.0 V to 3.6 V 1.7 3.6 7.0 1.7 9.0 ns - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 7.7 - - - pF VCC = 2.3 V to 2.7 V - 11.3 - - - pF VCC = 3.0 V to 3.6 V - 14.4 - - - pF nAn to nBn; nBn to nAn; see Figure 5 [1] VCC = 1.2 V nOE to nAn, nBn; see Figure 6 [1] VCC = 1.2 V VCC = 3.0 V to 3.6 V disable time tdis nOE to nAn, nBn; see Figure 6 [1] VCC = 1.2 V tsk(o) output skew time CPD power dissipation capacitance [1] 40 C to +125 C Unit Typ[2] [3] per input; VI = GND to VCC [4] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [2] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL VCC2 fo) = sum of the outputs. 74LVC_LVCH245A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 7 of 16 74LVC245A-Q100; 74LVCH245A-Q100 NXP Semiconductors Octal bus transceiver; 3-state 11. AC waveforms VI An, Bn input VM VM GND tPLH tPHL VOH VM Bn, An output VM VOL mna176 See Table 8 for measurement points VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Input (An, Bn) to output (Bn, An) propagation delays and output transition times VI OE input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PHZ VOH t PZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled mna367 See Table 8 for measurement points VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Table 8. Enable and disable times Measurement points Supply voltage VM VCC Input VI tr = tf VX VY 1.2 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V 1.65 V to 1.95 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V 2.3 V to 2.7 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V 2.7 V 1.5 V 2.7 V 2.5 ns VOL + 0.3 V VOH 0.3 V 3.0 V to 3.6 V 1.5 V 2.7 V 2.5 ns VOL + 0.3 V VOH 0.3 V 74LVC_LVCH245A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 8 of 16 74LVC245A-Q100; 74LVCH245A-Q100 NXP Semiconductors Octal bus transceiver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Table 9. Test circuit for measuring switching times Test data Supply voltage Input VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC 2 ns 30 pF 1 k open 2 VCC GND 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k open 2 VCC GND 2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 74LVC_LVCH245A_Q100 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 9 of 16 74LVC245A-Q100; 74LVCH245A-Q100 NXP Semiconductors Octal bus transceiver; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT163-1 (SO20) 74LVC_LVCH245A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 10 of 16 74LVC245A-Q100; 74LVCH245A-Q100 NXP Semiconductors Octal bus transceiver; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 Fig 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Package outline SOT360-1 (TSSOP20) 74LVC_LVCH245A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 11 of 16 74LVC245A-Q100; 74LVCH245A-Q100 NXP Semiconductors Octal bus transceiver; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT764-1 (DHVQFN20) 74LVC_LVCH245A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 12 of 16 74LVC245A-Q100; 74LVCH245A-Q100 NXP Semiconductors Octal bus transceiver; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic MIL Military 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC_LVCH245A_Q100 v.2 20140210 - 74LVC_LVCH245A_Q100 v.1 Modifications: 74LVC_LVCH245A_Q100 v.1 74LVC_LVCH245A_Q100 Product data sheet • Product data sheet Alternative descriptive title corrected (errata). 20120903 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 - © NXP B.V. 2014. All rights reserved. 13 of 16 NXP Semiconductors 74LVC245A-Q100; 74LVCH245A-Q100 Octal bus transceiver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC_LVCH245A_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 14 of 16 NXP Semiconductors 74LVC245A-Q100; 74LVCH245A-Q100 Octal bus transceiver; 3-state No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC_LVCH245A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 February 2014 © NXP B.V. 2014. All rights reserved. 15 of 16 NXP Semiconductors 74LVC245A-Q100; 74LVCH245A-Q100 Octal bus transceiver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 February 2014 Document identifier: 74LVC_LVCH245A_Q100