SiI9573 and SiI9575 Port Processor

SiI9573 and SiI9575 Port Processor
Data Sheet
SiI-DS-1089-F
March 2016
SiI9573 and SiI9575 Port Processor
Data Sheet
Contents
1.
General Description ...................................................................................................................................................... 7
1.1. HDMI Inputs and Outputs ..................................................................................................................................... 7
1.2. Performance Improvement Features .................................................................................................................... 8
1.3. Audio Inputs and Outputs ..................................................................................................................................... 8
1.4. Control Capability ................................................................................................................................................. 8
1.5. Packaging .............................................................................................................................................................. 8
2. Functional Description .................................................................................................................................................. 9
2.1. Always-on Section ................................................................................................................................................. 9
2.1.1.
Serial Ports Block ......................................................................................................................................... 10
2.1.2.
Static RAM Block ......................................................................................................................................... 10
2.1.3.
NVRAM Block .............................................................................................................................................. 10
2.1.4.
HDCP Registers Block .................................................................................................................................. 10
2.1.5.
OTP ROM Block ........................................................................................................................................... 10
2.1.6.
Booting Sequencer ...................................................................................................................................... 10
2.1.7.
Configuration, Status, and Interrupt Control Block ..................................................................................... 11
2.1.8.
Mobile HD Control Block ............................................................................................................................. 11
2.1.9.
CEC Interface Controller .............................................................................................................................. 11
2.1.10. Power Block................................................................................................................................................. 11
2.2. Power-down Section ........................................................................................................................................... 11
2.2.1.
TMDS Receiver Blocks ................................................................................................................................. 11
2.2.2.
6:1 Input Multiplexer Blocks A and B and 4:1 Input Multiplexer Blocks C and D ........................................ 11
2.2.3.
HDMI, MHL, and InstaPort Receiver Blocks ................................................................................................ 12
2.2.4.
Video/Audio Splitter Block .......................................................................................................................... 12
2.2.5.
InstaPrevue Block ........................................................................................................................................ 12
2.2.6.
Stream Mixer Block ..................................................................................................................................... 12
2.2.7.
2:1 Input Multiplexer Blocks E and F and Main and Subaudio Formatting Blocks ...................................... 12
2.2.8.
Parallel Video Input Block ........................................................................................................................... 12
2.2.9.
Video Pattern Generator Block ................................................................................................................... 13
2.2.10. Audio Sampling Rate Converter Block ......................................................................................................... 13
2.2.11. On-screen Display Controller ...................................................................................................................... 14
2.2.12. Audio Input Block ........................................................................................................................................ 14
2.2.13. Audio Output Block ..................................................................................................................................... 15
2.2.14. Audio Return Channel (ARC) Input and Output .......................................................................................... 15
2.2.15. TMDS Transmitter Block .............................................................................................................................. 16
3. Electrical Specifications............................................................................................................................................... 17
3.1. Absolute Maximum Conditions ........................................................................................................................... 17
3.2. Normal Operating Conditions ............................................................................................................................. 18
3.3. DC Specifications ................................................................................................................................................. 19
3.4. AC Specifications ................................................................................................................................................. 21
3.4.1.
Control Signal Timing Specifications ........................................................................................................... 23
3.4.2.
Audio Input Timing ..................................................................................................................................... 24
3.4.3.
Audio Output Timing .................................................................................................................................. 24
3.5. Serial Flash SPI Interface AC Specifications ......................................................................................................... 25
4. Timing Diagrams ......................................................................................................................................................... 26
4.1. Video Input Timing Diagrams ............................................................................................................................. 26
4.2. Reset Timing Diagrams ....................................................................................................................................... 27
2
4.3. I C Timing Diagrams ............................................................................................................................................ 28
4.4. Digital Audio Input Timing .................................................................................................................................. 28
4.5. Digital Audio Output Timing ............................................................................................................................... 29
5. Pin Diagram and Pin Descriptions ............................................................................................................................... 31
5.1. Pin Diagram ......................................................................................................................................................... 31
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
5.2. Pin Descriptions .................................................................................................................................................. 32
5.2.1.
HDMI Receiver and MHL Port Pins .............................................................................................................. 32
5.2.2.
HDMI Receiver and MHL Port Pins (continued) .......................................................................................... 33
5.2.3.
HDMI Transmitter Port Pins ........................................................................................................................ 33
5.2.4.
Audio Return Channel Pins ......................................................................................................................... 33
5.2.5.
Audio Pins ................................................................................................................................................... 34
5.2.6.
Crystal Pins .................................................................................................................................................. 34
5.2.7.
SPI Interface Pins ........................................................................................................................................ 35
5.2.8.
Parallel Video Bus ....................................................................................................................................... 35
2
5.2.9.
DDC I C Pins ................................................................................................................................................ 36
5.2.10. Control Pins ................................................................................................................................................. 37
5.2.11. System Switching Pins ................................................................................................................................. 37
5.2.12. Configuration Pins ....................................................................................................................................... 38
5.2.13. CEC Pins....................................................................................................................................................... 38
5.2.14. Power and Ground Pins .............................................................................................................................. 39
5.2.15. Reserved Pin ............................................................................................................................................... 39
6. Feature Information .................................................................................................................................................... 40
6.1. Standby and HDMI Port Power Supplies ............................................................................................................. 40
6.2. InstaPort.............................................................................................................................................................. 41
6.3. InstaPrevue ......................................................................................................................................................... 41
6.4. Support for UltraHD resolution at 50P/60P frames per second .......................................................................... 42
6.5. ViaPort Matrix Switch ......................................................................................................................................... 42
6.6. MHL Receiver ...................................................................................................................................................... 42
6.7. 3D Video Formats on Main Display .................................................................................................................... 43
6.8. VS Insertion ......................................................................................................................................................... 43
6.9. 3D L/R and Active Space Indicators Output on GPIO Pins................................................................................... 44
6.10.
Parallel Video Input Data Bus Mapping .......................................................................................................... 45
6.10.1. Common Video Input Formats ................................................................................................................... 45
6.10.2. RGB and YCbCr 4:4:4 Formats Dual Clock Edge .......................................................................................... 46
6.10.3. YC 4:2:2 Separate Sync Formats .................................................................................................................. 48
6.10.4. YC 4:2:2 Embedded Syncs Formats ............................................................................................................. 49
6.10.5. YC Mux 4:2:2 Separate Sync Formats Single Clock Edge ............................................................................. 52
6.10.6. YC Mux 4:2:2 Embedded Sync Formats Single Clock Edge .......................................................................... 56
6.10.7. YC Mux 4:2:2 Separate Sync Formats Dual Clock Edge ............................................................................... 59
6.10.8. YC Mux 4:2:2 Embedded Sync Formats Dual Clock Edge ............................................................................ 64
7. Design Recommendations .......................................................................................................................................... 69
7.1. Power Supply Decoupling ................................................................................................................................... 69
7.2. Power Supply Control Timing and Sequencing ................................................................................................... 69
8. Package Information ................................................................................................................................................... 70
8.1. ePad Requirements ............................................................................................................................................. 70
8.2. Package Dimensions ........................................................................................................................................... 71
8.3. Marking Specification ......................................................................................................................................... 72
8.4. Ordering Information .......................................................................................................................................... 72
References .......................................................................................................................................................................... 73
Standards Documents ..................................................................................................................................................... 73
Standards Groups ........................................................................................................................................................... 73
Lattice Semiconductor Documents ................................................................................................................................. 73
Technical Support ........................................................................................................................................................... 73
Revision History .................................................................................................................................................................. 74
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
3
SiI9573 and SiI9575 Port Processor
Data Sheet
Figures
Figure 1.1. Port Processor Application ............................................................................................................................ 7
Figure 2.1. Functional Block Diagram ............................................................................................................................. 9
2
Figure 2.2. I C Control Configuration ............................................................................................................................ 10
Figure 3.1. Test Point SBVCC5TP for SBVCC5 Measurement ......................................................................................... 18
Figure 3.2. Audio Crystal Schematic ............................................................................................................................. 23
Figure 4.1. IDCK Clock Duty Cycle ................................................................................................................................. 26
Figure 4.2. Control and Data Single-Edge Setup and Hold Times—EDGE = 1 ............................................................... 26
Figure 4.3. Control and Data Single-Edge Setup and Hold Times—EDGE = 0 ............................................................... 26
Figure 4.4. Control and Data Dual-Edge Setup and Hold Times ....................................................................................27
Figure 4.5. Conditions for Use of RESET# .......................................................................................................................27
Figure 4.6. RESET# Minimum Timing .............................................................................................................................27
2
Figure 4.7. I C Data Valid Delay (Driving Read Cycle Data) ........................................................................................... 28
2
Figure 4.8. I C Data Setup Time .................................................................................................................................... 28
2
Figure 4.9. I S Input Timing .......................................................................................................................................... 28
Figure 4.10. S/PDIF Input Timing .................................................................................................................................. 28
2
Figure 4.11. I S Output Timing ...................................................................................................................................... 29
Figure 4.12. S/PDIF Output Timing ............................................................................................................................... 29
Figure 4.13. MCLK Timing ............................................................................................................................................. 29
Figure 4.14. SPI Flash Memory Timing ......................................................................................................................... 30
Figure 5.1. Pin Diagram (Top View)............................................................................................................................... 31
Figure 6.1. Standby Power Supply Diagram .................................................................................................................. 40
Figure 6.2. VS Insertion in Active Space ........................................................................................................................ 44
Figure 6.3. L/R and Active Space Indicators Output on GPIO Pins ................................................................................ 45
Figure 6.4. 8-bit Color Depth RGB/YCbCr 4:4:4 Dual Edge Timing (DRA = 0) .................................................................47
Figure 6.5. 8-bit Color Depth RGB/YCbCr 4:4:4 Dual Edge Timing (DRA = 1) .................................................................47
Figure 6.6. 8-bit Color Depth YC 4:2:2 Timing (YCSWAP = 0) ........................................................................................ 48
Figure 6.7. 8-bit Color Depth YC 4:2:2 Timing (YCSWAP = 1) ........................................................................................ 49
Figure 6.8. 10-bit Color Depth YC 4:2:2 Timing (YCSWAP = 0) ...................................................................................... 49
Figure 6.9. 10-bit Color Depth YC 4:2:2 Timing (YCSWAP = 1) ...................................................................................... 49
Figure 6.10. 8-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 0) ........................................................... 50
Figure 6.11. 8-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 1) ........................................................... 51
Figure 6.12. 10-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 0) ......................................................... 51
Figure 6.13. 10-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 1) ......................................................... 51
Figure 6.14. 8-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0) .................................................................................... 52
Figure 6.15. 8-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1) .................................................................................... 53
Figure 6.16. 10-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0) .................................................................................. 54
Figure 6.17. 10-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1) .................................................................................. 54
Figure 6.18. 12-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0) .................................................................................. 55
Figure 6.19. 12-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1) .................................................................................. 56
Figure 6.20. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0) ...........................................................57
Figure 6.21. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1) ...........................................................57
Figure 6.22. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0) ........................................................ 58
Figure 6.23. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1) ........................................................ 58
Figure 6.24. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0) ........................................................ 59
Figure 6.25. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1) ........................................................ 59
Figure 6.26. 8-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0) .............................................. 60
Figure 6.27. 8-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 1) .............................................. 61
Figure 6.28. 10-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0) ............................................ 62
Figure 6.29. 10-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 0) ............................................ 62
Figure 6.30. 12-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0) ............................................ 63
Figure 6.31. 12-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 0) ............................................ 64
Figure 6.32. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0) .................... 65
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
Figure 6.33. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 1) .....................65
Figure 6.34. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0) ...................66
Figure 6.35. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 0) ...................67
Figure 6.36. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0) ...................68
Figure 6.37. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 0) ...................68
Figure 7.1. Decoupling and Bypass Schematic ...............................................................................................................69
Figure 7.2. Decoupling and Bypass Capacitor Placement ..............................................................................................69
Figure 8.1. Package Diagram..........................................................................................................................................71
Figure 8.2. Marking Diagram ......................................................................................................................................... 72
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
5
SiI9573 and SiI9575 Port Processor
Data Sheet
Tables
Table 2.1. Pixel Clock Source and Frequency ................................................................................................................ 13
Table 3.1. Absolute Maximum Conditions .................................................................................................................... 17
Table 3.2. Normal Operating Conditions ....................................................................................................................... 18
Table 3.3. Digital I/O DC Specifications ......................................................................................................................... 19
Table 3.4. TMDS Input DC Specifications – HDMI Mode ............................................................................................... 19
Table 3.5. TMDS Input DC Specifications – MHL Mode................................................................................................. 19
Table 3.6. TMDS Output DC Specifications ................................................................................................................... 20
Table 3.7. Single Mode Audio Return Channel DC Specifications ................................................................................. 20
Table 3.8. S/PDIF Input Port DC Specifications.............................................................................................................. 20
Table 3.9. CEC DC Specifications ................................................................................................................................... 20
Table 3.10. CBUS DC Specifications ............................................................................................................................... 20
Table 3.11. Power.......................................................................................................................................................... 21
Table 3.12. TMDS Input Timing AC Specifications – HDMI Mode ................................................................................. 21
Table 3.13. TMDS Input Timing AC Specifications – MHL Mode ................................................................................... 21
Table 3.14. TMDS Output Timing AC Specifications...................................................................................................... 21
Table 3.15. Single Mode Audio Return Channel AC Specifications ............................................................................... 22
Table 3.16. CEC AC Specifications ................................................................................................................................. 22
Table 3.17. CBUS AC Specifications ............................................................................................................................... 22
Table 3.18. Video Input Timing AC Specifications ........................................................................................................ 22
Table 3.19. Control Signal Timing Specifications .......................................................................................................... 23
Table 3.20. Audio Crystal Frequency ............................................................................................................................. 23
Table 3.21. S/PDIF Input Port AC Specifications ............................................................................................................ 24
2
Table 3.22. I S Input Port AC Specifications .................................................................................................................. 24
2
Table 3.23. I S Output Port AC Specifications ............................................................................................................... 24
Table 3.24. S/PDIF Output Port AC Specifications ......................................................................................................... 24
Table 3.25. Serial Flash AC Specifications ..................................................................................................................... 25
Table 6.1. Description of Power Modes ........................................................................................................................ 40
Table 6.2. Supported InstaPrevue Window Formats .................................................................................................... 42
Table 6.3. Supported 3D Video Formats ....................................................................................................................... 43
Table 6.4. L/R and Active Space Indicator Mapping to GPIO Pins ................................................................................. 44
Table 6.5. Video Input Formats ..................................................................................................................................... 45
Table 6.6. RGB/YCbCr 4:4:4 Separate Sync Dual Clock Edge Data Mapping .................................................................. 46
Table 6.7. YC 4:2:2 Separate Sync Data Mapping .......................................................................................................... 48
Table 6.8. YC 4:2:2 Embedded Sync Data Mapping ....................................................................................................... 50
Table 6.9. YC Mux 4:2:2 8-bit Color Depth Separate Sync Data Mapping ..................................................................... 52
Table 6.10. YC Mux 4:2:2 10-bit Color Depth Separate Sync Data Mapping ................................................................. 53
Table 6.11. YC Mux 4:2:2 12-bit Color Depth Separate Sync Data Mapping ................................................................. 55
Table 6.12. YC Mux 4:2:2 8-bit Color Depth Embedded Sync Data Mapping ................................................................ 56
Table 6.13. YC Mux 4:2:2 10-bit Color Depth Embedded Sync Data Mapping ...............................................................57
Table 6.14. YC Mux 4:2:2 12-bit Color Depth Embedded Sync Data Mapping .............................................................. 58
Table 6.15. YC Mux 4:2:2 8-bit Color Depth Separate Sync Dual Clock Edge Data Mapping ......................................... 60
Table 6.16. YC Mux 4:2:2 10-bit Color Depth Separate Sync Dual Clock Edge Data Mapping ....................................... 61
Table 6.17. YC Mux 4:2:2 12-bit Color Depth Separate Sync Dual Clock Edge Data Mapping ....................................... 63
Table 6.18. YC Mux 4:2:2 8-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping...................................... 64
Table 6.19. YC Mux 4:2:2 10-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping.................................... 66
Table 6.20. YC Mux 4:2:2 12-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping.................................... 67
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
1. General Description
The Lattice Semiconductor SiI9573 and SiI9575 Port
Processor is the latest generation HDMI® port
processor targeted at audio video receivers (AVR),
Home Theater in a Box (HTiB), and Digital TVs (DTVs).
The port processor has many innovative features such
as InstaPort®, InstaPrevue, Mobile High-Definition Link
(MHL®), ViaPort Matrix Switch (the SiI9575 device only),
and Audio Return Channel (ARC) technology.
The two devices are the same except where noted.
SiI957n is used throughout this document to refer to
both devices.
The SiI957n port processor offers an extensive set of
audio features including audio extraction and insertion.
Audio from the active HDMI input is sent to the main
or subaudio output port. High-Bitrate (HBR) audio is
supported on the main audio output port. Additionally,
2
a 2-channel I S or an S/PDIF input receives PCM or bit
stream audio from an audio DSP or a DTV SoC, and
output to either the main or sub-HDMI output, or
both.
The SiI957n port processor supports two independent
ARC transceivers. Each ARC transceiver is configurable
as an ARC receiver or transmitter. As an ARC receiver in
an AVR or HTiB design, either the Tx0 or Tx1 HDMI
output can receive an ARC signal from a DTV. As an ARC
transmitter in a DTV design, the ARC signal can be
transmitted out of the two of the six Rx HDMI inputs,
which are designated as ARC-capable, to an AVR or
soundbar.
The MHL to HDMI bridge function is available on two
input ports; this allows consumers to attach their
mobile devices to the AVR or DTV and view high
definition content while the AVR or DTV charges the
mobile device battery.
The SiI9575 device supports ViaPort Matrix Switch.
While the main HDMI output selects one of the HDMI
inputs, the second HDMI output can select another
HDMI input or parallel video input. This is ideal for AVR
Zone 2 support or PIP/POP function in DTV.
1.1. HDMI Inputs and Outputs

Six HDMI input ports support 300 MHz
simultaneously

Two HDMI output ports that support 300 MHz
simultaneously

TMDS™ cores run up to 3.0 Gb/s

HDMI, MHL, HDCP, and DVI compatible

Supports video resolutions up to 4K × 2K @ 30 Hz,
8-bit, 1080p @ 60 Hz, 12-bit or 720p/1080i @ 120
Hz, 12-bit

Supports 4K × 2K 50P/60P FPS when pixel format is
YCb Cr 4:2:0.

Supports all the mandatory and some optional 3D
formats up to 300 MHz

MHL support up to1080p @ 24 Hz on two input
ports

Pre-programmed with HDCP keys

Repeater function supports up to 127 devices
Figure 1.1. Port Processor Application
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
7
SiI9573 and SiI9575 Port Processor
Data Sheet
1.2. Performance Improvement
Features

InstaPort™ viewing technology reduces port
switching time to less than one second

InstaPrevue technology provides a picture-inpicture preview of connected source devices

AVI, Audio InfoFrame, and video input resolution
detection for all input ports, accessible port-byport

Hardware-based HDCP error detection and
recovery minimizes firmware intervention

Automatic output mute and unmute based on link
stability, such as cable connect/detach
1.3. Audio Inputs and Outputs

Two S/PDIF inputs and two S/PDIF outputs
supporting PCM and compressed audio formats up
to 192 kHz such as Dolby Digital, DTS, and AC-3

DSD output supports Super Audio CD applications,
up to 6 channels

I S outputs support PCM, DVD-Audio output, up to
8-channel 192 kHz

I S inputs support PCM, DVD-Audio input, up to 2channel 192 kHz
2

High-Bitrate audio output support such as
DTS-HD MA and Dolby® TrueHD

Sample Rate Converter (SRC) supports down
sampling 2:1 and 4:1

Two HDMI ARC inputs or outputs support
1.4. Control Capability

Two independent Consumer Electronics Control
(CEC) interfaces with HDMI-compliant CEC I/O to
support two sink devices

Integrated EDID in non-volatile memory and DDC
support for the HDMI ports using separate
256-byte SRAM for the HDMI ports and 128-byte
SRAM for VGA EDID

Individual control of Hot Plug Detect (HPD) for
each of the input ports

Controllable by the local I C bus
2
1.5. Packaging
176-pin, 20 mm × 20 mm, 0.4 mm pitch TQFP package
with an exposed pad (ePad)
2
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
2. Functional Description
Figure 2.1 shows the block diagram of the SiI957n port processor.
Always-On
Section
CEC A0
CBUS/
HPD
CBUS0
CBUS1
Serial Ports
DDC0
DDC1
DDC2
DDC3
DDC4
DDC5
DDC6
DDC
I2C
Booting
Sequencer
NVRAM
EDID SRAM
HDCP
Registers
Local
I 2C
Configuration, Status,
and Interrupt-Control
Registers
OTP
DDC TX
E
Power-Down
Section
TMDS Rx
(Port 0)
R1X
TMDS Rx
(Port 1)
R2X
TMDS Rx
(Port 2)
R3X
TMDS Rx
(Port 3)
R4X
TMDS Rx
(Port 4)
HDMI/
MHL
Receiver
InstaPort
M
U
X
HDCP
Decryption
Stream
Mixer
TMDS Rx
(Port 5)
Audio Output Main
Multi-Channel
C
SPI
OSD
Main
TMDS Tx
(Port 0)
HDCP Encryption
T0X
SRC
InstaPrevue
D
HDMI/
MHL
Receiver
InstaPort
Video/
Audio
Splitter
M
U
X
F
Parallel
Video
Input
I2S/SPDIF
Audio Input
M
U
X
B
M
U
X
I2S/SPDIF/
DSD
M
U
X
A
R5X
D[19..0]
RnPWR5V,
SBVCC5V
Power
INT
TPI HW
R0X
CEC A1
CEC Interface
Controller 1
CEC Interface
Controller 0
Mobile HD
Control
M
U
X
M
U
X
G
Sub
TMDS Tx
(Port 1)
HDCP Encryption
Audio Output Sub
2 Channel
T1X
I2S/SPDIF
ENB
Audio Input
Video
Pattern
Generator
ARC0/1 Rx
ARC0/1 Tx
ARC
Input
and
Output
Figure 2.1. Functional Block Diagram
2.1. Always-on Section
2
The Always-on section contains the low speed control circuits of the HDMI connection, and includes the I C interfaces,
internal memory blocks, and the registers that control the blocks of the Power-down section.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
9
SiI9573 and SiI9575 Port Processor
Data Sheet
2.1.1. Serial Ports Block
2
The Serial Ports Block provides eight I C serial interfaces: six DDC ports to communicate with the HDMI or DVI hosts,
2
one VGA DDC port, and one local I C port for initialization and control by a local microcontroller in the display or AVR.
2
Each interface is 5 V tolerant. Figure 2.2 shows the connection of the local I C port to the system microcontroller.
VDD33 Standby Power
SiI957n
Port Processor
CSDA
CSCL
System
Microcontroller
INT
2
Figure 2.2. I C Control Configuration
The seven DDC interfaces (DDC 0–6) on the SiI957n port processor are slave interfaces that can run up to 400 kHz. Each
interface connects to one E-DDC bus and is used to read the integrated EDID and HDCP authentication information. The
port is accessible on the E-DDC bus at device addresses 0xA0 for the EDID and 0x74 for HDCP control. The transmitter
2
DDC master controller supports accessing HDCP and EDID up to 100 kHz. Local I C can also access the transmitter DDC
bus; in this case, an internal oscillator provides the clock source.
2.1.2. Static RAM Block
The Static RAM (SRAM) Block contains 2,560 bytes of RAM. Each port is allocated a 256-byte block for DDC; this allows all
ports to be read simultaneously from six different sources connected to the SiI957n device. A 128-byte block is available
for VGA DDC, 768 bytes are available for Key Selection Vectors (KSV), 64 bytes are used for the auto-boot feature, and 64
bytes are reserved. Every EDID and SHA KSV has an offset location. The SRAM can be written to and read from using the
2
local I C interface and it can be read through the DDC interface. The memory can be read through the DDC interface
without main TV power, using only 5 V power from the HDMI connector.
2.1.3. NVRAM Block
The port processor contains 512 bytes of NVRAM, 256 of which is used to store common EDID data used by each of the
ports, 128 of which is used for VGA DDC, and 64 of which is used by the auto boot feature. 64 bytes are unused. Both
2
the NVRAM EDID data and NVRAM auto-boot data should be initialized by software using the local I C bus at least once
during the time of manufacture.
2.1.4. HDCP Registers Block
The HDCP Registers Block controls the necessary logic to decrypt the incoming audio and video data. The decryption
process is controlled entirely by the host-side microcontroller using a set sequence of register reads and writes through
the DDC channel. The decryption process uses preprogrammed HDCP keys and Key Selection Vector (KSV) stored in the
on-chip nonvolatile memory.
2.1.5. OTP ROM Block
The Receiver One-Time Programmable (OTP) ROM Block is preprogrammed at the factory with HDCP keys. System
manufacturers do not need to purchase key sets from Digital Content Protection, LLC. Lattice Semiconductor handles all
purchasing, programming, and security for the HDCP keys. The preprogrammed HDCP keys provide the highest level of
security possible, as it is not possible to read out the keys after they are programmed.
2.1.6. Booting Sequencer
The Booting Sequencer boots up the required data, such as EDID, initial HPD status, and MHL port selection from
NVRAM during power on.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
2.1.7. Configuration, Status, and Interrupt Control Block
The Configuration, Status, and Interrupt Control Registers Block incorporate the registers required for configuring and
managing the features of the SiI957n port processor. These registers are grouped by functions such as RPI, TPI, CPI,
MHL, and miscellaneous and are used to perform audio, video, and auxiliary format processing, HDMI 1.4a InfoFrame
2
Packet format, and power-down control. The registers are accessible from the local I C port. This block also handles
interrupt operation.
2.1.8. Mobile HD Control Block
The Mobile HD Control Block handles MHL DDC control. This block handles CBUS conversion to DDC signals for
accessing the EDID and HDCP interface blocks.
2.1.9. CEC Interface Controller
Two independent Consumer Electronics Control (CEC) interface controllers are available in the SiI957n port processor.
This gives the system designer the option to design a system that supports both primary CEC line and a secondary CEC
line that are not physically connected to each other. For example, using an AVR featuring two DTV connections from the
SiI957n device, the primary CEC line (CEC_A0 pin) can be connected to the CEC signal of all HDMI input ports of the AVR
while the secondary CEC line (CEC_A1 pin) connects to the CEC signal of the second DTV.
Each CEC interface controller provides a CEC-compliant signal and has a high-level register interface accessible through
2
the I C interface. Programming is done through the Lattice Semiconductor CEC Programming Interface (CPI). This
controller makes CEC control easy and straightforward by removing the burden of requiring that the host processor
perform these low-level transactions on the CEC bus. As a result, CEC pass-through mode is neither required nor
supported.
The CEC controllers (CEC_A0 and CEC_A1) are identical except for the device address used to access them.
2.1.10. Power Block
The Power Block features an analog power multiplexer with inputs from the +5 V power from the R[0–5]PWR5V and the
SBVCC5V sources. The output of the analog power multiplexer supplies power to the Always-On Section.
2.2. Power-down Section
The Power-down Section contains the HDMI high-speed data paths, including the analog TMDS input and output blocks
and the digital logic for HDMI data and HDCP processing.
2.2.1. TMDS Receiver Blocks
The TMDS Receiver Blocks, defined as Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5, are terminated separately,
2
equalized under the control of the receiver digital block, and controlled by the local I C bus. Input data is over-sampled
by five to enable the downstream DPLL block to capture the most stable signal at any given time.
2.2.2. 6:1 Input Multiplexer Blocks A and B and 4:1 Input Multiplexer Blocks C and D
6:1 Input Multiplexer Block A selects one of the six TMDS inputs and sends it to the main pipe. 6:1 Input Multiplexer
Block B selects one of the six TMDS inputs and sends it to the subpipe. 4:1 Input Multiplexer Block C selects among
main pipe, subpipe, parallel video, and video pattern generator sources and sends it to HDMI output Tx0. 4:1 Input
Multiplexer Block D selects among main pipe, subpipe, parallel video, and video pattern generator sources and sends it
to HDMI output Tx1. The specific function of the multiplexers is determined by whether InstaPort, InstaPrevue, or
matrix switch mode is enabled.
In InstaPort or InstaPrevue modes, Multiplexer Block A selects the active input and sends it to the main pipe for
processing. The subpipe functions as a roving pipe whereby Multiplexer Block B sequentially selects one of the five
inactive inputs and sends it to the InstaPort or InstaPrevue blocks for processing. Multiplexer Blocks C and D can each
independently select among main pipe, parallel video, and video pattern generator sources to send to HDMI output Tx0
and Tx1 respectively.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
11
SiI9573 and SiI9575 Port Processor
Data Sheet
In matrix switch mode, Multiplexer Block A selects one active input and sends it to the main pipe for processing. roving
is disabled and the subpipe functions as a second processing pipe for another active input selected by Multiplexer Block
B. Multiplexer Blocks C and D can each independently select between main pipe and subpipe sources to send to HDMI
output Tx0 and Tx1, respectively. Matrix Switch mode is supported on the SiI9575 device only.
2.2.3. HDMI, MHL, and InstaPort Receiver Blocks
The HDMI, MHL, and InstaPort Receiver blocks perform functions including deskewing, analyzing packets, processing
the main pipe and roving pipe, multiplexing, demultiplexing, repeater functions, and HDCP authentication. The SiI957n
device supports six HDMI input ports. MHL can be enabled on any two input ports selected at the time of manufacture
by programming a register in the NVRAM.
2.2.4. Video/Audio Splitter Block
The Video/Audio Splitter Block separates the video and audio data from the TMDS stream for the roving pipe. The video
is sent to the InstaPrevue block and the audio is sent to Multiplexer Blocks C and D. This can be used in the InstaPrevue
Picture-In-Picture (PIP) mode in which a single sub-window is displayed on the main video. The audio from the subwindow can replace the audio from the main video before being sent to Tx0 and Tx1.
2.2.5. InstaPrevue Block
The InstaPrevue Block captures and processes all of the preauthenticated HDMI/DVI/MHL subframe images from the
roving pipe. The operating preview mode is configured in this block.
2.2.6. Stream Mixer Block
The Stream Mixer Block replaces a region of the main port video with a sub-frame image from the InstaPrevue block. It
merges sub-frames with the main video input at the proper screen locations specified by external software register
settings.
2.2.7. 2:1 Input Multiplexer Blocks E and F and Main and Subaudio Formatting Blocks
2:1 Input Multiplexer Block E selects either the decoded audio stream from the TMDS input to main pipe or the subpipe
2
and sends it to the main audio block to be processed as I S and S/PDIF. The main audio block supports 8-channel PCM
2
and 6-channel DSD for I S and 2-channel PCM and compressed audio formats for S/PDIF. 2:1 Input Multiplexer Block F
selects either the decoded audio stream from the TMDS input to main pipe or the subpipe and sends it to the subaudio
2
2
block to be sent out as I S and S/PDIF. The subaudio block supports 2-channel PCM for I S and 2-channel PCM and
compressed audio formats for S/PDIF.
2.2.8. Parallel Video Input Block
The Parallel Video Input Block features a 20-bit parallel video input interface which supports input clocks up to 165 MHz
in dual edge and single edge modes. In dual edge mode, incoming data is latched on both edges of the clock for double
data rate (DDR) to support up to 720p/1080i @ 60 Hz for RGB/YCbCr 4:4:4 formats. In single edge mode, incoming data
is latched on one edge of the clock for single data rate (SDR) to support up to 1080p @ 60 Hz and UXGA @ 60 Hz for
YCbCr 4:2:2 formats.
Video processing features support color space conversion, 4:2:2 to 4:4:4 up- and 4:4:4 to 4:2:2 down-sampling, RGB
range expansion, RGB/YCbCr range compression, clipping, and dithering functions. All of these functions can be
bypassed through register settings.
The color space conversion feature performs color conversion from YCbCr to RGB and RGB to YCbCr according to the
selected color space standard ITU-R BT.601 for standard-definition DTV and ITU-R BT.709 for high-definition DTV.
Chrominance up-sampling increases the number of chrominance samples in each line of video. Up-sampling doubles
the number of chrominance samples in each line, converting 4:2:2 sampled video to 4:4:4 sampled video.
Chrominance down-sampling decreases the number of chrominance samples in each line of video. Down-sampling
halves the number of chrominance samples in each line, converting 4:4:4 sampled video to 4:2:2 sampled video.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
The SiI957n port processor can scale the input color range from limited-range into full range using the range expansion
block. When enabled by itself, the range expansion block expands 16–235 limited-range data into 0–255 full-range data
for each video channel. When range expansion and the YCbCr to RGB color space converter are both enabled, the input
conversion range for the Cb and Cr channels is 16–240.
When enabled by itself, the range compression block compresses 0–255 full range data into 16–235 limited range data
for each video channel. When enabled with the RGB to YCbCr converter, this block compresses to 16–240 for the Cb and
Cr channels. The color range scaling is linear.
When enabled, the clipping block clips the values of the output video to 16–235 for RGB video for the Y channel, and to
16–240 for the Cb and Cr channels.
The SiI957n port processor can dither the video by adding a pseudorandom number to every value. The 18-bit dithering
result can be truncated or rounded. Additionally, dithering can be enabled or disabled by video component (R, G, B, Y,
Cb, or Cr).
2.2.9. Video Pattern Generator Block
The Video Pattern Generator (VPG) Block supplies one of eight predefined video patterns to the HDMI transmitters. The
predefined video patterns are solid red, solid green, solid blue, solid black, solid white, ramp, 8 × 6 chessboard, and
color bars. The video patterns have an RGB color space at 480p, 576p, and 720p video resolutions.
An example use for the VPG is to combine the predefined video pattern with an external audio input to create a
complete HDMI stream which can then be sent out of the HDMI transmitter to a sound bar. The VPG can also be used
for test purposes during product development.
The VPG requires a pixel clock for its operation. One of several clock sources, including the crystal oscillator (xclk), audio
VCO clock 0, or audio VCO clock 1, can be used to generate the pixel clock for the VPG. If the crystal oscillator (xclk),
audio VCO clock 0, or audio VCO clock 1 is used as the clock source for the VPG, then the frequency of the external
audio crystal must be 27 MHz to generate the correct pixel clock frequencies for the VPG. Incorrect pixel clock
frequencies will be generated if the external audio crystal used is not 27 MHz; the range specified in Table 3.20 on page
23 will not work for this function. The xclk is generated from the external audio crystal. The audio VCO clock 0 is an
output of a PLL which uses the xclk as the input. The audio VCO clock 1 is an output of another PLL which also uses the
xclk as the input. Table 2.1 shows the pixel clock source and frequency for the VPG at 480p, 576p and 720p video
resolutions. Refer to the Programmer’s Reference for details on configuring the VPG.
Table 2.1. Pixel Clock Source and Frequency
Video Resolution
480p, 576p
Pixel Clock Source
xclk
Pixel Clock Frequency
27 MHz
720p
audio VCO clock 0 or audio VCO clock 1
(27 MHz) • (11/4) = 74.25 MHz
The audio VCO clock 0 and VCO clock 1 PLLs are shared with the audio extraction logic. Therefore, if audio VCO clock 0
or VCO clock 1 is used for the VPG, the respective main or subport audio extraction mode needs to be disabled.
2.2.10. Audio Sampling Rate Converter Block
The audio Sampling Rate Converter (SRC) Block allows the inserted 2-channel PCM audio from either the main- or subaudio ports to be down-sampled before combining with the HDMI stream from the main pipe and sending to Tx0. The
audio data can be down-sampled by a factor of 2 or 4 by register control. Conversions from: 192 kHz to 48 kHz,
176.4 kHz to 44.1 kHz, 96 kHz to 48 kHz, and 88.2 kHz to 44.1 kHz are supported.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
13
SiI9573 and SiI9575 Port Processor
Data Sheet
2.2.11. On-screen Display Controller
The On-screen Display Controller (OSD) Block supports a text-based onscreen display that allows for up to four
character-based windows to be overlaid onto the video displayed from the Tx0 HDMI output. The OSD supports three
font sizes: 12×16, 16 × 24 and 24 × 32 pixels, to provide flexibility for choosing the character and icon size in the OSD
windows.
OSD supports 480p, 576p, 720p, 1080p, and 1080iHDMI 2D video formats. OSD is supported on SiI957n Tx0 HDMI
output only. OSD may be combined on the displayed video along with InstaPrevue windows to form a complete menu
system.
A 12 kB on-chip RAM memory stores the OSD font bit maps and window index information. The OSD memory can be
2
loaded by the host microcontroller through the I C bus or from an external flash memory though the Serial Peripheral
Interface (SPI). The SPI supports clock frequencies of 1.6875 MHz, 3.375 MHz, 13.5 MHz, and 27 MHz. This interface is
used to read and write the external flash memory. In addition, the host microcontroller can program the external flash
2
memory using I C through the SPI interface.
2.2.12. Audio Input Block
The Audio Input Block supports external audio insertion into the transmitted HDMI streams. There are two audio input
2
blocks: the main audio port and the subaudio port. The inserted audio to the main audio port is two-channel I S or a
2
single S/PDIF. Similarly, the inserted audio to the subaudio port is two-channel I S or a single S/PDIF.
Both main audio port and subaudio port insertion support the following audio formats:

2
I S: 2 channels


PCM: 2 channels
S/PDIF: IEC 60958 and IEC 61937

PCM: 2channels

Compressed bit-stream: Dolby Digital, Dolby Digital Plus, Dolby Digital EX, Dolby Digital Surround EX DTS, DTS
ES
®
2
2
Each of the SiI957n I S main and subaudio port insertion requires SCK, WS, and SD0 signals for two channel I S. For both
the main and subaudio ports, the SiI957n device supports CTS and N value generation without requiring an MCLK input.
2
The SiI957n main audio port S/PDIF insertion shares the same pin with SD0 of the I S insertion. The function of this pin
is configured by software.
2
The SiI957n subaudio port S/PDIF insertion shares the same pin with SD0 of the I S insertion. The function of this pin is
2
configured by software. In addition, the subaudio port I S and S/PDIF insertion pins are multiplexed with the subaudio
2
port I S and S/PDIF extraction pins. The functions of these pins are configured by software.
The audio inserted into the main audio port can be combined with the HDMI stream from the main pipe and sent to Tx0
or combined with the HDMI stream from the subpipe and sent to Tx1. Similarly, the audio inserted to the subaudio port
can be combined with the HDMI stream from the main pipe and sent to Tx0 or combined with the HDMI stream from
the subpipe and sent to Tx1. The audio sampling rate converter block selects between inserted audio from the main
audio port and the subaudio port to send to Tx0. Input Multiplexer G selects between inserted audio from the main
audio port and the subaudio port to send to Tx1.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
2.2.13. Audio Output Block
The Audio Output Block supports audio extraction from the received HDMI/MHL streams. There are two audio output
blocks, the main audio port and the subaudio port. The extracted audio from the main audio port is eight-channel I2S,
six-channel DSD, or a single S/PDIF audio. The extracted audio from the subaudio port is either two-channel I2S or
single S/PDIF audio.


Main Audio Port Extraction

I S: 8 channels
PCM: up to 8 channels
HBR: Dolby TrueHD, DTS-HD Master Audio

DSD: 6 channels

S/PDIF: IEC 60958 and IEC 61937
PCM: 2 channels
Compressed bit-stream: Dolby Digital, Dolby Digital Plus, Dolby Digital EX, Dolby Digital Surround EX, DTS,
DTS-ES
2
Subaudio Port Extraction

I S: 2 channels
PCM: 2 channels

S/PDIF: IEC 60958 and IEC 61937
PCM: 2 channels
Compressed bit-stream: Dolby Digital, Dolby Digital Plus, Dolby Digital EX, Dolby Digital Surround EX, DTS,
DTS-ES
2
2
By default, the main audio port is configured for eight-channel I S audio extraction from the main pipe and the
2
subaudio port is configured for two-channel I S audio extraction from the subpipe. The SiI957n device allows swapping
2
2
the main and subaudio ports to provide two-channel I S audio extraction from the main pipe and eight-channel I S
audio extraction from the subpipe.
2
2
The SiI957n I S audio extraction provides the MCLK, SCK, WS, SD0, SD1, SD2, and SD3 signals for eight-channel I S from
2
the main audio port and SCK, WS, and SD0 for two-channel I S for the subaudio port. To generate the MCLK for the
subaudio port, an external PLL clock generator can be used.
2
The SiI957n main audio port I S, DSD, and S/PDIF audio extraction pins are shared. The functions of these pins are
configured by software.
2
The SiI957n subaudio port S/PDIF audio extraction shares the same pin with SD0 of the I S audio extraction. The
2
function of this pin is configured by software. In addition, the subaudio port I S and S/PDIF audio extraction pins are
2
multiplexed with the subaudio port I S and S/PDIF audio insertion pins. The functions of these pins are configured by
software.
2.2.14. Audio Return Channel (ARC) Input and Output
The Audio Return Channel (ARC) feature eliminates an extra cable when sending audio from an HDMI sink device to an
adjacent HDMI source or repeater device. This is done by allowing a single IEC60958-1 or IEC61937 audio stream to
travel in the opposite direction of the TMDS signal on its own conductor in the HDMI cable, after negotiation using CEC
Audio Return Channel Control. The HDMI sink device implements the ARC transmitter and the HDMI source or repeater
device implements the ARC receiver.
The SiI957n device provides two ARC transceiver channels. Each pin can be independently configured to operate as an
ARC transmitter or an ARC receiver. For example, the SiI957n device designed into a DTV can use the ARC transmitter
feature while the SiI957n device designed into an AVR can use the ARC receiver feature. For an ARC transmitter, the
ARC transceiver pin is connected to the ARC pin of the connector for the HDMI Rx port that is designated as ARCcapable. For an ARC receiver, the ARC transceiver pin is connected to the ARC pin of the HDMI connector for the
transmitter port that is designated as ARC-capable.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
15
SiI9573 and SiI9575 Port Processor
Data Sheet
ARC transceivers can share pins with the HDMI Ethernet Channel (HEC) signals. The SiI957n device does not support
HEC and therefore cannot use HEC and ARC simultaneously on the same receiver port.
The SiI957n device supports only single mode ARC. The SiI957n ARC receiver can be made compatible for common
mode ARC by using an AC-coupling network between the HPD and NC pins of the HDMI connector of the transmitter
port and the SiI957n ARC receiver pin.
2.2.15. TMDS Transmitter Block
The TMDS Transmitter Blocks perform HDCP encryption and 8-to-10-bit TMDS encoding on the data to be transmitted
over the HDMI link. The encoded data is sent to the three TMDS differential data lines, along with a TMDS differential
clock line. Internal source termination eliminates the need to use external R-C components for signal shaping. The
internal source termination can be disabled by registers settings. The SiI957n port processor integrates two HDMI
output ports, which enables zone-2 support by using the ViaPort Matrix Switch feature of the device. Both transmitter
ports support up to 300 MHz.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
3. Electrical Specifications
3.1. Absolute Maximum Conditions
Table 3.1. Absolute Maximum Conditions
Symbol
AVDD33
Parameter
TMDS core supply voltage
Min
−0.3
Typ
—
Max
4.0
Unit
V
Notes
1, 2
IOVCC33
I/O supply voltage
−0.3
—
4.0
V
1, 2
SBVCC5
5 V standby power supply voltage
−0.3
—
5.7
V
1, 2
R[0–5]PWR5V
5 V input from power pin of HDMI connector
−0.3
—
5.7
V
1, 2
XTALVCC33
PLL crystal oscillator power
−0.3
—
4.0
V
1, 2
AVDD13
TMDS receiver core supply voltage
−0.3
—
1.5
V
1, 2
APLL13
PLL Analog VCC
−0.3
—
1.5
V
1, 2
CVCC13
Digital core supply voltage
−0.3
—
1.5
V
1, 2
TDVDD13
TMDS transmitter core supply voltage
−0.3
—
1.5
V
1, 2
TPVDD13
TMDS transmitter core supply voltage
−0.3
—
1.5
V
1, 2
VI
Input voltage
−0.3
—
IOVCC33 + 0.3
V
1, 2
VO
Output voltage
−0.3
—
IOVCC33 + 0.3
V
1, 2
TJ
Junction temperature
0
—
125
C
—
TSTG
Storage temperature
−65
—
150
C
—
Notes:
1. Permanent damage can occur to the device if absolute maximum conditions are exceeded.
2. Functional operation should be restricted to the conditions described in the Normal Operating Conditions section below.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
17
SiI9573 and SiI9575 Port Processor
Data Sheet
3.2. Normal Operating Conditions
Table 3.2. Normal Operating Conditions
Symbol
AVDD33
Parameter
TMDS core supply voltage
Min
3.14
Typ
3.3
Max
3.46
Unit
V
Notes
—
IOVCC33
I/O supply voltage
3.14
3.3
3.46
V
—
SBVCC5
5 V standby power supply voltage
4.5
5.0
5.5
V
1
R[0–5]PWR5V
5 V input from power pin of HDMI connector
4.5
5.0
5.5
V
—
XTALVCC33
PLL crystal oscillator power
3.14
3.3
3.46
V
—
AVDD13
TMDS receiver core supply voltage
1.25
1.3
1.35
V
2
APLL13
PLL Analog VCC
1.25
1.3
1.35
V
2
CVCC13
Digital core supply voltage
1.25
1.3
1.35
V
2
TDVDD13
TMDS transmitter core supply voltage
1.25
1.3
1.35
V
2
TPVDD13
TMDS transmitter core supply voltage
1.25
1.3
1.35
V
2
AVDD13
TMDS receiver core supply voltage
1.27
1.3
1.35
V
3
APLL13
PLL Analog VCC
1.27
1.3
1.35
V
3
CVCC13
Digital core supply voltage
1.27
1.3
1.35
V
3
TDVDD13
TMDS transmitter core supply voltage
1.27
1.3
1.35
V
3
TPVDD13
TMDS transmitter core supply voltage
1.27
1.3
1.35
V
3
TA
Ambient temperature (with power applied)
0
+25
+70
C
—
ja
Ambient thermal resistance (Theta JA)
—
22.0
—
C/W
—
jc
Junction to case resistance (Theta JC)
—
—
6.0
C/W
—
Notes:
1. SBVCC5 voltage is measured at SBVCC5TP as shown in Figure 3.1.
2. For 4 HDMI Inputs and 2 HDMI output running simultaneously at 300MHz
3. For 5 or 6 HDMI Inputs and 2 HDMI Outputs running simultaneously at 300MHz
SBVCC5TP
10Ω
SBVCC5
10 F
0.1 F
SiI957n
GND
Figure 3.1. Test Point SBVCC5TP for SBVCC5 Measurement
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
3.3. DC Specifications
Table 3.3. Digital I/O DC Specifications
Symbol
VIH
Parameter
HIGH-level Input Voltage
Pin Type
LVTTL
Conditions
—
Min
2.0
Typ
—
Max
—
Unit
V
VIL
LOW-level Input Voltage
LOW-to-HIGH Threshold,
DDC Buses
HIGH-to-LOW Threshold,
DDC Buses
LVTTL
—
—
—
0.8
V
Schmitt
—
3.0
—
—
V
Schmitt
—
—
—
1.5
V
Schmitt
—
2.0
—
—
V
Schmitt
—
—
—
0.8
V
LVTTL
LVTTL
—
—
2.4
—
—
—
—
0.4
V
V
—
High Impedance
−10
—
10
4 mA Digital Output Drive
LVTTL
VOUT = 2.4 V
VOUT = 0.4 V
4
4
—
—
—
—
A
mA
mA
LOW-to-HIGH Threshold,
Reset
Schmitt
—
2.0
—
—
V
Schmitt
—
—
—
0.8
V
All
—
—
—
V
All
—
—
—
GND –0.3
IOVCC33
+0.3
VTH+DDC
VTH-DDC
VTH+I2C
VTH-I2C
LOW-to-HIGH Threshold,
2
I C Buses
HIGH-to-LOW Threshold,
2
I C Buses
VOH
VOL
HIGH-level Output Voltage
LOW-level Output Voltage
IOL
Output Leakage Current
IOD4
VTH+RESET
VCINL
HIGH-to-LOW Threshold,
Reset
Input Clamp Voltage
VCIPL
Input Clamp Voltage
VTH-RESET
V
Table 3.4. TMDS Input DC Specifications – HDMI Mode
Symbol
VID
Parameter
Differential Mode Input Voltage
VICM
Common Mode Input Voltage
Conditions
—
Min
150
Typ
—
Max
1200
Units
mV
—
AVDD33
–400
—
AVDD33
–37.5
mV
Table 3.5. TMDS Input DC Specifications – MHL Mode
Symbol
Parameter
Conditions
Min
AVDD33
–1200
Typ
VIDC
Single-ended Input DC Voltage
—
VIDF
Differential Mode Input Swing Voltage
—
200
—
VICM
Common Mode Input Swing Voltage
—
170
—
—
Max
AVDD33
–300
Units
1000
Min (720,
0.85 VIDF)
mV
mV
mV
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
19
SiI9573 and SiI9575 Port Processor
Data Sheet
Table 3.6. TMDS Output DC Specifications
Symbol
VSWING
Parameter
Single-ended Output Swing Voltage
Conditions
RLOAD = 50 Ω
Min
400
AVDD33
–200
AVDD33
–700
Typ
—
VH
Single-ended High-level Output Voltage
—
VL
Single-ended Low-level Output Voltage
—
VTH+RSEN
LOW-to-HIGH Threshold, RSEN
VTH-RSEN
Notes:
4.
5.
HIGH-to-LOW Threshold, RSEN
Max
600
AVDD33
+10
AVDD33
–400
Units
mV
Notes
—
mV
—
mV
—
—
0.8
—
1.1
V
1
—
0.3
—
0.5
V
2
—
—
RSEN deasserted state to asserted state threshold voltage when sink Rx termination transitions from disabled to enabled.
RSEN asserted state to deasserted state threshold voltage when sink Rx termination transitions from enabled to disabled.
Table 3.7. Single Mode Audio Return Channel DC Specifications
Symbol
Vel
Vel swing
Parameter
Operating DC Voltage
Swing Amplitude
Conditions
—
—
Min
0
400
Typ
—
—
Max
5
600
Units
V
mV
Table 3.8. S/PDIF Input Port DC Specifications
Symbol
Parameter
ZI_SPDIF
Termination Impedance
VI_SPDIF
Input Voltage
Notes:
1.
2.
3.
Conditions
—
—
75 Ω
termination,
AC-coupled
Min
—
—
Typ
75
4
Max
—
—
Units
Ω
kΩ
Notes
1
2
400
—
600
mVPP
3
This impedance is implemented with an external 75 Ω resistor to ground and is used when the interconnection is over a 75
Ω COAX cable.
This is the internal impedance of the S/PDIF input.
The S/PDIF input can also be safely driven at LVTTL voltage levels without AC coupling. The 75 Ω termination is not
required in this case.
Table 3.9. CEC DC Specifications
Symbol
VTH+CEC
VTH-CEC
Parameter
LOW to HIGH Threshold
HIGH to LOW Threshold
VOH_CEC
VOL_CEC
HIGH-level Output Voltage
LOW-level Output Voltage
IIL_CEC
Input Leakage Current
Conditions
—
—
Min
2.0
—
Typ
—
—
Max
—
0.8
Units
V
V
—
—
Power Off;
RnPWR5V = 0 V
2.5
—
—
—
—
0.6
V
V
—
—
1.8
A
Table 3.10. CBUS DC Specifications
Symbol
VIH_CBUS
VIL_CBUS
Parameter
High-level Input Voltage
Low-level Input Voltage
Conditions
—
—
Min
1.0
—
Typ
—
—
Max
—
0.6
Units
V
V
VOH_CBUS
High-level Output Voltage
IOH = 100 A
1.5
—
1.9
V
VOL_CBUS
Low-level Output Voltage
—
0.2
V
Pull-down Resistance – Discovery
IOL = –100 A
—
—
ZDSC_CBUS
800
1000
1200
Ω
ZON_CBUS
Pull-down Resistance – Active
100
110
kΩ
Input Leakage Current
—
High Impedance
90
IIL_CBUS
—
—
1
A
CCBUS
Capacitance
Power On
—
—
80
pF
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
Table 3.11. Power
Symbol
IAPLL13
Parameter
Supply Current for APLL13
Min
—
Typ
—
Max
3
Unit
mA
Notes
1
IAVDD13
Supply Current for AVDD13
—
—
250
mA
1
IAVDD33
Supply Current for AVDD33
—
—
345
mA
1
IIOVCC33
Supply Current for IOVCC33
—
—
2
mA
1
IXTALVCC33
Supply Current for XTALVCC33
—
—
<1
mA
1
ICVCC13
Supply Current for CVCC13
—
—
680
mA
1
ISBVCC5STBY
Supply Current for SBVCC5 in Standby mode
—
—
8
mA
2
ISBVCC5ACT
Supply Current for SBVCC5 in Active mode
—
—
30
mA
1
ITDVDD13
Supply Current for TDVDD13
—
—
60
mA
1
ITPVDD13
Supply Current for TPVDD13
—
—
30
mA
1
Total
Total Power
—
—
2.6
W
1
Notes:
1. With six 300 MHz HDMI receiver inputs with InstaPort, InstaPrevue, audio outputs, and OSD on and two 300 MHz transmitter
outputs.
2. With no active AV sources connected to the HDMI Rx inputs.
3.4. AC Specifications
Table 3.12. TMDS Input Timing AC Specifications – HDMI Mode
Symbol
TRXDPS
Parameter
Intrapair Differential Input Skew
TRXCCS
Channel-to-Channel Differential Input Skew
FRXC
Differential Input Clock Frequency
TRXC
Differential Input Clock Period
TIJIT
Differential Input Clock Jitter Tolerance (0.3Tbit)
Conditions
—
Min
—
Typ
—
Max
0.4
Units
TBIT
—
—
—
0.2TPIXEL
+ 1.78
ns
—
25
—
300
MHz
—
3.33
—
40
ns
300 MHz
—
—
100
ps
Conditions
—
Min
—
Typ
—
Max
93
Units
ps
Table 3.13. TMDS Input Timing AC Specifications – MHL Mode
Symbol
TSKEW_DF
Parameter
Input Differential Intrapair Skew
TSKEW_CM
FRXC
Input Common-mode Intrapair Skew
Differential Input Clock Frequency
—
—
—
25
—
—
93
75
ps
MHz
TRXC
Differential Input Clock Period
—
13.33
—
ns
TCLOCK_JIT
Common Mode Clock Jitter Tolerance
—
—
—
TDATA_JIT
Differential Data Jitter Tolerance
—
—
—
40
0.3TBIT
+ 266.7
0.4TBIT +
88.88
ps
ps
Table 3.14. TMDS Output Timing AC Specifications
Symbol
TTXDPS
Parameter
Intrapair Differential Output Skew
Conditions
—
Min
—
Typ
—
Max
0.15
Units
TBIT
TTXRT
TTXFT
FTXC
Data/Clock Rise Time
Data/Clock Fall Time
Differential Output Clock Frequency
20%–80%
80%–20%
—
75
75
25
—
—
—
—
—
300
ps
ps
MHz
TTXC
TDUTY
Differential Output Clock Period
Differential Output Clock Duty Cycle
—
—
3.33
40%
—
—
40
60%
ns
TTXC
TOJIT
Differential Output Clock Jitter
—
—
—
0.25
TBIT
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
21
SiI9573 and SiI9575 Port Processor
Data Sheet
Table 3.15. Single Mode Audio Return Channel AC Specifications
Symbol
TASMRT
TASMFT
Parameter
Rise Time
Fall Time
TASMJIT
FASMDEV
Jitter Max
Clock Frequency Deviation
Conditions
10%–90%
90%–10%
Min
—
—
Typ
—
—
Max
60
60
Units
ns
ns
—
—
—
–1000
—
—
0.05
1000
UI*
ppm
*Note: Proportional to unit time (UI), according to sample rate. Refer to the S/PDIF specification.
Table 3.16. CEC AC Specifications
Symbol
TR_CEC
Parameter
Rise Time
Conditions
10%–90%
Min
—
Typ
—
Max
250
Units
s
TF_CEC
Fall Time
90%–10%
—
—
50
s
Conditions
1 MHz clock
Min
0.8
Typ
—
Max
1.2
—
–1%
—
+1%
Units
s
TBIT_CBUS
—
0.2 V–1.5 V
0.2 V–1.5 V
40%
5
5
—
—
—
60%
200
200
TBIT_CBUS
ns
ns
—
—
—
100
ns
Table 3.17. CBUS AC Specifications
Symbol
TBIT_CBUS
Parameter
Bit Time
TBJIT_CBUS
Bit-to-Bit Jitter
TDUTY_CBUS
TR_CBUS
TF_CBUS
Duty Cycle of 1 Bit
Rise Time
Fall Time
ΔTRF
Rise-to-Fall Time Difference
Table 3.18. Video Input Timing AC Specifications
Symbol
TCIP
FCIP
TCIP12
Parameter
IDCK Period, One Pixel per Clock
IDCK Frequency, One Pixel per Clock
IDCK Period, Dual-edge Clock
Conditions
—
—
—
Min
6.06
25
12.12
Typ
—
—
—
Max
40
165
40
Units
ns
MHz
ns
Figure
—
—
—
Notes
1
1
2
FCIP12
TDUTY
IDCK Frequency, Dual-edge Clock
IDCK Duty cycle, One Pixel per Clock
—
—
25
40%
—
—
82.5
60%
MHz
TCIP
—
Figure 4.1
2
—
TDUTY12
TIJIT
TSIDF
IDCK Duty Cycle, Dual-edge Clock
Worst Case IDCK Clock Jitter
Setup Time to IDCK Falling Edge
—
—
45%
—
1.0
—
—
—
55%
1.0
—
TCIP12
ns
ns
Figure 4.1
—
—
3, 4
5
THIDF
TSIDR
Hold Time to IDCK Falling Edge
Setup Time to IDCK Rising Edge
2.2
1.0
—
—
—
—
ns
ns
THIDR
TSIDD
THIDD
Hold Time to IDCK Rising Edge
Setup Time to IDCK Rising or Falling Edge
Hold Time to IDCK Rising or Falling Edge
2.2
1.0
2.2
—
—
—
—
—
—
ns
ns
ns
EDGE = 0
EDGE = 1
Dual-edge
Clocking
Figure 4.3
Figure 4.2
Figure 4.4
5
6
Notes:
1. TCIP and FCIP apply in single-edge clocking modes. TCIP is the inverse of FCIP and is not a controlling specification.
2. TCIP12 and FCIP12 apply in dual-edge mode. TCIP12 is the inverse of FCIP12 and is not a controlling specification.
3. Input clock jitter is estimated by triggering a digital scope at the rising edge of the input clock, and measuring peak-to-peak time
spread of the rising edge of the input clock 1 microsecond after the triggering.
4. Actual jitter tolerance can be higher depending on the frequency of the jitter.
5. Setup and hold time specifications apply to Data, DE, VSYNC, and HSYNC input pins, relative to IDCK input clock.
6. Setup and hold limits are not affected by the setting of the EDGE bit for 8/10/12-bit dual-edge clocking mode.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
3.4.1. Control Signal Timing Specifications
Under normal operating conditions unless otherwise specified.
Table 3.19. Control Signal Timing Specifications
Symbol
TRESET
TI2CDVD
Parameter
RESET# signal LOW time required for reset
SDA Data Valid Delay from SCL falling edge on
READ command
tSU;DAT
I C data setup time
THDDAT
I C data hold time
Response time for INT output pin from change in
input condition (HPD, Receiver Sense, VSYNC
change, etc.).
TINT
Conditions
—
CL = 400pF
Min
50
Typ
—
Max
—
700
Units
µs
ns
—
—
2
—
210
2
0–400 kHz
2.0
RESET# =
HIGH
—
Notes
1, 5
2, 6
—
—
ns
7
—
—
ns
3, 6
—
100
µs
—
FSCL
Frequency on master DDC SCL signal
—
40
70
100
kHz
4
FCSCL
Frequency on master CSCL signal
—
40
—
400
kHz
—
Notes:
1. Reset on RESET# signal can be LOW as the supply becomes stable (shown in Figure 4.5), or pulled LOW for at least TRESET (shown
in Figure 4.6).
2
2
2. All standard-mode (100 kHz) I C timing requirements are guaranteed by design. These timings apply to the slave I C port (pins
2
CSDA and CSCL) and to the master I C port (pins DSDA and DSCL).
2
3. This minimum hold time is required by CSCL and CSDA signals as an I C slave. The device does not include the 300 ns internal
2
delay required by the I C Specification (Version 2.1, Table 5, note 2).
2
4. The master DDC block provides an SCL signal for the E-DDC bus. The HDMI Specification limits this to I C Standard Mode or 100
kHz. Use of the Master DDC block does not require an active IDCK.
5. Not a Schmitt trigger.
2
2
6. Operation of I C pins above 100 kHz is defined by LVTTL levels VIH, VIL, VOH, and VOL. For these levels, I C speeds up to 400 kHz
(fast mode) are supported.
2
7. In default configuration, operation at 400 kHz does not meet the tSU;DAT data setup time required by the I C Specification. For
advanced configuration information, refer to SiI-PR-1054 revision D or later.
Table 3.20. Audio Crystal Frequency
Symbol
FXTAL
Parameter
External Crystal Frequency
Conditions
—
Min
26
Typ
27
Max
28.5
Units
MHz
Note: Fxtal must be 27 MHz if the crystal oscillator (xclk) is used as the clock source for the Video Pattern Generator.
3.3 V
XTALVCC33
XTALIN
C1
27 MHz
R
XTALOUT
C2
XTALGND
The values of C1, C2, and R
depend upon the
characteristics of the crystal.
Figure 3.2. Audio Crystal Schematic
Note: The XTALIN/XTALOUT pin pair must be driven with a clock in all applications.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
23
SiI9573 and SiI9575 Port Processor
Data Sheet
3.4.2. Audio Input Timing
Table 3.21. S/PDIF Input Port AC Specifications
Symbol
FS_SPDIF
Parameter
Sample Rate
Conditions
2 Channel
Min
32
Typ
—
Max
192
Units
kHz
Figure
—
Notes
—
TSPCYC
S/PDIF Cycle Time
TSPDUTY
S/PDIF Duty Cycle
Note: Refer to the notes for Table 3.22.
CL = 10 pF
CL = 10 pF
—
90%
—
—
1.0
110%
UI
UI
Figure 4.10
Figure 4.10
1
1
Conditions
—
CL = 10 pF
CL = 10 pF
Min
32
—
90%
Typ
—
—
—
Max
192
1.0
110%
Units
kHz
UI
UI
Figure
—
Figure 4.9
Figure 4.9
Notes
—
1
—
CL = 10 pF
CL = 10 pF
15
0
—
—
—
—
ns
ns
Figure 4.9
Figure 4.9
2
2
2
Table 3.22. I S Input Port AC Specifications
Symbol
FS_I2S
TSCKCYC
TSCKDUTY
Parameter
Sample Rate
2
I S Cycle Time
2
I S Duty Cycle
TI2SSU
TI2SHD
I S Setup Time
2
I S Hold Time
2
Notes:
2
1. Proportional to unit time (UI) according to sample rate. Refer to the I S or S/PDIF specifications.
2
2. Setup and hold minimum times are based on 13.388 MHz sampling, which is adapted from Figure 3 of the Philips I S
Specification.
3.4.3. Audio Output Timing
2
Table 3.23. I S Output Port AC Specifications
Symbol
TTR
Parameter
SCK Clock Period (TX)
Conditions
CL = 10 pF
Min
1.0
Typ
—
Max
—
Units
TTR
THC
SCK Clock HIGH Time
CL = 10 pF
0.35
—
—
TTR
TLC
SCK Clock LOW Time
CL = 10 pF
0.35
—
—
TTR
TSU
Setup Time, SCK to SD/WS
CL = 10 pF
0.4TTR – 5
—
—
ns
THD
Hold Time, SCK to SD/WS
CL = 10 pF
0.4TTR – 5
—
—
ns
TSCKDUTY
SCK Duty Cycle
CL = 10 pF
40
—
60
% TTR
TSCK2SD
SCK to SD or WS Delay
CL = 10 pF
–5.0
—
5.0
ns
Note: Refer to Figure 4.11 on page 29.
Table 3.24. S/PDIF Output Port AC Specifications
Symbol
TSPCYC
Parameter
SPDIF Cycle Time
Conditions
CL = 10 pF
Min
—
Typ
1.0
Max
—
Units
1
UI
FSPDIF
SPDIF Frequency
—
4.0
—
24.0
MHz
TSPDUTY
SPDIF Duty Cycle
CL = 10 pF
90.0
—
110.0
% TSPCYC
TMCLKCYC
MCLK Cycle Time
CL = 10 pF
20.0
—
250
ns
FMCLK
MCLK Frequency
CL = 10 pF
4.0
—
50.0
MHz
—
65
% TMCLKCYC
TMCLKDUTY
MCLK Duty Cycle
CL = 10 pF
45
Notes:
1. Proportional to unit time (UI), according to sample rate. Refer to the S/PDIF specification.
2. Refer to Figure 4.12 on page 29 and Figure 4.13 on page 29.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
3.5. Serial Flash SPI Interface AC Specifications
Table 3.25. Serial Flash AC Specifications
Symbol
FSCLK
Parameter
Clock Frequency
Min
1.6875
Typ
—
Max
27
Unit
MHz
TSCLKH
TSCLKL
Clock HIGH Time
Clock LOW Time
16
16
—
—
—
—
ns
ns
TSLCH
TCHSH
TDVCH
SS Active Setup Time
SS Not Active Hold Time
SDI Data Out Setup Time
11
11
6
—
—
—
—
—
—
ns
ns
ns
TCHDX
TCLQV
SDI Data Out Hold Time
Clock LOW-to-SDO Data In Valid
6
—
—
—
—
16
ns
ns
Note: Refer to Figure 4.14 on page 30.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
25
SiI9573 and SiI9575 Port Processor
Data Sheet
4. Timing Diagrams
4.1. Video Input Timing Diagrams
TCIP/TCIP12
50%
50%
50%
TDUTY /TDUTY12
Figure 4.1. IDCK Clock Duty Cycle
TCIP
IDCK
50 %
TSIDR
D[19:0] , DE,
HSYNC, VSYNC
50 %
THIDR
no change allowed
50 %
50 %
Signals may change only in the unshaded portion of the waveform
,
to meet both the
minimum setup and minimum hold time specifications
.
Figure 4.2. Control and Data Single-Edge Setup and Hold Times—EDGE = 1
IDCK
50 %
TSIDF
D[19:0] , DE,
HSYNC, VSYNC
50 %
50 %
THIDF
no change allowed
50 %
Signals may change only in the unshaded portion of the waveform
,
to meet both the
minimum setup and minimum hold time specifications
.
Figure 4.3. Control and Data Single-Edge Setup and Hold Times—EDGE = 0
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
TCIP12
IDCK
50 %
TSIDD
D[11:0], DE,
HSYNC,VSYNC
50 %
50 %
THIDD
no change
allowed
TSIDD
50 %
THIDD
no change
allowed
50 %
Signals may change only in the unshaded portion of the waveform, to meet both the
minimum setup and minimum hold time specifications.
Figure 4.4. Control and Data Dual-Edge Setup and Hold Times
4.2. Reset Timing Diagrams
VCC must be stable between the limits shown in the Normal Operating Conditions section on page 18 for TRESET before
RESET# goes HIGH, as shown in Figure 4.5. Before accessing registers, RESET# must be pulled LOW for TRESET. This can be
done by holding RESET# LOW until TRESET after stable power, or by pulling RESET# LOW from a HIGH state for at least
TRESET, as shown in Figure 4.6. Note: VCC can be one of RnPPWR5V or SBVCC5V.
VCCmax
VCCmin
VCC
TRESET
RESET#
Figure 4.5. Conditions for Use of RESET#
RESET#
TRESET
Figure 4.6. RESET# Minimum Timing
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
27
SiI9573 and SiI9575 Port Processor
Data Sheet
4.3. I2C Timing Diagrams
CSDA, DSDA
TI2CDVD
CSCL, DSCL
2
Figure 4.7. I C Data Valid Delay (Driving Read Cycle Data)
CSDA, DSDA
tSU:DAT
CSCL, DSCL
2
Figure 4.8. I C Data Setup Time
4.4. Digital Audio Input Timing
TSCKCYC
TSCKDUTY
SCK
50 %
50 %
TI2SSU
SD[0:3], WS
TI2SHD
no change allowed
50 %
50 %
2
Figure 4.9. I S Input Timing
TSPCYC
T SPDUTY
50%
SPDIF
Figure 4.10. S/PDIF Input Timing
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
4.5. Digital Audio Output Timing
TTR
TSCKDUTY
SCK
TSCK2SD {Max}
WS
SD
TSU
Data Valid
THD
TSCK2SD {Min}
Data Valid
Data Valid
2
Figure 4.11. I S Output Timing
TSPCYC
T SPDUTY
50%
SPDIF
Figure 4.12. S/PDIF Output Timing
TMCLKCYC
MCLK
50%
50%
TMCLKDUTY
Figure 4.13. MCLK Timing
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
29
SiI9573 and SiI9575 Port Processor
Data Sheet
TCHSH
SS
TSLCH
SCLK
TDVCH
TCHDX
SDI
SS and SDI Timing
SS
TSCLKH
SCLK
TCLQV
TSCLKL
SDO
SDO Timing
Figure 4.14. SPI Flash Memory Timing
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
5. Pin Diagram and Pin Descriptions
5.1. Pin Diagram
SD0_IN/SPDIF0_IN
SCK1_IN/SCK1_OUT
WS1_IN/WS1_OUT
SD1_IN/SD1_OUT/SPDIF1_IN/SPDIF1_OUT
ARC0
ARC1
CVCC13
TPVDD13
TDVDD13
T1XC–
T1XC+
T1X0–
T1X0+
T1X1–
T1X1+
T1X2–
T1X2+
TPVDD13
TDVDD13
T0XC–
T0XC+
T0X0–
T0X0+
T0X1–
T0X1+
T0X2–
T0X2+
CVCC13
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
IDCK
IOVCC33
D11
D12
D13
Figure 5.1 shows the pin assignments of the SiI957n port processor. Individual pin functions are described in the Pin
Descriptions section on the next page. The package is a 20 × 20 × 0.4 mm 176-pin TQFP with an ePad, which must be
connected to ground.
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 96
D14
1
132
SCK0_IN/GPIO10
D15
2
131
WS0_IN/GPIO11
D16
3
130
SPDIF0_OUT/DL2
D17
4
129
MUTEOUT/GPIO9
D18
5
128
SD0_3/DR2/GPIO8
D19
6
127
SD0_2/DL1/GPIO7
DE
7
126
SD0_1/DR1/GPIO6
VSYNC
8
125
MCLK
HSYNC
9
124
SD0_0/DL0
R0XC–
10
123
IOVCC33
R0XC+
11
122
SCK0/DDCK
R0X0–
12
121
WS0_OUT/DR0
R0X0+
13
120
SDI/GPIO5
R0X1–
14
119
SDO/GPIO4
R0X1+
15
118
SCLK/GPIO3
R0X2–
16
117
SS/GPIO2
R0X2+
17
116
CVCC13
AVDD13
18
115
XTALGND
AVDD33
19
114
XTALIN
R1XC–
20
113
XTALOUT
R1XC+
21
112
XTALVCC33
R1X0–
22
111
APLL13
R1X0+
23
110
TXDSCL1
R1X1–
24
109
TXDSDA1
R1X1+
25
108
TX_HPD1
R1X2–
26
107
TXDSCL0
R1X2+
27
106
TXDSDA0
R2XC–
28
105
TX_HPD0
R2XC+
29
104
MHL_CD1/GPIO1
R2X0–
30
103
MHL_CD0/GPIO0
R2X0+
31
102
VCC33OUT
R2X1–
32
101
SBVCC5
R2X1+
33
100
R5PWR5V
R2X2–
34
99
CBUS_HPD5
R2X2+
35
98
DSCL5
AVDD13
36
97
DSDA5
CVCC13
37
96
RSVDL
AVDD33
38
95
R4PWR5V
R3XC–
39
94
CBUS_HPD4
R3XC+
40
93
DSCL4
R3X0–
41
92
DSDA4
R3X0+
42
91
R3PWR5V
R3X1–
43
90
CBUS_HPD3
R3X1+
44
89
DSCL3
SiI957n
Top View
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
R3X2–
R4XC–
R4XC+
R4X0–
R4X0+
R4X1–
R4X1+
R4X2–
R4X2+
AVDD13
AVDD33
R5XC–
R5XC+
R5X0–
R5X0+
R5X1–
R5X1+
R5X2–
R5X2+
CVCC13
CSCL
CSDA
INT
RESET#
TPWR_CI2CA
CEC_A1
CEC_A0
DSDA6(VGA)
DSCL6(VGA)
75
76
77
78
79
80
81
82
83
84
85
86
87
88
DSDA3
57
R2PWR5V
56
DSCL2
55
CBUS_HPD2
54
DSDA2
53
R1PWR5V
52
CBUS_HPD1
51
DSCL1
50
DSDA1
49
R0PWR5V
48
CBUS_HPD0
47
DSCL0
46
RSVDL
DSDA0
45
R3X2+
ePad (GND)
Figure 5.1. Pin Diagram (Top View)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
31
SiI9573 and SiI9575 Port Processor
Data Sheet
5.2. Pin Descriptions
5.2.1. HDMI Receiver and MHL Port Pins
Name
R0X0+
Pin
13
Type
TMDS
Dir
Input
Description
HDMI Receiver Port 0 TMDS Input Data Pairs.
R0X0–
R0X1+
12
15
R0X1–
R0X2+
14
17
R0X2–
R0XC+
R0XC–
16
11
10
TMDS
Input
HDMI Receiver Port 0 TMDS Input Clock Pair.
R1X0+
R1X0–
23
22
TMDS
Input
HDMI Receiver Port 1TMDS Input Data Pairs.
R1X1+
R1X1–
R1X2+
25
24
27
R1X2–
R1XC+
26
21
R1XC–
R2X0+
R2X0–
20
31
30
TMDS
Input
HDMI Receiver Port 1 TMDS Input Clock Pair.
TMDS
Input
HDMI Receiver Port 2 TMDS Input Data Pairs.
R2X1+
R2X1–
33
32
R2X2+
R2X2–
R2XC+
35
34
29
R2XC–
28
TMDS
Input
HDMI Receiver Port 2 TMDS Input Clock Pair.
R3X0+
R3X0–
42
41
TMDS
Input
HDMI Receiver Port 3 TMDS Input Data Pairs.
R3X1+
R3X1–
R3X2+
44
43
46
R3X2–
R3XC+
45
40
TMDS
Input
HDMI Receiver Port 3 TMDS Input Clock Pair.
R3XC–
R4X0+
39
50
TMDS
Input
HDMI Receiver Port 4 TMDS Input Data Pairs.
R4X0–
R4X1+
R4X1–
49
52
51
R4X2+
R4X2–
54
53
R4XC+
48
TMDS
Input
HDMI Receiver Port 4 TMDS Input Clock Pair.
R4XC–
47
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
5.2.2. HDMI Receiver and MHL Port Pins (continued)
Name
R5X0+
R5X0–
Pin
60
59
R5X1+
R5X1–
62
61
R5X2+
R5X2–
R5XC+
64
63
58
Type
TMDS
Dir
Input
Description
HDMI Receiver Port 5 TMDS Input Data Pairs.
TMDS
Input
HDMI Receiver Port 5 TMDS Input Clock Pair.
R5XC–
57
Note: For Port n and Port m that have been configured as MHL inputs, the RnX0+ and RnX0– pin pair and RmX0+ and RmX0– pin pair
carry the respective MHL signals.
5.2.3. HDMI Transmitter Port Pins
Name
T0X0+
Pin
155
T0X0–
154
T0X1+
157
T0X1–
156
T0X2+
159
T0X2–
158
T0XC+
153
T0XC–
152
T1X0+
145
T1X0–
144
T1X1+
147
T1X1–
146
T1X2+
149
T1X2–
148
T1XC+
143
T1XC–
142
Type
TMDS
Dir
Output
Description
HDMI Transmitter Port 0 TMDS Output Data Pairs.
Main HDMI transmitter output port TMDS data pairs.
TMDS
Output
HDMI Transmitter Port 0 TMDS Output Clock Pair.
Main HDMI transmitter output port TMDS clock pair.
TMDS
Output
HDMI Transmitter Port 1 TMDS Output Data Pairs.
Sub-HDMI transmitter output port TMDS data pairs.
TMDS
Output
HDMI Transmitter Port 1 TMDS Output Clock Pair.
Sub-HDMI transmitter output port TMDS clock pair.
5.2.4. Audio Return Channel Pins
Name
ARC0
Pin
137
ARC1
138
Type
Analog
Dir
Input/
Output
Description
Audio Return Channels 0 and 1.
These pins are used to transmit or receive an IEC60958-1 audio stream. In ARC
transmitter mode, received on the SPDIFn_IN input pin, this pin transmits an
S/PDIF signal to an ARC receiver-capable source (such as HTiB) or a repeater
(such as AVR) devices, using single-mode ARC.
In ARC receiver mode, transmitted through the SPDIFn_OUT pin, this pin
receives an S/PDIF signal from an ARC transmitter-capable sink (such as DTV)
device, using single-mode ARC. In combination with external components,
common-mode ARC can be received.
Each channel can either be an ARC input or an ARC output at one time.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
33
SiI9573 and SiI9575 Port Processor
Data Sheet
5.2.5. Audio Pins
Name
MCLK
SCK0/
DDCK
WS0_OUT/
DR0
SD0_0/
DL0
SD0_1/DR1/
GPIO6
SD0_2/DL1/
GPIO7
SD0_3/DR2/
GPIO8
SPDIF0_OUT/
DL2
Pin
125
122
Type
LVTTL
LVTTL
Dir
Output
Output
Description
Master Clock Output
2
Main Port I S Serial Clock Output/DSD Clock Output.
121
LVTTL
Output
Main Port I S Word Select Output/DSD Data Right Bit 0.
124
LVTTL
Output
Main Port I S Serial Data 0 Output/DSD Data Left Bit 0 Output.
126
LVTTL
Output
127
LVTTL
Output
128
LVTTL
Output
Main Port I S Serial Data 1 Output/DSD Data Right Bit 1 Output/
Programmable GPIO 6.
2
Main Port I S Serial Data 2 Output/DSD Data Left Bit 1 Output/ Programmable
GPIO 7.
2
Main Port I S Serial Data 3 Output/DSD Data Right Bit 2/ Programmable GPIO
8.
130
Output
Main Port S/PDIF Output/DSD Data Left Bit 2.
SCK0_IN/
GPIO10
132
Analog/
LVTTL
LVTTL
Input/
Output
Main Port I S Serial Clock Input/Programmable GPIO 10.
WS0_IN/
GPIO11
131
LVTTL
Main Port I S Word Select Input/Programmable GPIO 11.
SD0_IN/
SPDIF0_IN
133
SCK1_IN/
SCK1_OUT
134
Analog/
LVTTL
LVTTL
Input/
Output
Input
Input/
Output
Subport I S Serial Clock1 Input/I S Serial bit Clock Output.
WS1_IN/
WS1_OUT
135
LVTTL
Subport I S Word Select Input/I S Word Select Output.
SD1_IN/
SD1_OUT/
SPDIF1_IN/
SPDIF1_OUT
MUTEOUT/
GPIO9
136
LVTTL
Input/
Output
Input/
Output
129
LVTTL
Input/
Output
Mute Audio Output/Programmable GPIO 9.
Dir
Output
Description
Crystal clock output.
2
2
2
2
2
2
Main Port I S Serial Data Input/S/PDIF Input.
2
2
2
2
2
2
Subport I S Serial Data Input/I S Serial Data1 Output/ SPDIF Input//SPDIF
Output.
5.2.6. Crystal Pins
Name
XTALOUT
Pin
113
XTALIN
114
Type
LVTTL
5 V tolerant
LVTTL
5 V tolerant
Input
Crystal clock input.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
5.2.7. SPI Interface Pins
Name
SS/
GPIO2
Pin
117
Type
LVTTL
Dir
Input/
Output
Description
SPI Slave Select/Programmable GPIO 2.
SCLK/
GPIO3
118
LVTTL
Schmitt
Open-drain\
Input/
Output
SPI Clock/Programmable GPIO 3.
SDO/
GPIO4
119
LVTTL
Schmitt
Open-drain
Input/
Output
SPI Slave Data Output/Master Data Input/Programmable GPIO 4.
SDI/
GPIO5
120
LVTTL
Schmitt
Open-drain
Input/
Output
SPI Slave Data Input/Master Data Output/Programmable GPIO 5.
5.2.8. Parallel Video Bus
Name
D0
Pin
161
Type
LVTTL
Dir
Input
Description
Video Data Inputs.
The video data inputs can be configured to support a wide variety of input
formats, including multiple RGB and YCbCr bus formats, using register
settings.
D1
162
D2
163
D3
164
D4
165
D5
166
D6
167
D7
168
D8
169
D9
170
D10
171
D11
174
D12
175
D13
176
D14
1
D15
2
D16
3
D17
4
D18
5
D19
6
DE
7
LVTTL
Input
Data Enable Input
HSYNC
9
LVTTL
Input
Horizontal Sync Input
VSYNC
8
LVTTL
Input
Vertical Sync Input
IDCK
172
LVTTL
Input
Input Data Clock
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
35
SiI9573 and SiI9575 Port Processor
Data Sheet
5.2.9. DDC I2C Pins
Name
DSDA0
Pin
76
Type
LVTTL
Schmitt
Open-drain
5 V tolerant
Dir
Input/
Output
Description
2
DDC I C Data for respective HDMI receiver port.
These signals are true open drain, and do not pull to ground when power is
not applied to the device. These pins require an external pull-up resistor.
DSDA1
DSDA2
DSDA3
80
84
88
DSDA4
DSDA5
92
97
DSDA6(VGA)
73
LVTTL
Schmitt
Open-drain
5 V tolerant
Input/
Output
DDC I C data for VGA port.
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
DSCL0
77
Input
DSCL1
81
DSCL2
85
DDC I C Clock for respective HDMI receiver port.
These signals are true open drain, and do not pull to ground when power is
not applied to the device. These pins require an external pull-up resistor.
DSCL3
DSCL4
89
93
LVTTL
Schmitt
Open-drain
5 V tolerant
DSCL5
DSCL6(VGA)
98
74
Input
DDC I C Clock for VGA port.
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
TXDSDA0
106
Input/
Output
DDC Master I C Data for HDMI transmitter Port 0.
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
TXDSDA1
109
Input/
Output
DDC Master I C Data for HDMI transmitter Port 1.
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
TXDSCL0
107
Input/
Output
DDC Master I C Clock for HDMI transmitter Port 0.
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
TXDSCL1
110
LVTTL
Schmitt
Open-drain
5 V tolerant
LVTTL
Schmitt
Open-drain
5 V tolerant
LVTTL
Schmitt
Open-drain
5 V tolerant
LVTTL
Schmitt
Open-drain
5 V tolerant
LVTTL
Schmitt
Open-drain
5 V tolerant
Input/
Output
DDC Master I C Clock for HDMI transmitter Port 1
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
2
2
2
2
2
2
2
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
5.2.10. Control Pins
Name
CSCL
Pin
66
Type
Schmitt
Open-drain
5 V tolerant
Dir
Input
Description
2
Local Configuration/Status I C Clock.
2
Chip configuration/status is accessed via this I C port. This pin is true open
drain, so it does not pull to ground if power is not applied. See Figure 2.2 on
page 10.
CSDA
67
Input/
Output
Local Configuration/Status I C Data.
2
Chip configuration/status is accessed via this I C port. This pin is true open
drain, so it does not pull to ground if power is not applied. See Figure 2.2 on
page 10.
RESET#
69
LVTTL
Schmitt
Open-drain
5 V tolerant
Schmitt
2
Input
External reset.
Active LOW. Must be pulled up to VCC33OUT. When main power is not
provided to the system, the microcontroller must present a high impedance of
at least 100 kΩ to RESET#. If this condition is not met, a circuit to block the
leakage from VCC33OUT to the microcontroller GPIO may be required.
Type
Power
Dir
Input
Description
5 V Port detection input for respective HDMI receiver port.
Connect to 5 V signal from HDMI input connector. These pins require a 10 Ω
series resistor, a 5.1 kΩ pull down resistor, and at least a 1 µF capacitor to
ground.
LVTTL
1.5 mA
5 V tolerant
Analog
Input/
Output
Input
Hot Plug Detect Input for HDMI transmitter Port 0.
Input
Hot Plug Detect Input for HDMI transmitter Port 1.
5.2.11. System Switching Pins
Name
R0PWR5V
R1PWR5V
Pin
79
83
R2PWR5V
87
R3PWR5V
R4PWR5V
91
95
R5PWR5V
100
CBUS_HPD0
78
CBUS_HPD1
82
CBUS_HPD2
86
CBUS_HPD3
90
CBUS_HPD4
94
CBUS_HPD5
99
TX_HPD0
105
TX_HPD1
108
MHL_CD0/
GPIO0
103
LVTTL
5 V tolerant
LVTTL
5 V tolerant
LVTTL
MHL_CD1/
GPIO1
104
LVTTL
Hot Plug Detect output for the respective HDMI receiver port.
In MHL mode, these pins serve as the respective CTRL bus.
Input/
Output
MHL Cable Detect 0/Programmable GPIO 0.
MHL_CD0 is 5 V tolerant if SBVCC5 or one of the R[0-5]PWR5V is applied to
the device. If none of these power supplies are applied, then MHL_CD0 is 3.3
V tolerant.
Input/
Output
MHL Cable Detect 1/Programmable GPIO 1.
MHL_CD1 is 5 V tolerant if SBVCC5 or one of the R[0-5]PWR5V is applied to
the device. If none of these power supplies are applied, then MHL_CD1 is 3.3
V tolerant.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
37
SiI9573 and SiI9575 Port Processor
Data Sheet
5.2.12. Configuration Pins
Name
TPWR_CI2CA
Pin
70
Type
LVTTL
Dir
Input/
Output
Description
2
I C Slave Address Input/Transmit Power Sense Output.
2
During power-on-reset (POR), this pin is used as an input to latch the I C subaddress. The level on this pin is latched when the POR transitions from the
asserted state to the de-asserted state.
After completion of POR, this pin is used as the TPWR output. A register
setting can change this pin to show if the active port is receiving a TMDS clock.
INT
68
Schmitt
Open-drain
8 mA
3.3 V tolerant
Output
Interrupt Output.
This is an open-drain output and requires an external pull-up resistor. This
output can be safely pulled up to 3.3 V with no power (no SBVCC5,
no R[0-5]PWR5V, no 3.3 V, and no 1.3 V) applied to the device.
5.2.13. CEC Pins
Name
CEC_A0
Pin
72
Type
CEC
Compliant
5 V tolerant,
Schmitt
triggered,
LVTTL
Dir
Input/
Output
Description
Primary CEC I/O used for interfacing to CEC devices This signal is electrically
compliant with the CEC specification.
As an input, this pin acts as an LVTTL Schmitt triggered input and is 5 V
tolerant. As an output, the pin acts as an NMOS driver with resistive pull-up.
This pin has an internal pull-up resistor.
This signal should be connected to the CEC signal of all HDMI input and output
ports if the system supports just one CEC line.
OR
In a system designed to have separate CEC connectivity for the HDMI input
and output ports, this signal should be connected to the CEC signal of all the
input ports supported in the system.
This signal and CEC_A0 each connect to a separate CEC controller within the
port processor and are independent of each other.
CEC_A1
71
CEC
Compliant
5 V tolerant,
Schmitt
triggered,
LVTTL
Input/
Output
Secondary CEC I/O used for interfacing to CEC devices.
This signal is electrically compliant with the CEC specification. As an input, this
pin acts as an LVTTL Schmitt triggered input and is 5 V tolerant. As an output,
the pin acts as an NMOS driver with resistive pull-up. This pin has an internal
pull-up resistor.
This is an optional CEC signal provided for system designers who want to
implement a system with two independent CEC lines, such as a system that
supports a separate CEC line for the HDMI input ports and the HDMI output
ports. In the example of a DTV that provides a second HDMI output using the
SiI957n port processor; this signal can be connected to the CEC signal of the
output port while the CEC_A1 signal is connected to the CEC signal of the
input ports.
This signal and CEC_A1 each connect to a separate CEC controller within the
port processor and are independent of each other.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
5.2.14. Power and Ground Pins
Name
AVDD33
Pin
19, 38, 56
Type
Power
Description
TMDS Core VDD.
AVDD33 should be isolated from other system supplies to
prevent leakage from the source device through the TMDS
input pins. AVDD33 should not be used to power other system
components that can be adversely affected by such leakage.
Supply
3.3 V
IOVCC33
123, 173
Power
I/O VCC.
3.3 V
SBVCC5
101
Power
Local Power from system.
This pin requires a 10 Ω series resistor.
5.0 V
AVDD13
18, 36, 55
Power
TMDS Receiver Core VDD.
1.3 V
CVCC13
37, 65, 116, 139, 160
Power
Digital Core VCC.
1.3 V
APLL13
111
Power
PLL Analog VCC.
1.3 V
VCC33OUT
102
Power
Internal regulator 3.3 V output.
VCC33OUT should not be used as a power source to provide
power to other external circuits
3.3 V
TPVDD13
140, 150
Power
Analog Power for TMDS Tx core.
1.3 V
TDVDD13
141, 151
Power
Digital Power for TMDS Tx core.
1.3 V
XTALVCC33
112
Power
PLL crystal oscillator power.
3.3 V
XTALGND
115
Ground
PLL crystal oscillator ground.
GND
GND
ePad
Ground
The ePad must be soldered to ground, as this is the only
ground connection for the device.
GND
5.2.15. Reserved Pin
Name
RSVDL
RSVDL
Pin
75
96
Type
Reserved
Reserved
Description
Reserved, must be tied to ground.
Reserved, must be tied to ground through a 4.7 kΩ pull-down resistor.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
39
SiI9573 and SiI9575 Port Processor
Data Sheet
6. Feature Information
6.1. Standby and HDMI Port Power Supplies
The port processor has a 5-volt standby power supply pin (SBVCC5V) that can be used to supply power to the EDID and
CEC portions of the device when all other power supplies are turned off. This arrangement results in a low-power mode,
but allows the EDID to be readable and the CEC controllers to be operational. Table 6.1 summarizes the power modes
available in the SiI957n port processor. Figure 6.1 shows a block diagram of the standby power supply sources and the
always-on power island.
Table 6.1. Description of Power Modes
Power Mode
Power-on Mode
Standby Power mode
HDMI Port-only Power
Description
All power supplies to the SiI957n chip are on. All
functions are available. The standby power
supply is 5 V.
The always-on power domain is on, supplied
from the internal power MUX; all other supplies
are off. The standby power supply is 5 V. In this
mode, EDID and CEC are functional, but video
and audio processing is not performed and all
outputs are off.
Power is off to the device. HDMI +5 V from the
HDMI cable is the only power source. For
example, if the TV is unplugged from AC wall
outlet, the EDID and CEC are functional in this
mode.
SBVCC5
5V
RnPWR5V
NA
AVDD33
3.3 V
AVDD13
1.3 V
5V
NA
Off
Off
Off
5 V on
any
input
Off
Off
Note: All other supplies are on in the power-on mode and off in all other modes.
AVDD33
AVDD13
CVCC13
TDVDD13
TPVDD13
HDMI
Connectors
n = 0 to 5
RnPWR5V
ARC
SBVCC5
ARC Block
Power
Multiplexer
EDID
RAM
CEC
Always-on
Power Island
Video and
Audio
Processing
Blocks
SiI957n
Port Processor
Figure 6.1. Standby Power Supply Diagram
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
If all power is off to the device, such as if the AVR or TV is unplugged from the AC electrical outlet, the EDID can still be
read from the source by using power from the HDMI connector +5 V signal. In this case, the internal power MUX
automatically switches to the HDMI connector power for powering the always-on logic. In this mode, only the EDID and
CEC blocks are functional; all other functions of the device are in power-off mode. No damage will occur to the device
in this mode.
6.2. InstaPort
The SiI957n port processor supports the InstaPort™ HDCP preauthentication feature, which hides the HDCP
authentication time from the user. HDCP authentication is started on an upstream (input) port immediately after a
source device is connected, regardless of whether the port is currently selected for output to the downstream sink
device. All nonselected ports are HDCP authenticated in this manner and when HDCP is authenticated, it is maintained
in the background. When a nonselected port is then selected, the authenticated content is immediately available
because it does not have to reauthenticate HDCP. This InstaPort HDCP preauthentication feature reduces port switching
times to less than one second.
6.3. InstaPrevue
The SiI957n device incorporates the InstaPrevue feature, which provides periodically updated picture-in-picture
previews of each connected source device. The contents of each preauthenticated TMDS source device not being
viewed can be displayed as a small subwindow overlaid onto the main video currently being viewed. With this feature,
DTV and AVR manufacturers can provide the end-user with a content based, rather than a text based user interface for
changing or selecting among various Blu-ray disc players, set-top boxes, DVD players, game consoles, or other
HDMI/DVI/MHL connected sources.
InstaPrevue operates in one of three modes:

The All Preview mode displays one to five sub-windows, selected by the user, regardless of whether a source device
is connected or not. A subwindow with a manufacturer defined color is displayed for an unconnected source device.

The Active mode displays only the subwindows for which there is a connected, active, and authenticated source
device.

The Selected mode displays a single subwindow for a connected source device selected by the user and is intended
as a Picture-In-Picture (PIP) type preview.
InstaPrevue can be displayed on both Tx0 and Tx1 outputs of the SiI957n device. On the SiI9575 device, InstaPrevue
does not operate in ViaPort Matrix Switch mode.
The supported combinations of main video display and InstaPrevue window formats are shown in the following table.
InstaPrevue is compatible with RGB, YC4:4:4, and YC4:2:2 color formats.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
41
SiI9573 and SiI9575 Port Processor
Data Sheet
Table 6.2. Supported InstaPrevue Window Formats
Main Video Display Format
All supported 2D Resolutions
720p and 1080p 3D Frame Packing
InstaPrevue Window Format
Supported?
All supported 2D Resolutions except 4K×2K
Yes
720p and 1080p 3D Frame Packing
Yes
480p and 1080i 3D Frame Packing
No
3D Side-by-Side (Half)
No
3D Side-by-Side (Full)
No
3D Top & Bottom
No
All supported 2D Resolutions except 4K×2K
Yes
720p and 1080p 3D Frame Packing
Yes
480p and 1080i 3D Frame Packing
No
3D Side-by-Side (Half)
No
3D Top & Bottom
No
All Formats
No
All Formats
No
480p and 1080i 3D Frame Packing
3D Top & Bottom
3D Side-by-Side (Half)
3D Side-by-Side (Full)
4K×2K
6.4. Support for UltraHD resolution at 50P/60P frames per second
The SiI957n device support 4K × 2K 50P and 4K × 2K 60p frame per second when pixel format is YCbCr 4:2:0 with TMDS
clock frequency of 300 MHz. When configuring this mode, On-screen Display (OSD) and InstaPrevue must be disabled
by the Firmware.
6.5. ViaPort Matrix Switch
The ViaPort Matrix Switch feature is available only on the SiI9575 device. When enabled, a different input source is sent
to each of the two HDMI transmitter ports. The available input sources for the ViaPort Matrix Switch are any one of six
TMDS input ports, an external parallel video input port, and an internal video pattern generator. This feature allows the
system designer to implement a two zone system in an AVR or similar device.
6.6. MHL Receiver
The SiI957n port processor supports the Mobile High-definition Link (MHL) as a sink device on two of the six RX receiver
ports selected at the time of manufacture. MHL is a high-speed multimedia data transfer protocol intended for use
between mobile and display devices. The SiI957n device supports HDMI and MHL modes on the two selected RX
receiver ports simultaneously. When an HDMI source is connected, the receiver port is configured as an HDMI port.
When an MHL source is connected, an MHL cable detect sense signal from the cable is asserted and sent to the SiI957n
device and also to the host microcontroller as an interrupt to configure the receiver port as an MHL port and to initiate
the CBUS discovery process.
MHL carries video, audio, auxiliary, control data, and power across a cable consisting of five conductors. One connection
is for a dedicated ground which is used as the 0V reference for the signals on the remaining four connections. Two other
conductors form a single channel TMDS differential signal pair used to send video, audio and auxiliary data from the
source device to the sink device. On the SiI957n device, the MHL TMDS channel differential signal pair pins are shared
with the RX0+ and RX0– pins of the HDMI TMDS channel differential signal pair. Another connection is for the MHL
Control Bus (CBUS). The CBUS carries control information that provides configuration and status exchanges between the
source and the sink devices. CBUS is a software/hardware protocol that supports four types of packet transfers: Display
Data Control (DDC), Vendor Specific, MHL Sideband Channel (MSC), and a reserved type. EDID data can be transferred
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
between the source and sink devices using the CBUS. On the SiI957n device, the CBUS signal pin is shared with the HPD
signal pin. Another connection is used as the VBUS which provides +5V power to charge the connected MHL source
device. An external power switch is typically used on the system board to supply the +5 V power to the VBUS. Enabling
the switch provides the +5 V power on the VBUS when the MHL source is connected and the MHL cable detect signal is
asserted.
6.7. 3D Video Formats on Main Display
The SiI957n port processor supports the pass-through of 3D video modes described in the HDMI 1.4a Specification. All
modes support RGB 4:4:4, YCbCr 4:4:4, and YCbCr 4:2:2 color formats and 8-, 10-, and 12-bit data-width per color
component. Table 6.3 shows only the maximum possible resolution with a given frame rate; for example, Side-by-Side
(Half) mode is defined for 1080p @ 60 Hz, which implies that 720p, 60 Hz and 480p @ 60 Hz are also supported.
Furthermore, a frame rate of 24 Hz also means that a frame rate of 23.98 Hz is supported and a frame rate of 60 Hz also
means a frame rate of 59.94 Hz is supported. The input pixel clock changes accordingly.
The SiI957n device supports pass-through of the HDMI Vendor Specific InfoFrame, which carries 3D information to the
receiver. It also supports extraction of the HDMI Vendor Specific InfoFrame, which allows the 3D information contained
2
in the InfoFrame to be passed to the host system over the I C port.
Table 6.3. Supported 3D Video Formats
3D Format
Extended Definition
Frame Packing
—
Side-by-Side
Full
Line Alternative
—
L + Depth
—
Frame Packing
—
Side-by-Side
Full
Half
Top & Bottom
—
Resolution
Frame Rate (Hz)
Input Pixel Clock (MHz)
1080p
50/60
297
1080p
24/30
720p/1080i
50/60
1080p
24/30
720p/1080i
50/60
1080p
50/60
1080p
50/60
1080p
24/30
720p/1080i
50/60
1080p
24/30
720p/1080i
50/60
—
1080i
50/60
—
1080p
24/30
Line Alternative
—
Field Alternative
L + Depth
148.5
74.25
148.5
6.8. VS Insertion
The SiI957n device features logic that can be used to assist the downstream SoC in processing 3D video for display. It
can monitor the 3D video stream and insert a VS pulse in the VS signal during the Active space period for demarcating
the L and R video frames. Figure 6.2 on the next page shows the VS insertion mode. The front porch, pulse width, back
porch, and polarity of the inserted VS signal can be individually set.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
43
SiI9573 and SiI9575 Port Processor
Data Sheet
Original 3D Stream
HS
VS
Vact_video
Vact_space
Vact_video
Modified 3D Stream
HS
VS
Vact_video
Vfront
Vsync
Vback
Vact_video
Figure 6.2. VS Insertion in Active Space
6.9. 3D L/R and Active Space Indicators Output on GPIO Pins
The SiI957n device can also monitor the 3D video stream and output L, R and Active Space indicators on GPIO pins for
2
both the main pipe and the subpipe. The main pipe GPIO pins are shared with the main pipe I S audio extraction pins
and the subpipe GPIO pins are shared with the SPI interface pins as shown in Table 6.4.
Table 6.4. L/R and Active Space Indicator Mapping to GPIO Pins
Pin
118
119
Name
SCLK/GPIO3
SDO/GPIO4
Primary Function
SPI SCLK
SPI SDO
Secondary Function
SP_3D_R_FLAG
SP_3D_V_FLAG
120
126
SDI/GPIO5
SD0_1/DR1/GPIO6
SPI SDI
2
Audio Out I S/DSD
SP_3D_L_FLAG
MP_3D_R_FLAG
127
128
SD0_2/DL1/GPIO7
SD0_3/DR2/GPIO8
Audio Out I S/DSD
2
Audio Out I S/DSD
2
MP_3D_V_FLAG
MP_3D_L_FLAG
2
The main pipe I S audio extraction must be disabled when the main pipe 3D indicators are output on the respective
GPIO pins. The SPI interface to the external Flash memory cannot be used when the subpipe 3D indicators are output
on the respective GPIO pins. Figure 6.3 shows the 3D L, R and Active Space indicators output on the respective GPIO
pins. 3D indicators are supported only for 720p frame-packed, and 1080p frame-packed video modes.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
SiI-DS-1089-F
GPIO6/GPIO3
GPIO8/GPIO5
H
GPIO7/GPIO4
SiI9573 and SiI9575 Port Processor
Data Sheet
Active video
Delay
L
V
Active space
Delay
Active video
Delay
Single register
controls delay for
all three markers
R
3D Frame Packing Video
Figure 6.3. L/R and Active Space Indicators Output on GPIO Pins
6.10.Parallel Video Input Data Bus Mapping
6.10.1. Common Video Input Formats
Table 6.5. Video Input Formats
4:4:4
Bus
Width/
4
SYNC
5 VGA/
Color
480i
576i
480p
Depth
1x, dual 12/8
Sep
27 25/27 27
27
65
74.25 74.25
—
—
—
1
46
4:4:4
1x, dual
12/8
Sep
27 25/27
27
27
65
74.25 74.25
—
—
—
1
46
1x, single
16/8
20/10
Sep
27 25/27
27
27
65
74.25 74.25
108
148.5
162
2
48
Emb
27 25/27
27
27
65
74.25 74.25
108
148.5
162
2, 3
49
Sep
—
50/54
54
54
130
148.5 148.5
—
—
—
2
52
Emb
—
50/54
54
54
130
148.5 148.5
—
—
—
2, 3
56
Sep
27 25/27
27
27
65
74.25 74.25
108
148.5
162
1
—
Emb
27 25/27
27
27
65
74.25 74.25
108
148.5
162
1, 3
—
Color Video
Space Format
RGB
YCbCr
4:2:2
Clock
Mode
8/8
2x, single/
10/10
YC Mux
12/12
8/8
1x, dual/
10/10
YC Mux
12/12
Input Clock (MHz)
576p
XGA
720p
1080i SXGA 1080p UXGA
Notes Page
Notes:
1. Falling or rising edge latched first is programmable.
2. Latching on falling or rising edge is programmable.
3. If embedded syncs are provided, DE is generated internally from SAV/EAV sequences. Embedded syncs use
ITU-R BT 656 SAV/EAV sequences of FF, 00, 00, XY.
4. Sep = separate sync; Emb = embedded sync.
5. 480i must be provided at 27 MHz, using pixel replication, to be transmitted across the HDMI link.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
45
SiI9573 and SiI9575 Port Processor
Data Sheet
6.10.2. RGB and YCbCr 4:4:4 Formats Dual Clock Edge
The input clock runs at the pixel rate and a complete definition of each pixel is received on each input clock cycle. One
clock edge latches in half the pixel data. The opposite clock edge latches in the remaining half of the pixel data on the
same pins. The same timing format is used for RGB and YCbCr 4:4:4. Each pair of columns in Table 6.6 shows the first
pixel of n + 1 pixels in the line of video. The figures below the table show RGB and YCbCr data; the YCbCr 4:4:4 data is
given in braces {}. Data and control signals (Dx, DE, HSYNC, and VSYNC) must change state to meet the setup and hold
times specified for the dual edge mode, with respect to the first edge of IDCK as defined by the setting of the Edge
Select bit (see the Programmer’s Reference). The figures show IDCK latching input data when the Edge Select bit is set
to 1 (first edge is the rising edge).
Table 6.6. RGB/YCbCr 4:4:4 Separate Sync Dual Clock Edge Data Mapping
Video Bus
Setting
YCSWAP
DRA
Pin Name
D0
D1
D2
12-bit Data Bus
8-bit Color Depth
N/A
0
RGB
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
LOW
LOW
LOW
LOW
12-bit Data Bus
8-bit Color Depth
N/A
1
RGB
1st Clock
2nd Clock
Edge
Edge
B0[0]
G0[4]
B0[1]
G0[5]
B0[2]
G0[6]
12-bit Data Bus
8-bit Color Depth
N/A
0
YCbCr
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
LOW
LOW
LOW
LOW
12-bit Data Bus
8-bit Color Depth
N/A
1
YCbCr
1st Clock
2nd Clock
Edge
Edge
Cb0[0]
Y0[4]
Cb0[1]
Y0[5]
Cb0[2]
Y0[6]
D3
D4
LOW
LOW
LOW
LOW
B0[3]
B0[4]
G0[7]
R0[0]
LOW
LOW
LOW
LOW
Cb0[3]
Cb0[4]
Y0[7]
Cr0[0]
D5
D6
D7
LOW
LOW
LOW
LOW
LOW
LOW
B0[5]
B0[6]
B0[7]
R0[1]
R0[2]
R0[3]
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[5]
Cb0[6]
Cb0[7]
Cr0[1]
Cr0[2]
Cr0[3]
D8
D9
B0[0]
B0[1]
G0[4]
G0[5]
G0[0]
G0[1]
R0[4]
R0[5]
Cb0[0]
Cb0[1]
Y0[4]
Y0[5]
Y0[0]
Y0[1]
Cr0[4]
Cr0[5]
D10
D11
D12
B0[2]
B0[3]
B0[4]
G0[6]
G0[7]
R0[0]
G0[2]
G0[3]
LOW
R0[6]
R0[7]
LOW
Cb0[2]
Cb0[3]
Cb0[4]
Y0[6]
Y0[7]
Cr0[0]
Y0[2]
Y0[3]
LOW
Cr0[6]
Cr0[7]
LOW
D13
D14
B0[5]
B0[6]
R0[1]
R0[2]
LOW
LOW
LOW
LOW
Cb0[5]
Cb0[6]
Cr0[1]
Cr0[2]
LOW
LOW
LOW
LOW
D15
D16
D17
B0[7]
G0[0]
G0[1]
R0[3]
R0[4]
R0[5]
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[7]
Y0[0]
Y0[1]
Cr0[3]
Cr0[4]
Cr0[5]
LOW
LOW
LOW
LOW
LOW
LOW
D18
D19
G0[2]
G0[3]
R0[6]
R0[7]
LOW
LOW
LOW
LOW
Y0[2]
Y0[3]
Cr0[6]
Cr0[7]
LOW
LOW
LOW
LOW
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
blank
Pixel 0
Pixel 1
Pixel 2
Pixel n - 1
D[19:16]
val
G0[3:0]
{Y0[3:0]}
R0[7:4]
{Cr0[7:4]}
G1[3:0]
{Y1[3:0]}
R1[7:4]
{Cr1[7:4]}
G2[3:0]
{Y2[3:0]}
R2[7:4]
{Cr2[7:4]}
Gn-1[3:0]
{Yn-1[3:0]}
Rn-1[7:4]
{Crn-1[7:4]}
D[15:12]
val
B0[7:4]
{Cb0[7:4]}
R0[3:0]
{Cr0[3:0]}
B1[7:4]
{Cb1[7:4]}
R1[3:0]
{Cr1[3:0]}
B2[7:4]
{Cb2[7:4]}
R2[3:0]
{Cr2[3:0]}
Bn-1[7:4]
{Cbn-1[7:4]}
D[11:8]
val
B0[3:0]
{Cb0[3:0]}
G0[7:4]
{Y0[7:4]}
B1[3:0]
{Cb1[3:0]}
G1[7:4]
{Y1[7:4]}
B2[3:0]
{Cb2[3:0]}
G2[7:4]
{Y2[7:4]}
Bn-1[3:0]
{Cbn-1[3:0]}
blank
Pixel n
blank
Gn[3:0]
{Yn[3:0]}
Rn[7:4]
{Crn[7:4]}
val
val
val
val
Rn-1[3:0]
{Crn-1[3:0]}
Bn[7:4]
{Cbn[7:4]}
Rn[3:0]
{Crn[3:0]}
val
val
val
val
Gn-1[7:4]
{Yn-1[7:4]}
Bn[3:0]
{Cbn[3:0}
Gn[7:4]
{Yn[7:4]}
val
val
val
val
IDCK
DE
HSYNC,
VSYNC
Figure 6.4. 8-bit Color Depth RGB/YCbCr 4:4:4 Dual Edge Timing (DRA = 0)
blank
Pixel 0
Pixel 1
Pixel 2
Pixel n - 1
R0[7:4]
{Cr0[7:4]}
G1[3:0]
{Y1[3:0]}
R1[7:4]
{Cr1[7:4]}
G2[3:0]
{Y2[3:0]}
R2[7:4]
{Cr2[7:4]}
Gn-1[3:0]
{Yn-1[3:0]}
Rn-1[7:4]
{Crn-1[7:4]}
blank
Pixel n
blank
Gn[3:0]
{Yn[3:0]}
Rn[7:4]
{Crn[7:4]}
val
val
val
val
D[11:8]
val
G0[3:0]
{Y0[3:0]}
D[7:4]
val
B0[7:4]
{Cb0[7:4]}
R0[3:0]
{Cr0[3:0]}
B1[7:4]
{Cb1[7:4]}
R1[3:0]
{Cr1[3:0]}
B2[7:4]
{Cb2[7:4]}
R2[3:0]
{Cr2[3:0]}
Bn-1[7:4]
{Cbn-1[7:4]}
Rn-1[3:0]
{Crn-1[3:0]}
Bn[7:4]
{Cbn[7:4]}
Rn[3:0]
{Crn[3:0]}
val
val
val
val
D[3:0]
val
B0[3:0]
{Cb0[3:0]}
G0[7:4]
{Y0[7:4]}
B1[3:0]
{Cb1[3:0]}
G1[7:4]
{Y1[7:4]}
B2[3:0]
{Cb2[3:0]}
G2[7:4]
{Y2[7:4]}
Bn-1[3:0]
{Cbn-1[3:0]}
Gn-1[7:4]
{Yn-1[7:4]}
Bn[3:0]
{Cbn[3:0}
Gn[7:4]
{Yn[7:4]}
val
val
val
val
IDCK
DE
HSYNC,
VSYNC
Figure 6.5. 8-bit Color Depth RGB/YCbCr 4:4:4 Dual Edge Timing (DRA = 1)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
47
SiI9573 and SiI9575 Port Processor
Data Sheet
6.10.3. YC 4:2:2 Separate Sync Formats
The input clock runs at the pixel rate and a complete definition of each pixel is received on each input clock cycle. A
luma (Y) value is carried for every pixel, but the chroma values (Cb and Cr) change only every second pixel. The data
bus can be 16 or 20 bits. HSYNC and VSYNC are driven explicitly on their own signals. Each pair of columns in Table
6.7 shows the first and second pixel of n + 1 pixels in the line of video. The DE HIGH time must contain an even
number of pixel clocks.
Table 6.7. YC 4:2:2 Separate Sync Data Mapping
Video Bus
Setting
YCSWAP
16-bit Data Bus
8-bit Color Depth
0
16-bit Data Bus
8-bit Color Depth
1
N/A
20-bit Data Bus
10-bit Color Depth
0
N/A
20-bit Data Bus
10-bit Color Depth
1
DRA
Pin Name
D0
D1
Pixel #0
LOW
LOW
Pixel #1
LOW
LOW
Pixel #0
LOW
LOW
Pixel #1
LOW
LOW
Pixel #0
Cb0[0]
Cb0[1]
N/A
Pixel #1
Cr0[0]
Cr0[1]
Pixel #0
Y0[0]
Y0[1]
Pixel #1
Y1[0]
Y1[1]
D2
D3
Cb0[0]
Cb0[1]
Cr0[0]
Cr0[1]
Y0[0]
Y0[1]
Y1[0]
Y1[1]
Cb0[2]
Cb0[3]
Cr0[2]
Cr0[3]
Y0[2]
Y0[3]
Y1[2]
Y1[3]
D4
D5
D6
Cb0[2]
Cb0[3]
Cb0[4]
Cr0[2]
Cr0[3]
Cr0[4]
Y0[2]
Y0[3]
Y0[4]
Y1[2]
Y1[3]
Y1[4]
Cb0[4]
Cb0[5]
Cb0[6]
Cr0[4]
Cr0[5]
Cr0[6]
Y0[4]
Y0[5]
Y0[6]
Y1[4]
Y1[5]
Y1[6]
D7
D8
Cb0[5]
Cb0[6]
Cr0[5]
Cr0[6]
Y0[5]
Y0[6]
Y1[5]
Y1[6]
Cb0[7]
Cb0[8]
Cr0[7]
Cr0[8]
Y0[7]
Y0[8]
Y1[7]
Y1[8]
D9
D10
D11
Cb0[7]
LOW
LOW
Cr0[7]
LOW
LOW
Y0[7]
LOW
LOW
Y1[7]
LOW
LOW
Cb0[9]
Y0[0]
Y0[1]
Cr0[9]
Y1[0]
Y1[1]
Y0[9]
Cb0[0]
Cb0[1]
Y1[9]
Cr0[0]
Cr0[1]
D12
D13
Y0[0]
Y0[1]
Y1[0]
Y1[1]
Cb0[0]
Cb0[1]
Cr0[0]
Cr0[1]
Y0[2]
Y0[3]
Y1[2]
Y1[3]
Cb0[2]
Cb0[3]
Cr0[2]
Cr0[3]
D14
D15
D16
Y0[2]
Y0[3]
Y0[4]
Y1[2]
Y1[3]
Y1[4]
Cb0[2]
Cb0[3]
Cb0[4]
Cr0[2]
Cr0[3]
Cr0[4]
Y0[4]
Y0[5]
Y0[6]
Y1[4]
Y1[5]
Y1[6]
Cb0[4]
Cb0[5]
Cb0[6]
Cr0[4]
Cr0[5]
Cr0[6]
D17
D18
Y0[5]
Y0[6]
Y1[5]
Y1[6]
Cb0[5]
Cb0[6]
Cr0[5]
Cr0[6]
Y0[7]
Y0[8]
Y1[7]
Y1[8]
Cb0[7]
Cb0[8]
Cr0[7]
Cr0[8]
D19
Y0[7]
Y1[7]
Cb0[7]
Cr0[7]
Y0[9]
Y1[9]
Cb0[9]
Cr0[9]
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
Pixeln - 1 Pixel n
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
D[19:12]
val
Y0[7:0]
Y1[7:0]
Y2[7:0]
Y3[7:0]
Yn -1[7:0]
D[9:2]
val
Cb0[7:0]
Cr0[7:0]
Cb2[7:0]
Cr2[7:0]
Cbn-1[7:0]
N/A
blank
blank
blank
Yn [7:0]
val
val
val
Crn-1[7:0]
val
val
val
IDCK
DE
HSYNC,
VSYNC
Figure 6.6. 8-bit Color Depth YC 4:2:2 Timing (YCSWAP = 0)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
Pixeln - 1 Pixel n
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
D[19:12]
val
Cb0[7:0]
Cr0[7:0]
Cb2[7:0]
Cr2[7:0]
Cbn-1[7:0]
D[9:2]
val
Y0[7:0]
Y1[7:0]
Y2[7:0]
Y3[7:0]
Yn -1[7:0]
blank
blank
blank
Crn-1[7:0]
val
val
val
Yn [7:0]
val
val
val
blank
blank
blank
IDCK
DE
HSYNC,
VSYNC
Figure 6.7. 8-bit Color Depth YC 4:2:2 Timing (YCSWAP = 1)
Pixeln - 1 Pixel n
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
D[19:10]
val
Y0[9:0]
Y1[9:0]
Y2[9:0]
Y3[9:0]
Yn -1[9:0]
Yn [9:0]
val
val
val
D[9:0]
val
Cb0[9:0]
Cr0[9:0]
Cb2[9:0]
Cr2[9:0]
Cbn-1[9:0]
Crn-1[9:0]
val
val
val
blank
blank
blank
IDCK
DE
HSYNC,
VSYNC
Figure 6.8. 10-bit Color Depth YC 4:2:2 Timing (YCSWAP = 0)
Pixeln - 1 Pixel n
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
D[19:10]
val
Cb0[9:0]
Cr0[9:0]
Cb2[9:0]
Cr2[9:0]
Cbn-1[9:0]
Crn-1[9:0]
val
val
val
D[9:0]
val
Y0[9:0]
Y1[9:0]
Y2[9:0]
Y3[9:0]
Yn -1[9:0]
Yn [9:0]
val
val
val
IDCK
DE
HSYNC,
VSYNC
Figure 6.9. 10-bit Color Depth YC 4:2:2 Timing (YCSWAP = 1)
6.10.4. YC 4:2:2 Embedded Syncs Formats
The Embedded Sync format is identical to the YC 4:2:2 formats with Separate Syncs, except that the syncs are
embedded and not explicit. The data bus is 16 bits. Each pair of columns in Table 6.8 shows the first and second pixel of
n + 1 pixels in the line of video.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
49
SiI9573 and SiI9575 Port Processor
Data Sheet
Table 6.8. YC 4:2:2 Embedded Sync Data Mapping
Video Bus
Setting
YCSWAP
DRA
Pin Name
D0
D1
16-bit Data Bus
8-bit Color Depth
0
N/A
Pixel #0
Pixel #1
LOW
LOW
LOW
LOW
16-bit Data Bus
8-bit Color Depth
1
N/A
Pixel #0
Pixel #1
LOW
LOW
LOW
LOW
20-bit Data Bus
10-bit Color Depth
0
N/A
Pixel #0
Pixel #1
Cb0[0]
Cr0[0]
Cb0[1]
Cr0[1]
20-bit Data Bus
10-bit Color Depth
1
N/A
Pixel #0
Pixel #1
Y0[0]
Y1[0]
Y0[1]
Y1[1]
D2
D3
Cb0[0]
Cb0[1]
Cr0[0]
Cr0[1]
Y0[0]
Y0[1]
Y1[0]
Y1[1]
Cb0[2]
Cb0[3]
Cr0[2]
Cr0[3]
Y0[2]
Y0[3]
Y1[2]
Y1[3]
D4
D5
Cb0[2]
Cb0[3]
Cr0[2]
Cr0[3]
Y0[2]
Y0[3]
Y1[2]
Y1[3]
Cb0[4]
Cb0[5]
Cr0[4]
Cr0[5]
Y0[4]
Y0[5]
Y1[4]
Y1[5]
D6
D7
D8
Cb0[4]
Cb0[5]
Cb0[6]
Cr0[4]
Cr0[5]
Cr0[6]
Y0[4]
Y0[5]
Y0[6]
Y1[4]
Y1[5]
Y1[6]
Cb0[6]
Cb0[7]
Cb0[8]
Cr0[6]
Cr0[7]
Cr0[8]
Y0[6]
Y0[7]
Y0[8]
Y1[6]
Y1[7]
Y1[8]
D9
D10
Cb0[7]
LOW
Cr0[7]
LOW
Y0[7]
LOW
Y1[7]
LOW
Cb0[9]
Y0[0]
Cr0[9]
Y1[0]
Y0[9]
Cb0[0]
Y1[9]
Cr0[0]
D11
D12
D13
LOW
Y0[0]
Y0[1]
LOW
Y1[0]
Y1[1]
LOW
Cb0[0]
Cb0[1]
LOW
Cr0[0]
Cr0[1]
Y0[1]
Y0[2]
Y0[3]
Y1[1]
Y1[2]
Y1[3]
Cb0[1]
Cb0[2]
Cb0[3]
Cr0[1]
Cr0[2]
Cr0[3]
D14
D15
Y0[2]
Y0[3]
Y1[2]
Y1[3]
Cb0[2]
Cb0[3]
Cr0[2]
Cr0[3]
Y0[4]
Y0[5]
Y1[4]
Y1[5]
Cb0[4]
Cb0[5]
Cr0[4]
Cr0[5]
D16
D17
D18
Y0[4]
Y0[5]
Y0[6]
Y1[4]
Y1[5]
Y1[6]
Cb0[4]
Cb0[5]
Cb0[6]
Cr0[4]
Cr0[5]
Cr0[6]
Y0[6]
Y0[7]
Y0[8]
Y1[6]
Y1[7]
Y1[8]
Cb0[6]
Cb0[7]
Cb0[8]
Cr0[6]
Cr0[7]
Cr0[8]
D19
Y0[7]
Y1[7]
Cb0[7]
Cr0[7]
Y0[9]
Y1[9]
Cb0[9]
Cr0[9]
HSYNC
VSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
SAV
Pixel 0
Pixel 1
Pixel 2
Pixel 3
Pixel n - 1
EAV
Pixel n
D[19:12]
FF
00
00
XY
Y0[7:0]
Y1[7:0]
Y2[7:0]
Y3[7:0]
Yn-1[7:0]
Yn[7:0]
FF
D[9:2]
FF
00
00
XY
Cb0[7:0]
Cr0[7:0]
Cb2[7:0]
Cr2[7:0]
Cbn-1[7:0]
Crn-1[7:0]
FF
00
00
XY
00
00
XY
IDCK
Active
video
Figure 6.10. 8-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 0)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
50
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
SAV
D[19:12]
FF
00
00
D[9:2]
FF
00
00
Pixel n - 1
Pixel 0
Pixel 1
Pixel 2
Pixel 3
XY
Cb0[7:0]
Cr0[7:0]
Cb2[7:0]
Cr2[7:0]
Cbn-1[7:0]
XY
Y0[7:0]
Y1[7:0]
Y2[7:0]
Y3[7:0]
Yn-1[7:0]
EAV
Pixel n
Crn-1[7:0]
FF
00
00
XY
Yn[7:0]
FF
00
00
XY
IDCK
Active
video
Figure 6.11. 8-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 1)
SAV
Pixel 0
Pixel 1
Pixel 2
Pixel 3
Pixel n - 1
EAV
Pixel n
D[19:10]
FF
00
00
XY
Y0[9:0]
Y1[9:0]
Y2[9:0]
Y3[9:0]
Yn-1[9:0]
Yn[9:0]
FF
00
00
XY
D[9:0]
FF
00
00
XY
Cb0[9:0]
Cr0[9:0]
Cb2[9:0]
Cr2[9:0]
Cbn-1[9:0]
Crn-1[9:0]
FF
00
00
XY
IDCK
Active
video
Figure 6.12. 10-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 0)
SAV
Pixel 0
Pixel 1
Pixel 2
Pixel 3
Pixel n - 1
EAV
Pixel n
D[19:10]
FF
00
00
XY
Cb0[9:0]
Cr0[9:0]
Cb2[9:0]
Cr2[9:0]
Cbn-1[9:0]
Crn-1[9:0]
FF
00
00
XY
D[9:0]
FF
00
00
XY
Y0[9:0]
Y1[9:0]
Y2[9:0]
Y3[9:0]
Yn-1[9:0]
Yn[9:0]
FF
00
00
XY
IDCK
Active
video
Figure 6.13. 10-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 1)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
51
SiI9573 and SiI9575 Port Processor
Data Sheet
6.10.5. YC Mux 4:2:2 Separate Sync Formats Single Clock Edge
The video data is multiplexed onto fewer pins than the mapping described in the YC 4:2:2 Separate Sync Formats
section on page 48. The input clock runs at double the pixel rate so a chroma value is sent for each pixel, followed by a
corresponding luma value for the same pixel. Thus, a luma (Y) value is provided for each pixel, while the Cb and Cr
values alternate on successive pixels. Each group of four columns in Table 6.9 shows the four clock cycles for the first
two pixels of the line. Pixel values for Cb0 and Y0 values are sent with the first pixel (first two clock cycles). Then the Cr0
and Y1 values are sent with the second pixel (next two clock cycles). The figures below the table show how this pattern
is extended for the rest of the pixels in a video line of n + 1 pixels.
Table 6.9. YC Mux 4:2:2 8-bit Color Depth Separate Sync Data Mapping
Video Bus
Setting
YCSWAP
DRA
8-bit Data Bus
8-bit Color Depth
N/A
0
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
LOW
LOW
LOW
LOW
Pin Name
D0
D1
8-bit Data Bus
8-bit Color Depth
N/A
1
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
LOW
LOW
LOW
LOW
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
LOW
LOW
LOW
LOW
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
LOW
LOW
LOW
LOW
D2
D3
D4
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[0]
LOW
LOW
Y0[0]
LOW
LOW
Cr0[0]
LOW
LOW
Y1[0]
D5
D6
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[1]
Cb0[2]
Y0[1]
Y0[2]
Cr0[1]
Cr0[2]
Y1[1]
Y1[2]
D7
D8
D9
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[3]
Cb0[4]
Cb0[5]
Y0[3]
Y0[4]
Y0[5]
Cr0[3]
Cr0[4]
Cr0[5]
Y1[3]
Y1[4]
Y1[5]
D10
D11
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[6]
Cb0[7]
Y0[6]
Y0[7]
Cr0[6]
Cr0[7]
Y1[6]
Y1[7]
D12
D13
D14
Cb0[0]
Cb0[1]
Cb0[2]
Y0[0]
Y0[1]
Y0[2]
Cr0[0]
Cr0[1]
Cr0[2]
Y1[0]
Y1[1]
Y1[2]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D15
D16
Cb0[3]
Cb0[4]
Y0[3]
Y0[4]
Cr0[3]
Cr0[4]
Y1[3]
Y1[4]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D17
D18
Cb0[5]
Cb0[6]
Y0[5]
Y0[6]
Cr0[5]
Cr0[6]
Y1[5]
Y1[6]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D19
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
Pixel 0
D[19:12]
val
Cb0[7:0]
Pixel 1
Y0[7:0]
Cr0[7:0]
Y1[7:0]
Pixel 2
Cb2[7:0]
Y2[7:0]
Pixel 3
Cr2[7:0]
Y3[7:0]
Pixel n - 1
Cbn-1[7:0]
Yn-1[7:0]
Pixel n
Crn-1[7:0]
Yn[7:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.14. 8-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
Pixel 0
D[11:4]
val
Cb0[7:0]
Pixel 1
Y0[7:0]
Cr0[7:0]
Pixel 2
Y1[7:0]
Cb2[7:0]
Pixel 3
Y2[7:0]
Cr2[7:0]
Pixel n - 1
Y3[7:0]
Cbn-1[7:0]
Yn-1[7:0]
Pixel n
Crn-1[7:0]
Yn[7:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.15. 8-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1)
Table 6.10. YC Mux 4:2:2 10-bit Color Depth Separate Sync Data Mapping
Video Bus
Setting
10-bit Data Bus
10-bit Color Depth
10-bit Data Bus
10-bit Color Depth
YCSWAP
DRA
N/A
0
N/A
1
Pin Name
D0
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
LOW
LOW
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
LOW
LOW
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
LOW
LOW
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
LOW
LOW
D1
D2
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[0]
LOW
Y0[0]
LOW
Cr0[0]
LOW
Y1[0]
D3
D4
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[1]
Cb0[2]
Y0[1]
Y0[2]
Cr0[1]
Cr0[2]
Y1[1]
Y1[2]
D5
D6
D7
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[3]
Cb0[4]
Cb0[5]
Y0[3]
Y0[4]
Y0[5]
Cr0[3]
Cr0[4]
Cr0[5]
Y1[3]
Y1[4]
Y1[5]
D8
D9
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[6]
Cb0[7]
Y0[6]
Y0[7]
Cr0[6]
Cr0[7]
Y1[6]
Y1[7]
D10
D11
D12
Cb0[0]
Cb0[1]
Cb0[2]
Y0[0]
Y0[1]
Y0[2]
Cr0[0]
Cr0[1]
Cr0[2]
Y1[0]
Y1[1]
Y1[2]
Cb0[8]
Cb0[9]
LOW
Y0[8]
Y0[9]
LOW
Cr0[8]
Cr0[9]
LOW
Y1[8]
Y1[9]
LOW
D13
D14
Cb0[3]
Cb0[4]
Y0[3]
Y0[4]
Cr0[3]
Cr0[4]
Y1[3]
Y1[4]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D15
D16
D17
Cb0[5]
Cb0[6]
Cb0[7]
Y0[5]
Y0[6]
Y0[7]
Cr0[5]
Cr0[6]
Cr0[7]
Y1[5]
Y1[6]
Y1[7]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D18
D19
Cb0[8]
Cb0[9]
Y0[8]
Y0[9]
Cr0[8]
Cr0[9]
Y1[8]
Y1[9]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
53
SiI9573 and SiI9575 Port Processor
Data Sheet
Pixel 0
D[19:10]
val
Cb0[9:0]
Pixel 1
Y0[9:0]
Cr0[9:0]
Y1[9:0]
Pixel 2
Cb2[9:0]
Y2[9:0]
Pixel 3
Cr2[9:0]
Y3[9:0]
Pixel n - 1
Cbn-1[9:0]
Yn-1[9:0]
Pixel n
Crn-1[9:0]
Yn[9:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.16. 10-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0)
Pixel 0
D[11:2]
val
Cb0[9:0]
Pixel 1
Y0[9:0]
Cr0[9:0]
Y1[9:0]
Pixel 2
Cb2[9:0]
Y2[9:0]
Pixel 3
Cr2[9:0]
Y3[9:0]
Pixel n - 1
Cbn-1[9:0]
Yn-1[9:0]
Pixel n
Crn-1[9:0]
Yn[9:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.17. 10-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
54
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
Table 6.11. YC Mux 4:2:2 12-bit Color Depth Separate Sync Data Mapping
Video Bus
Setting
YCSWAP
DRA
12-bit Data Bus
12-bit Color Depth
N/A
0
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
LOW
LOW
Pin Name
D0
12-bit Data Bus
12-bit Color Depth
N/A
1
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
LOW
LOW
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
Cb0[0]
Y0[0]
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
Cr0[0]
Y1[0]
D1
D2
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[1]
Cb0[2]
Y0[1]
Y0[2]
Cr0[1]
Cr0[2]
Y1[1]
Y1[2]
D3
D4
D5
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[3]
Cb0[4]
Cb0[5]
Y0[3]
Y0[4]
Y0[5]
Cr0[3]
Cr0[4]
Cr0[5]
Y1[3]
Y1[4]
Y1[5]
D6
D7
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[6]
Cb0[7]
Y0[6]
Y0[7]
Cr0[6]
Cr0[7]
Y1[6]
Y1[7]
D8
D9
D10
Cb0[0]
Cb0[1]
Cb0[2]
Y0[0]
Y0[1]
Y0[2]
Cr0[0]
Cr0[1]
Cr0[2]
Y1[0]
Y1[1]
Y1[2]
Cb0[8]
Cb0[9]
Cb0[10]
Y0[8]
Y0[9]
Y0[10]
Cr0[8]
Cr0[9]
Cr0[10]
Y1[8]
Y1[9]
Y1[10]
D11
D12
Cb0[3]
Cb0[4]
Y0[3]
Y0[4]
Cr0[3]
Cr0[4]
Y1[3]
Y1[4]
Cb0[11]
LOW
Y0[11]
LOW
Cr0[11]
LOW
Y1[11]
LOW
D13
D14
Cb0[5]
Cb0[6]
Y0[5]
Y0[6]
Cr0[5]
Cr0[6]
Y1[5]
Y1[6]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D15
D16
D17
Cb0[7]
Cb0[8]
Cb0[9]
Y0[7]
Y0[8]
Y0[9]
Cr0[7]
Cr0[8]
Cr0[9]
Y1[7]
Y1[8]
Y1[9]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D18
D19
Cb0[10]
Cb0[11]
Y0[10]
Y0[11]
Cr0[10]
Cr0[11]
Y1[10]
Y1[11]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
Pixel 0
D[19:8]
val
Cb0[11:0]
Pixel 1
Y0[11:0]
Cr0[11:0]
Y1[11:0]
Pixel 2
Cb2[11:0]
Y2[11:0]
Pixel 3
Cr2[11:0]
Y3[11:0]
Pixel n - 1
Cbn-1[11:0]
Yn-1[11:0]
Pixel n
Crn-1[11:0]
Yn[11:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.18. 12-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
55
SiI9573 and SiI9575 Port Processor
Data Sheet
Pixel 0
D[11:0]
val
Cb0[11:0]
Pixel 1
Y0[11:0]
Cr0[11:0]
Pixel 2
Y1[11:0]
Cb2[11:0]
Y2[11:0]
Pixel 3
Cr2[11:0]
Pixel n - 1
Y3[11:0]
Cbn-1[11:0]
Yn-1[11:0]
Pixel n
Crn-1[11:0]
Yn[11:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.19. 12-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1)
6.10.6. YC Mux 4:2:2 Embedded Sync Formats Single Clock Edge
This format is identical to the one described in the YC Mux 4:2:2 Separate Sync Formats Single Clock Edge section on
page 52, except the syncs are embedded and not explicit. The figures following this table show only the first two pixels
and last pixel of the line and the SAV and EAV sequences, but the remaining pixels are similar to those shown in the
figures of the previous section.
Table 6.12. YC Mux 4:2:2 8-bit Color Depth Embedded Sync Data Mapping
Video Bus
Setting
YCSWAP
DRA
Pin Name
D0
8-bit Data Bus
8-bit Color Depth
N/A
0
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
LOW
LOW
8-bit Data Bus
8-bit Color Depth
N/A
1
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
LOW
LOW
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
LOW
LOW
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
LOW
LOW
D1
D2
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D3
D4
D5
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[0]
Cb0[1]
LOW
Y0[0]
Y0[1]
LOW
Cr0[0]
Cr0[1]
LOW
Y1[0]
Y1[1]
D6
D7
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[2]
Cb0[3]
Y0[2]
Y0[3]
Cr0[2]
Cr0[3]
Y1[2]
Y1[3]
D8
D9
D10
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[4]
Cb0[5]
Cb0[6]
Y0[4]
Y0[5]
Y0[6]
Cr0[4]
Cr0[5]
Cr0[6]
Y1[4]
Y1[5]
Y1[6]
D11
D12
LOW
Cb0[0]
LOW
Y0[0]
LOW
Cr0[0]
LOW
Y1[0]
Cb0[7]
LOW
Y0[7]
LOW
Cr0[7]
LOW
Y1[7]
LOW
D13
D14
Cb0[1]
Cb0[2]
Y0[1]
Y0[2]
Cr0[1]
Cr0[2]
Y1[1]
Y1[2]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D15
D16
D17
Cb0[3]
Cb0[4]
Cb0[5]
Y0[3]
Y0[4]
Y0[5]
Cr0[3]
Cr0[4]
Cr0[5]
Y1[3]
Y1[4]
Y1[5]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D18
D19
Cb0[6]
Cb0[7]
Y0[6]
Y0[7]
Cr0[6]
Cr0[7]
Y1[6]
Y1[7]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
56
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
SAV
D[19:12]
FF
00
Pixel 0
00
XY
Cb0[7:0]
Y0[7:0]
Pixel 1
Cr0[7:0]
Y1[7:0]
EAV
Pixel n
Crn-1[7:0]
Yn[7:0]
FF
00
00
XY
IDCK
Active
video
Figure 6.20. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0)
SAV
D[19:10]
FF
00
00
D[9:0]
FF
00
00
Pixel n - 1
Pixel 0
Pixel 1
Pixel 2
Pixel 3
XY
Cb0[9:0]
Cr0[9:0]
Cb2[9:0]
Cr2[9:0]
Cbn-1[9:0]
XY
Y0[9:0]
Y1[9:0]
Y2[9:0]
Y3[9:0]
Yn-1[9:0]
EAV
Pixel n
Crn-1[9:0]
FF
00
00
XY
Yn[9:0]
FF
00
00
XY
IDCK
Active
video
Figure 6.21. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1)
Table 6.13. YC Mux 4:2:2 10-bit Color Depth Embedded Sync Data Mapping
Video Bus
Setting
YCSWAP
DRA
Pin Name
D0
10-bit Data Bus
10-bit Color Depth
N/A
0
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
LOW
LOW
10-bit Data Bus
10-bit Color Depth
N/A
1
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
LOW
LOW
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
LOW
LOW
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
LOW
LOW
D1
D2
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[0]
LOW
Y0[0]
LOW
Cr0[0]
LOW
Y1[0]
D3
D4
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[1]
Cb0[2]
Y0[1]
Y0[2]
Cr0[1]
Cr0[2]
Y1[1]
Y1[2]
D5
D6
D7
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[3]
Cb0[4]
Cb0[5]
Y0[3]
Y0[4]
Y0[5]
Cr0[3]
Cr0[4]
Cr0[5]
Y1[3]
Y1[4]
Y1[5]
D8
D9
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[6]
Cb0[7]
Y0[6]
Y0[7]
Cr0[6]
Cr0[7]
Y1[6]
Y1[7]
D10
D11
D12
Cb0[0]
Cb0[1]
Cb0[2]
Y0[0]
Y0[1]
Y0[2]
Cr0[0]
Cr0[1]
Cr0[2]
Y1[0]
Y1[1]
Y1[2]
Cb0[8]
Cb0[9]
LOW
Y0[8]
Y0[9]
LOW
Cr0[8]
Cr0[9]
LOW
Y1[8]
Y1[9]
LOW
D13
D14
Cb0[3]
Cb0[4]
Y0[3]
Y0[4]
Cr0[3]
Cr0[4]
Y1[3]
Y1[4]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D15
D16
D17
Cb0[5]
Cb0[6]
Cb0[7]
Y0[5]
Y0[6]
Y0[7]
Cr0[5]
Cr0[6]
Cr0[7]
Y1[5]
Y1[6]
Y1[7]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D18
D19
Cb0[8]
Cb0[9]
Y0[8]
Y0[9]
Cr0[8]
Cr0[9]
Y1[8]
Y1[9]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
57
SiI9573 and SiI9575 Port Processor
Data Sheet
SAV
D[19:10]
FF
00
Pixel 0
00
XY
Cb0[9:0]
Y0[9:0]
Pixel 1
Cr0[9:0]
Y1[9:0]
EAV
Pixel n
Yn[9:0]
Crn-1[9:0]
FF
00
00
XY
00
XY
IDCK
Active
video
Figure 6.22. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0)
SAV
D[11:2]
FF
00
Pixel 0
00
XY
Cb0[9:0]
Y0[9:0]
Pixel 1
Cr0[9:0]
Y1[9:0]
EAV
Pixel n
Crn-1[9:0]
Yn[9:0]
FF
00
IDCK
Active
video
Figure 6.23. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1)
Table 6.14. YC Mux 4:2:2 12-bit Color Depth Embedded Sync Data Mapping
12-bit Data Bus
12-bit Color Depth
N/A
0
Video Bus
Setting
YCSWAP
DRA
Pin Name
D0
D1
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
LOW
LOW
LOW
LOW
12-bit Data Bus
12-bit Color Depth
N/A
1
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
LOW
LOW
LOW
LOW
Pixel #0
1st Clock
2nd Clock
Cycle
Cycle
Cb0[0]
Y0[0]
Cb0[1]
Y0[1]
Pixel #1
3rd Clock
4th Clock
Cycle
Cycle
Cr0[0]
Y1[0]
Cr0[1]
Y1[1]
D2
D3
D4
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[2]
Cb0[3]
Cb0[4]
Y0[2]
Y0[3]
Y0[4]
Cr0[2]
Cr0[3]
Cr0[4]
Y1[2]
Y1[3]
Y1[4]
D5
D6
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[5]
Cb0[6]
Y0[5]
Y0[6]
Cr0[5]
Cr0[6]
Y1[5]
Y1[6]
D7
D8
D9
LOW
Cb0[0]
Cb0[1]
LOW
Y0[0]
Y0[1]
LOW
Cr0[0]
Cr0[1]
LOW
Y1[0]
Y1[1]
Cb0[7]
Cb0[8]
Cb0[9]
Y0[7]
Y0[8]
Y0[9]
Cr0[7]
Cr0[8]
Cr0[9]
Y1[7]
Y1[8]
Y1[9]
D10
D11
Cb0[2]
Cb0[3]
Y0[2]
Y0[3]
Cr0[2]
Cr0[3]
Y1[2]
Y1[3]
Cb0[10]
Cb0[11]
Y0[10]
Y0[11]
Cr0[10]
Cr0[11]
Y1[10]
Y1[11]
D12
D13
Cb0[4]
Cb0[5]
Y0[4]
Y0[5]
Cr0[4]
Cr0[5]
Y1[4]
Y1[5]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D14
D15
D16
Cb0[6]
Cb0[7]
Cb0[8]
Y0[6]
Y0[7]
Y0[8]
Cr0[6]
Cr0[7]
Cr0[8]
Y1[6]
Y1[7]
Y1[8]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D17
D18
Cb0[9]
Cb0[10]
Y0[9]
Y0[10]
Cr0[9]
Cr0[10]
Y1[9]
Y1[10]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D19
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
LOW
LOW
LOW
LOW
HSYNC
VSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
58
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
SAV
D[19:8]
FF
00
Pixel 0
00
XY
Cb0[11:0]
Y0[11:0]
Cr0[11:0]
Y1[11:0]
EAV
Pixel n
Pixel 1
Crn-1[11:0]
Yn[11:0]
FF
00
00
XY
00
XY
IDCK
Active
video
Figure 6.24. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0)
SAV
D[11:0]
FF
00
Pixel 0
00
XY
Cb0[11:0]
Y0[11:0]
Cr0[11:0]
Y1[11:0]
EAV
Pixel n
Pixel 1
Crn-1[11:0]
Yn[11:0]
FF
00
IDCK
Active
video
Figure 6.25. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1)
6.10.7. YC Mux 4:2:2 Separate Sync Formats Dual Clock Edge
The video data is multiplexed onto fewer pins than the mapping described in the YC 4:2:2 Separate Sync Formats on
page 48. The input clock runs at the pixel rate and a complete definition of each pixel is received on each input clock
cycle. The chroma value is sent for each pixel, followed by a corresponding luma value for the same pixel. Thus, a luma
(Y) value is provided for each pixel, while the Cb and Cr values alternate on successive pixels. One clock edge latches in
half the pixel data. The opposite clock edge latches in the remaining half of the pixel data on the same pins.
Each group of four columns in Table 6.9 shows the two clock cycles for the first two pixels of the line. Pixel values for
Cb0 and Y0 values are sent with the first pixel (first and second clock edges of the first clock cycle). Then the Cr0 and Y1
values are sent with the second pixel (first and second clock edges of the second clock cycle). The figures below the
table show how this pattern is extended for the rest of the pixels in a video line of n + 1 pixels.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
59
SiI9573 and SiI9575 Port Processor
Data Sheet
Table 6.15. YC Mux 4:2:2 8-bit Color Depth Separate Sync Dual Clock Edge Data Mapping
Video Bus
Setting
YCSWAP
DRA
8-bit Data Bus
8-bit Color Depth
0
0
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
Pin Name
D0
8-bit Data Bus
8-bit Color Depth
1
1
Pixel #1
2nd Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
Pixel #1
2nd Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
D1
D2
D3
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D4
D5
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Y0[0]
Y0[1]
Cb0[0]
Cb0[1]
Y1[0]
Y1[1]
Cr0[0]
Cr0[1]
D6
D7
D8
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Y0[2]
Y0[3]
Y0[4]
Cb0[2]
Cb0[3]
Cb0[4]
Y1[2]
Y1[3]
Y1[4]
Cr0[2]
Cr0[3]
Cr0[4]
D9
D10
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Y0[5]
Y0[6]
Cb0[5]
Cb0[6]
Y1[5]
Y1[6]
Cr0[5]
Cr0[6]
D11
D12
D13
LOW
Cb0[0]
Cb0[1]
LOW
Y0[0]
Y0[1]
LOW
Cr0[0]
Cr0[1]
LOW
Y1[0]
Y1[1]
Y0[7]
LOW
LOW
Cb0[7]
LOW
LOW
Y1[7]
LOW
LOW
Cr0[7]
LOW
LOW
D14
D15
Cb0[2]
Cb0[3]
Y0[2]
Y0[3]
Cr0[2]
Cr0[3]
Y1[2]
Y1[3]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D16
D17
Cb0[4]
Cb0[5]
Y0[4]
Y0[5]
Cr0[4]
Cr0[5]
Y1[4]
Y1[5]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D18
D19
Cb0[6]
Cb0[7]
Y0[6]
Y0[7]
Cr0[6]
Cr0[7]
Y1[6]
Y1[7]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
Pixel n - 1
Pixel n
Pixel 0
D[19:12]
val
Cb0[7:0]
Y0[7:0]
Pixel 1
Cr0[7:0]
Y1[7:0]
Pixel 2
Cb2[7:0]
Y2[7:0]
Pixel 3
Cr2[7:0]
Y3[7:0]
Cbn-1[7:0]
Yn-1[7:0]
Crn-1[7:0]
Yn[7:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.26. 8-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
60
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
Pixel 0
D[11:4]
val
Y0[7:0]
Cb0[7:0]
Pixel 1
Y1[7:0]
Pixel 2
Cr0[7:0]
Y2[7:0]
Pixel 3
Cb2[7:0]
Y3[7:0]
Pixel n - 1
Cr2[7:0]
Yn-1[7:0]
Cbn-1[7:0]
Pixel n
Yn[7:0]
Crn-1[7:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.27. 8-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 1)
Table 6.16. YC Mux 4:2:2 10-bit Color Depth Separate Sync Dual Clock Edge Data Mapping
Video Bus
Setting
YCSWAP
DRA
Pin Name
D0
D1
10-bit Data Bus
10-bit Color Depth
0
0
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
LOW
LOW
10-bit Data Bus
10-bit Color Depth
0
1
Pixel #1
2nd Clock
3rd Clock
4th Clock
Edge
Edge
LOW
LOW
LOW
LOW
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
LOW
LOW
Pixel #1
2nd Clock
3rd Clock
4th Clock
Edge
Edge
LOW
LOW
LOW
LOW
D2
D3
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[0]
Cb0[1]
Y0[0]
Y0[1]
Cr0[0]
Cr0[1]
Y1[0]
Y1[1]
D4
D5
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[2]
Cb0[3]
Y0[2]
Y0[3]
Cr0[2]
Cr0[3]
Y1[2]
Y1[3]
D6
D7
D8
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[4]
Cb0[5]
Cb0[6]
Y0[4]
Y0[5]
Y0[6]
Cr0[4]
Cr0[5]
Cr0[6]
Y1[4]
Y1[5]
Y1[6]
D9
D10
LOW
Cb0[0]
LOW
Y0[0]
LOW
Cr0[0]
LOW
Y1[0]
Cb0[7]
Cb0[8]
Y0[7]
Y0[8]
Cr0[7]
Cr0[8]
Y1[7]
Y1[8]
D11
D12
D13
Cb0[1]
Cb0[2]
Cb0[3]
Y0[1]
Y0[2]
Y0[3]
Cr0[1]
Cr0[2]
Cr0[3]
Y1[1]
Y1[2]
Y1[3]
Cb0[9]
LOW
LOW
Y0[9]
LOW
LOW
Cr0[9]
LOW
LOW
Y1[9]
LOW
LOW
D14
D15
Cb0[4]
Cb0[5]
Y0[4]
Y0[5]
Cr0[4]
Cr0[5]
Y1[4]
Y1[5]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D16
D17
D18
Cb0[6]
Cb0[7]
Cb0[8]
Y0[6]
Y0[7]
Y0[8]
Cr0[6]
Cr0[7]
Cr0[8]
Y1[6]
Y1[7]
Y1[8]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D19
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
61
SiI9573 and SiI9575 Port Processor
Data Sheet
Pixel 0
D[19:10]
val
Cb0[9:0]
Y0[9:0]
Pixel 1
Cr0[9:0]
Y1[9:0]
Pixel 2
Cb2[9:0]
Y2[9:0]
Pixel 3
Cr2[9:0]
Y3[9:0]
Pixel n - 1
Cbn-1[9:0]
Yn-1[9:0]
Pixel n
Crn-1[9:0]
Yn[9:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.28. 10-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0)
Pixel 0
D[11:2]
val
Cb0[9:0]
Y0[9:0]
Pixel 1
Cr0[9:0]
Y1[9:0]
Pixel 2
Cb2[9:0]
Y2[9:0]
Pixel 3
Cr2[9:0]
Y3[9:0]
Pixel n - 1
Cbn-1[9:0]
Yn-1[9:0]
Pixel n
Crn-1[9:0]
Yn[9:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.29. 10-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 0)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
62
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
Table 6.17. YC Mux 4:2:2 12-bit Color Depth Separate Sync Dual Clock Edge Data Mapping
Video Bus
Setting
YCSWAP
DRA
12-bit Data Bus
12-bit Color Depth
0
0
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
Pin Name
D0
12-bit Data Bus
12-bit Color Depth
0
1
Pixel #1
2nd Clock
3rd Clock
4th Clock
Edge
Edge
LOW
LOW
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
Cb0[0]
Y0[0]
Pixel #1
2nd Clock
3rd Clock
4th Clock
Edge
Edge
Cr0[0]
Y1[0]
D1
D2
D3
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[1]
Cb0[2]
Cb0[3]
Y0[1]
Y0[2]
Y0[3]
Cr0[1]
Cr0[2]
Cr0[3]
Y1[1]
Y1[2]
Y1[3]
D4
D5
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[4]
Cb0[5]
Y0[4]
Y0[5]
Cr0[4]
Cr0[5]
Y1[4]
Y1[5]
D6
D7
D8
LOW
LOW
Cb0[0]
LOW
LOW
Y0[0]
LOW
LOW
Cr0[0]
LOW
LOW
Y1[0]
Cb0[6]
Cb0[7]
Cb0[8]
Y0[6]
Y0[7]
Y0[8]
Cr0[6]
Cr0[7]
Cr0[8]
Y1[6]
Y1[7]
Y1[8]
D9
D10
Cb0[1]
Cb0[2]
Y0[1]
Y0[2]
Cr0[1]
Cr0[2]
Y1[1]
Y1[2]
Cb0[9]
Cb0[10]
Y0[9]
Y0[10]
Cr0[9]
Cr0[10]
Y1[9]
Y1[10]
D11
D12
D13
Cb0[3]
Cb0[4]
Cb0[5]
Y0[3]
Y0[4]
Y0[5]
Cr0[3]
Cr0[4]
Cr0[5]
Y1[3]
Y1[4]
Y1[5]
Cb0[11]
LOW
LOW
Y0[11]
LOW
LOW
Cr0[11]
LOW
LOW
Y1[11]
LOW
LOW
D14
D15
Cb0[6]
Cb0[7]
Y0[6]
Y0[7]
Cr0[6]
Cr0[7]
Y1[6]
Y1[7]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D16
D17
D18
Cb0[8]
Cb0[9]
Cb0[10]
Y0[8]
Y0[9]
Y0[10]
Cr0[8]
Cr0[9]
Cr0[10]
Y1[8]
Y1[9]
Y1[10]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D19
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
Pixel n - 1
Pixel n
Pixel 0
D[19:8]
val
Cb0[11:0]
Y0[11:0]
Pixel 1
Cr0[11:0]
Y1[11:0]
Pixel 2
Cb2[11:0]
Y2[11:0]
Pixel 3
Cr2[11:0]
Y3[11:0]
Cbn-1[11:0]
Yn-1[11:0]
Crn-1[11:0]
Yn[11:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.30. 12-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
63
SiI9573 and SiI9575 Port Processor
Data Sheet
Pixel 0
D[11:0]
val
Cb0[11:0]
Y0[11:0]
Pixel 1
Cr0[11:0]
Pixel 2
Y1[11:0]
Cb2[11:0]
Pixel 3
Y2[11:0]
Cr2[11:0]
Pixel n - 1
Y3[11:0]
Cbn-1[11:0]
Yn-1[11:0]
Pixel n
Crn-1[11:0]
Yn[11:0]
val
IDCK
DE
HSYNC
VSYNC
Figure 6.31. 12-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 0)
6.10.8. YC Mux 4:2:2 Embedded Sync Formats Dual Clock Edge
This format is identical to the one described in the YC Mux 4:2:2 Separate Sync Formats Dual Clock Edge section on page
59, except the syncs are embedded and not explicit. The figures following this table show only the first two pixels and
last pixel of the line and the SAV and EAV sequences, but the remaining pixels are similar to those shown in the figures
of the previous section.
Table 6.18. YC Mux 4:2:2 8-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping
Video Bus
Setting
YCSWAP
DRA
Pin Name
D0
8-bit Data Bus
8-bit Color Depth
0
0
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
8-bit Data Bus
8-bit Color Depth
1
1
Pixel #1
2nd Clock
3rd Clock
4th Clock
Edge
Edge
LOW
LOW
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
Pixel #1
2nd Clock
3rd Clock
4th Clock
Edge
Edge
LOW
LOW
D1
D2
D3
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D4
D5
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Y0[0]
Y0[1]
Cb0[0]
Cb0[1]
Y1[0]
Y1[1]
Cr0[0]
Cr0[1]
D6
D7
D8
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Y0[2]
Y0[3]
Y0[4]
Cb0[2]
Cb0[3]
Cb0[4]
Y1[2]
Y1[3]
Y1[4]
Cr0[2]
Cr0[3]
Cr0[4]
D9
D10
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Y0[5]
Y0[6]
Cb0[5]
Cb0[6]
Y1[5]
Y1[6]
Cr0[5]
Cr0[6]
D11
D12
LOW
Cb0[0]
LOW
Y0[0]
LOW
Cr0[0]
LOW
Y1[0]
Y0[7]
LOW
Cb0[7]
LOW
Y1[7]
LOW
Cr0[7]
LOW
D13
D14
D15
Cb0[1]
Cb0[2]
Cb0[3]
Y0[1]
Y0[2]
Y0[3]
Cr0[1]
Cr0[2]
Cr0[3]
Y1[1]
Y1[2]
Y1[3]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D16
D17
Cb0[4]
Cb0[5]
Y0[4]
Y0[5]
Cr0[4]
Cr0[5]
Y1[4]
Y1[5]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D18
D19
Cb0[6]
Cb0[7]
Y0[6]
Y0[7]
Cr0[6]
Cr0[7]
Y1[6]
Y1[7]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
64
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
SAV
D[19:12]
FF
FF
00
00
Pixel 0
00
00
00
00
XY
XY
00
00
Pixel 1
Cb0[7:0]
Y0[7:0]
XY
XY
Cr0[7:0]
Y1[7:0]
IDCK
Active
video
Pixel n
D[19:12]
EAV
Yn[7:0]
Crn-1[7:0]
FF
FF
IDCK
Active
video
Figure 6.32. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0)
SAV
D[11:4]
FF
FF
00
00
Pixel 0
00
00
XY
XY
00
00
Pixel 1
Y0[7:0]
Cb0[7:0]
XY
XY
Y1[7:0]
Cr0[7:0]
IDCK
Active
video
Pixel n
D[11:4]
Yn[7:0]
Crn-1[7:0]
EAV
FF
FF
00
00
IDCK
Active
video
Figure 6.33. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 1)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
65
SiI9573 and SiI9575 Port Processor
Data Sheet
Table 6.19. YC Mux 4:2:2 10-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping
Video Bus
Setting
YCSWAP
DRA
Pin Name
D0
10-bit Data Bus
10-bit Color Depth
0
0
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
10-bit Data Bus
10-bit Color Depth
0
1
Pixel #1
2nd Clock
3rd Clock
4th Clock
Edge
Edge
LOW
LOW
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
Pixel #1
2nd Clock
3rd Clock
4th Clock
Edge
Edge
LOW
LOW
D1
D2
D3
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[0]
Cb0[1]
LOW
Y0[0]
Y0[1]
LOW
Cr0[0]
Cr0[1]
LOW
Y1[0]
Y1[1]
D4
D5
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[2]
Cb0[3]
Y0[2]
Y0[3]
Cr0[2]
Cr0[3]
Y1[2]
Y1[3]
D6
D7
D8
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[4]
Cb0[5]
Cb0[6]
Y0[4]
Y0[5]
Y0[6]
Cr0[4]
Cr0[5]
Cr0[6]
Y1[4]
Y1[5]
Y1[6]
D9
D10
LOW
Cb0[0]
LOW
Y0[0]
LOW
Cr0[0]
LOW
Y1[0]
Cb0[7]
Cb0[8]
Y0[7]
Y0[8]
Cr0[7]
Cr0[8]
Y1[7]
Y1[8]
D11
D12
D13
Cb0[1]
Cb0[2]
Cb0[3]
Y0[1]
Y0[2]
Y0[3]
Cr0[1]
Cr0[2]
Cr0[3]
Y1[1]
Y1[2]
Y1[3]
Cb0[9]
LOW
LOW
Y0[9]
LOW
LOW
Cr0[9]
LOW
LOW
Y1[9]
LOW
LOW
D14
D15
Cb0[4]
Cb0[5]
Y0[4]
Y0[5]
Cr0[4]
Cr0[5]
Y1[4]
Y1[5]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D16
D17
D18
Cb0[6]
Cb0[7]
Cb0[8]
Y0[6]
Y0[7]
Y0[8]
Cr0[6]
Cr0[7]
Cr0[8]
Y1[6]
Y1[7]
Y1[8]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D19
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
LOW
LOW
LOW
LOW
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
SAV
D[19:10]
FF
FF
00
00
Pixel 0
00
00
XY
XY
00
00
Pixel 1
Cb0[9:0]
Y0[9:0]
XY
XY
Cr0[9:0]
Y1[9:0]
IDCK
Active
video
Pixel n
D[19:10]
Crn-1[9:0]
Yn[9:0]
EAV
FF
FF
00
00
IDCK
Active
video
Figure 6.34. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
66
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
SAV
D[11:2]
FF
FF
00
00
Pixel 0
00
00
XY
XY
00
00
Pixel 1
Cb0[9:0]
Y0[9:0]
XY
XY
Cr0[9:0]
Y1[9:0]
IDCK
Active
video
Pixel n
D[11:2]
Crn-1[9:0]
Yn[9:0]
EAV
FF
FF
00
00
IDCK
Active
video
Figure 6.35. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 0)
Table 6.20. YC Mux 4:2:2 12-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping
Video Bus
Setting
YCSWAP
DRA
Pin Name
D0
D1
12-bit Data Bus
12-bit Color Depth
0
0
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
LOW
LOW
LOW
LOW
12-bit Data Bus
12-bit Color Depth
0
1
Pixel #1
2nd Clock
3rd Clock
4th Clock
Edge
Edge
LOW
LOW
LOW
LOW
Pixel #0
1st Clock
1st Clock
2nd Clock
Edge
Edge
Cb0[0]
Y0[0]
Cb0[1]
Y0[1]
Pixel #1
2nd Clock
3rd Clock
4th Clock
Edge
Edge
Cr0[0]
Y1[0]
Cr0[1]
Y1[1]
D2
D3
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[2]
Cb0[3]
Y0[2]
Y0[3]
Cr0[2]
Cr0[3]
Y1[2]
Y1[3]
D4
D5
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Cb0[4]
Cb0[5]
Y0[4]
Y0[5]
Cr0[4]
Cr0[5]
Y1[4]
Y1[5]
D6
D7
D8
LOW
LOW
Cb0[0]
LOW
LOW
Y0[0]
LOW
LOW
Cr0[0]
LOW
LOW
Y1[0]
Cb0[6]
Cb0[7]
Cb0[8]
Y0[6]
Y0[7]
Y0[8]
Cr0[6]
Cr0[7]
Cr0[8]
Y1[6]
Y1[7]
Y1[8]
D9
D10
Cb0[1]
Cb0[2]
Y0[1]
Y0[2]
Cr0[1]
Cr0[2]
Y1[1]
Y1[2]
Cb0[9]
Cb0[10]
Y0[9]
Y0[10]
Cr0[9]
Cr0[10]
Y1[9]
Y1[10]
D11
D12
D13
Cb0[3]
Cb0[4]
Cb0[5]
Y0[3]
Y0[4]
Y0[5]
Cr0[3]
Cr0[4]
Cr0[5]
Y1[3]
Y1[4]
Y1[5]
Cb0[11]
LOW
LOW
Y0[11]
LOW
LOW
Cr0[11]
LOW
LOW
Y1[11]
LOW
LOW
D14
D15
Cb0[6]
Cb0[7]
Y0[6]
Y0[7]
Cr0[6]
Cr0[7]
Y1[6]
Y1[7]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D16
D17
D18
Cb0[8]
Cb0[9]
Cb0[10]
Y0[8]
Y0[9]
Y0[10]
Cr0[8]
Cr0[9]
Cr0[10]
Y1[8]
Y1[9]
Y1[10]
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D19
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
LOW
LOW
LOW
LOW
HSYNC
VSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
67
SiI9573 and SiI9575 Port Processor
Data Sheet
SAV
D[19:8]
FF
FF
00
00
Pixel 0
00
00
XY
XY
00
00
Pixel 1
Cb0[11:0]
Y0[11:0]
XY
XY
Cr0[11:0]
Y1[11:0]
IDCK
Active
video
Pixel n
D[19:8]
Crn-1[11:0]
EAV
Yn[11:0]
FF
FF
00
00
IDCK
Active
video
Figure 6.36. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0)
SAV
D[11:0]
FF
FF
00
00
Pixel 0
00
00
XY
XY
00
00
Pixel 1
Cb0[11:0]
Y0[11:0]
XY
XY
Cr0[11:0]
Y1[11:0]
IDCK
Active
video
Pixel n
D[11:0]
Crn-1[11:0]
Yn[11:0]
EAV
FF
FF
00
00
IDCK
Active
video
Figure 6.37. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 0)
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
68
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
7. Design Recommendations
7.1. Power Supply Decoupling
Designers should include decoupling and bypass capacitors at each power signal in the layout. These are shown
schematically in Figure 7.1. Connections in one group (such as AVDD33) can share C2, C3, and the ferrite, with each pin
having a separate C1 placed as close to the pin as possible. Figure 7.2 is representative of the various types of power
connections on the port processor.
The recommended impedance of the ferrite is 10  or more in the frequency range of 1 to 2 MHz.
+3.3 V
L1
VDD Pin
C1
C2
C3
GND
Figure 7.1. Decoupling and Bypass Schematic
+3.3 V
C1
C2
L1
VDD
Ferrite
C3
Via to GND
Figure 7.2. Decoupling and Bypass Capacitor Placement
7.2. Power Supply Control Timing and Sequencing
All power supplies in the SiI957n port processor are independent. However, identical supplies must be provided at the
same time. For example, all three AVDD33 supplies have to be turned on at the same time.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
69
SiI9573 and SiI9575 Port Processor
Data Sheet
8. Package Information
8.1. ePad Requirements
The SiI957n device is packaged in a 176-pin, 20 mm × 20mm TQFP package with an exposed pad (ePad) that is used for
the electrical ground of the device and for improved thermal transfer characteristics. The ePad dimensions are
7.500 mm × 6.740 mm ±0.20 mm. Soldering the ePad to the ground plane of the PCB is required to meet package
power dissipation requirements at full speed operation, and to correctly connect the chip circuitry to electrical ground.
A clearance of at least 0.25 mm should be designed on the PCB between the edge of the ePad and the inner edges of
the lead pads to avoid the possibility of electrical short circuits.
The thermal land area on the PCB may use thermal vias to improve heat removal from the package. These thermal vias
also double as the ground connections of the chip and must attach internally in the PCB to the ground plane. An array
of vias should be designed into the PCB beneath the package. For optimum thermal performance, the via diameter
should be 12 mils to 13 mils (0.30 mm to 0.33 mm) and the via barrel should be plated with 1-ounce copper to plug the
via. This design helps to avoid any solder wicking inside the via during the soldering process, which may result in voids
in solder between the pad and the thermal land. If the copper plating does not plug the vias, the thermal vias can be
tented with solder mask on the top surface of the PCB to avoid solder wicking inside the via during assembly. The solder
mask diameter should be at least 4 mils (0.1 mm) larger than the via diameter.
Package stand-off when mounting the device also needs to be considered. For a nominal stand-off of approximately
0.1 mm, the stencil thickness of 5 mils to 8 mils should provide a good solder joint between the ePad and the thermal
land.
Figure 8.1 on the next page shows the package dimensions of the SiI957n port processor.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
70
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
8.2. Package Dimensions
These drawings are not to scale. All dimensions are in millimeters.
D
D1
D2
7.500 ± 0.20
D
132
89
88
133
A
A
R1
R2
B
A
6.740 ± 0.20
H
GAGE PLANE
E2 E1 E
S
0.25 C
L
SECTION A-A
0.05
176
Pin 1
Identifier
45
1
44
e
0.07
b
M
C A–B S D S
A2
L1
4X
4X
A
S
H A–B D
H A–B D
0.20
0.20
A1
DETAIL A
TOP VIEW
0.08
DETAIL B
DETAIL A
SIDE VIEW
C
SEATING PLANE
C
DETAIL B
JEDEC Package Code MS-026
Item
Description
Min
Typ
Max
Item
Description
A
Thickness
1.00
1.10
1.20
b
Lead width
A1
A2
D
Stand-off
Body thickness
Footprint
0.05
0.95
0.10
1.00
22.00 BSC
0.15
1.05
C
e
L
Lead thickness
Lead pitch
Lead foot length
E
D1
Footprint
Body size
L1
R1
E1
D2
E2
Body size
—
—
R2
S
22.00 BSC
20.00 BSC
—
—
20.00 BSC
17.20
17.20
—
—
Min
Typ
Max
—
0.16
—
0.09
0.20
0.45
—
0.40 BSC
0.60
Total lead length
Lead radius, inside
0.08
1.00 REF
—
—
Lead radius, outside
Lead horizontal run
0.08
0.20
—
—
0.20
—
0.75
Figure 8.1. Package Diagram
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
71
SiI9573 and SiI9575 Port Processor
Data Sheet
8.3. Marking Specification
Figure 8.2 shows the markings of the SiI957n package. This drawing is not to scale.
Logo
SiI957n CTUC
LLLLLL.LL-L
YYWW
XXXXXXX
Pin 1 location
Silicon Image Part Number
Lot # (= Job#)
Date code
Trace code
SiIxxxxrpppp-sXXXX
Product
Designation
Special
Designation
Revision
Speed
Package Type
Figure 8.2. Marking Diagram
8.4. Ordering Information
Production Part Numbers:
Device
Part Number
Standard
SiI9573CTUC
With ViaPort Matrix Switch
SiI9575CTUC
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
72
SiI-DS-1089-F
SiI9573 and SiI9575 Port Processor
Data Sheet
References
Standards Documents
This is a list of standards abbreviations appearing in this document, and references to their respective specifications
documents.
Abbreviation
HDMI
HCTS
Standards publication, organization, and date
High Definition Multimedia Interface, Revision 1.4a, HDMI Licensing, LLC, March 2010
HDMI Compliance Test Specification, Revision 1.4a, HDMI Licensing, LLC, March 2010
HDCP
DVI
High-bandwidth Digital Content Protection, Revision 1.4, Digital Content Protection, LLC; July 2009
Digital Visual Interface, Revision 1.0, Digital Display Working Group; April 1999
E-EDID
E-DID IG
EDDC
Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA; Feb. 2000
VESA EDID Implementation Guide, VESA, June 2001
Enhanced Display Data Channel Standard, Version 1.1, VESA; March 2004
MHL
MHL (Mobile High-Definition Link) Specification, Version 1.2, MHL, LLC, June 2010
Standards Groups
For information on the specifications that apply to this document, contact the responsible standards groups appearing
on this list.
Standards Group
ANSI/EIA/CEA
Web URL
http://global.ihs.com
VESA
HDCP
http://www.vesa.org
http://www.digital-cp.com
DVI
HDMI
MHL
http://www.ddwg.org
http://www.hdmi.org
http://www.mhlconsortium.org
Lattice Semiconductor Documents
This is a list of the related documents that are available from your Lattice Semiconductor sales representative.
The Programmer Reference requires an NDA with Lattice Semiconductor.
Document
SiI-PR-1054
SiI-PR-0041
Title
SiI9573, SiI9575, and SiI9523 Port Processor Programmer’s Reference
CEC Programming Interface (CPI) Programmer’s Reference
Technical Support
For assistance, submit a technical support case at www.latticesemi.com/techsupport.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
73
SiI9573 and SiI9575 Port Processor
Data Sheet
Revision History
Revision F, March 2016
Updated to latest template.
Revision F, December 2013
 Added 4K × 2K 50/60 FPS support.
 Added new section on Support for UltraHD resolution at 50P/60P frames per second.
Revision E, September 2013

Removed statement of “only” on OSD resolution limitations in On-screen Display Controller section.

Added Note 2 and updated to Note 3 in Table 3.2. Updated current values in Table 3.11: IAVDDI13 from 240 to 250,
IAVDDI33 from 330 to 345, and ICVCC13 from 650 to 680 mA.

Updated Note 3 in Table 3.11 from “three 225 MHz” to “six 300 MHz.”
Revision D, May 2013
2
Added information about I C setup time.
Revision C, January 2013
Updated OSD video support and SBVCC5 voltage measurement; added VS insertion description.
Revision B, August 2012
Updated 3D L/R section, and Table 7; global grammatical changes.
Revision A, January 2012
First production release.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
74
SiI-DS-1089-F
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th
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