Plastic Packages for Integrated Circuits Package Outline Drawing W8x9.72A 72 Ball Wafer Level Chip Scale Package (WLCSP 0.4mm Pitch) Rev 0, 2/15 X Y 0.400 3.270±0.030 J 72x 0.265 ±0.035 H G F E 3.670 ±0.030 D C B 0.2350 A (4X) 0.10 1 TOP VIEW PIN 1 (A1 CORNER) 2 3 4 5 7 6 8 0.2350 0.200 BOTTOM VIEW 0.05 Z PACKAGE OUTLINE 0.240 Z SEATING PLANE 3 0.290 2 0.265 ±0.035 0.10 0.05 0.400 4 6 NSMD 0.200 ±0.030 RECOMMENDED LAND PATTERN 0.500 ±0.050 SIDE VIEW NOTES: 1. Dimensions and tolerance and tolerance per ASMEY 14.5 - 1994. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z . 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 4. Bump position designation per JESD 95-1, SPP-010. 5. All dimensions are in millimeters. 6. NSMD refers to non-solder mask defined pad design per Intersil Techbrief http://www.intersil.com/data/tb/tb451.pdf 1 Z X Y Z