Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W3x3.9D
3x3 ARRAY 9 BALLS WITH 0.40 PITCH WAFER LEVEL CHIP SCALE PACKAGE (WITH BSC)
Rev 0, 1/14
X
Y
1.410 ± 0.030
0.400
C
9 x 0.265 ± 0.035
1.410 ± 0.030
B
0.305
A
(4X)
0.10
1
TOP VIEW
2
3
PIN 1
(A1 CORNER)
0.305
BOTTOM VIEW
Z
0.05
SEATING PLANE
Z
3
PACKAGE OUTLINE
0.240
0.040BSC
(BACK SIDE COATING)
0.400
0.265 ± 0.035
0.290
RECOMMENDED LAND PATTERN
0.10
Z X Y
0.05
Z
0.200 ± 0.030
0.540 ± 0.050
SIDE VIEW
NOTES:
1. All dimensions are in millimeters.
2. Dimension and tolerance per ASMEY 14.5 - 1994,
and JESD 95-1 SPP-010.
3. NSMD refers to Non-Solder Mask Defined pad design per
Intersil Tech Brief TB451 located at:
http://www.intersil.com/content/dam/Intersil/documents/
tb45/tb451.pdf
1