Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W11x11.121B
121 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP 0.5mm pitch)
Rev 0, 2/14
5.526±0.030
X
0.500
Y
121x 0.320±0.030
L
K
J
H
G
5.540±0.030
F
E
D
C
B
0.270
A
(4X)
1
0.10
2
3
4
5
6
7
8
9
10 11
0.263
0.500
PIN 1
TOP VIEW
BOTTOM VIEW
Z SEATING PLANE
0.05 Z
PACKAGE OUTLINE
0.330
0.500
0.320±0.030
121x
0.10 M Z X Y
0.05 M Z
0.280
0.240±0.030
0.600±0.060
3 NSMD
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. All dimensions are in millimeters.
2. Dimensions and tolerance per ASMEY 14.5M - 1994 and JESD 95-1, SPP-010.
3. NSMD refers to non-solder mask defined pad design per Intersil Techbrief TB451.
1
SIDE VIEW

Open as PDF

Similar pages: Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD); Package Outline Drawing (POD)