Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W5x6.30C
5X6 ARRAY 30 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
Rev 0, 6/14
1.600
X
Y
2.330±0.030
0.400
F
E
30x 0.265±0.035
D
2.000
2.610±0.030
C
B
A
0.305
(4X)
0.10
1
2
3
4
5
0.400
PIN 1 (A1 CORNER)
TOP VIEW
0.365
BOTTOM VIEW
Z
0.05 Z
PACKAGE OUTLINE
SEATING PLANE
3
0.240
0.290
0.400
0.265±0.035 30x
0.10 M Z X Y
0.05 M Z
0.200±0.030
TYPICAL RECOMMENDED LAND PATTERN
0.500±0.050
SIDE VIEW
NOTES:
1. Dimensions and tolerance per ASME Y 14.5M - 1994.
2. Dimension is measured at the maximum bump diameter
parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical
crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
5. There shall be a minimum clearance of 0.10mm between
the edge of the bump and the body edge.
1