Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W3x5.15A
15 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP 0.4mm pitch)
Rev 0, 7/14
X
1.51 ±0.030
0.800
Y
0.400
E
15X 0.265 ±0.035
2.15 ±0.030
D
1.600
C
B
(4X)
0.275
A
0.10
1
2
3
PIN 1
(A1 CORNER)
0.355
TOP VIEW
BOTTOM VIEW
0.05 Z
PACKAGE OUTLINE
0.240
SEATING PLANE
3
0.040 BSC
(BACKSIDE COATING)
0.290
0.400
0.265 ±0.035 15X
0.10 M Z X Y
0.05 M Z
0.200 ±0.030
0.540 ±0.050
RECOMMENDED LAND PATTERN
SIDE VIEW
NOTES:
1. Dimensions and tolerance per ASME Y 14.5M - 1994.
2. Dimension is measured at the maximum bump diameter
parallel to primary datum Z .
3. Primary datum Z and seating plane are defined by the spherical
crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
5. There shall be a minimum clearance of 0.10mm between
the edge of the bump and the body edge.
1