PRELIMINARY ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER General Description Features The ICS853S024 is a low skew, 1-to-24 Differential-to-3.3V, 2.5V LVPECL Fanout Buffer and HiPerClockS™ a member of theHiPerClockS™ family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The ICS853S024 is characterized to operate from either a 3.3V or a 2.5V power supply. Guaranteed output skew characteristics make the ICS853S024 ideal for those clock distribution applications demanding well defined performance and repeatability. • • • Twenty four LVPECL outputs. • • Maximum output frequency: >1.5GHz • • • • • • Output skew: 25ps (typical) ICS One differential clock input pair Differential input clock (CLK, nCLK) can accept the following signaling levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL Translates any single ended input signal to 3.3V/ 2.5V LVPECL levels with resistor bias on nCLK input tR / tF: 180ps (typical) Additive phase jitter, RMS: 0.111ps (typical) @ 312.5MHz Full 3.3V or 2.5V supply voltage 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) packages. . Block Diagram VEE Q20 nQ19 Q19 nQ18 Q18 VCC nQ21 Q21 nQ20 Q0:Q23 Q23 nQ22 Q22 nQ0:nQ23 VCC VEE Q0 nQ0 Q1 nQ1 Q2 nQ2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 3 46 4 45 ICS853S024 5 44 64-Lead TQFP, EPad 6 43 10mm x 10mm x 1mm 7 42 8 41 package body 9 40 Y Package 10 39 Top View 11 38 12 37 13 36 35 14 nCLK CLK nQ17 Q17 nQ16 Q16 nQ15 Q15 nQ14 Q14 nQ13 Q13 nQ12 Q12 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCC VCC VEE VCC Q6 Q3 nQ3 Q4 nQ4 Q5 nQ5 VEE VCC 1 2 VEE 24 nQ6 Q7 nQ7 Q8 nQ8 Q9 nQ9 Q10 nQ10 Q11 nQ11 VCC nCLK Pullup 24 VCC VCC nQ23 CLK Pulldown Pin Assignment The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. LOW SKEW LVPECL FANOUT BUFFER 1 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Table 1. Pin Descriptions Number Name Type Description 1, 16, 18, 31, 33, 34, 50, 63, 64 VCC Power Power supply pins. 2, 15, 17, 32, 49 VEE Power Negative supply pins. 3, 4 Q0, nQ0 Output Differential clock outputs. LVPECL interface levels. 5, 6 Q1, nQ1 Output Differential clock outputs. LVPECL interface levels. 7, 8 Q2, nQ2 Output Differential clock outputs. LVPECL interface levels. 9, 10 Q3, nQ3 Output Differential clock outputs. LVPECL interface levels. 11, 12 Q4, nQ4 Output Differential clock outputs. LVPECL interface levels. 13, 14 Q5, nQ5 Output Differential clock outputs. LVPECL interface levels. 19, 20 Q6, nQ6 Output Differential clock outputs. LVPECL interface levels. 21, 22 Q7, nQ7 Output Differential clock outputs. LVPECL interface levels. 23, 24 Q8, nQ8 Output Differential clock outputs. LVPECL interface levels. 25, 26 Q9, nQ9 Output Differential clock outputs. LVPECL interface levels. 27, 28 Q10, nQ10 Output Differential clock outputs. LVPECL interface levels. 29, 30 Q11, nQ11 Output Differential clock outputs. LVPECL interface levels. 35, 36 Q12, nQ12 Output Differential clock outputs. LVPECL interface levels. 37, 38 Q13, nQ13 Output Differential clock outputs. LVPECL interface levels. 39, 40 Q14, nQ14 Output Differential clock outputs. LVPECL interface levels. 41, 42 Q15, nQ15 Output Differential clock outputs. LVPECL interface levels. 43, 44 Q16, nQ16 Output Differential clock outputs. LVPECL interface levels. 45, 46 Q17, nQ17 Output Differential clock outputs. LVPECL interface levels. 47 CLK Input Pulldown Non-inverting differential clock input. Input Pullup/ Pulldown Inverting differential clock input. VCC/2 default when left floating. 48 nCLK NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 50 kΩ 50 kΩ RPULLDOWN Input Pulldown Resistor LOW SKEW LVPECL FANOUT BUFFER 2 Minimum Typical Maximum Units ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 32.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 3A. LVPECL Power Supply DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VCC Core Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 200 mA NOTE 1: Output terminated with 50Ω to VCC / 2. See Parameter Measurement Information Section. Table 3B. Differential DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units CLK 150 µA nCLK 150 µA CLK -5 µA nCLK -150 µA 0.15 1.3 V VEE + 0.5 VCC – 0.85 V Maximum Units NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 3C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.9 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC – 2V. LOW SKEW LVPECL FANOUT BUFFER 3 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Table 3D. LVPECL DC Characteristics, VCC = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC – 1.4 VCC – 0.9 V VCC – 2.0 VCC – 1.5 V 0.4 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC – 2V. AC Electrical Characteristics Table 4. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Parameter Symbol fMAX Output Frequency tPD Propagation Delay; NOTE 1 tjit(φ) Additive Phase Jitter, RMS; NOTE 2 tsk(o) Output Skew; NOTE 3, 4 tsk(pp) Part-to-Part Skew; NOTE 4, 5 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units 1.9 GHz 600 ps 156.25 MHz, Integration Range: 12kHz – 20MHz 0.149 ps 312.5 MHz, Integration Range: 12kHz – 20MHz 0.111 ps 1GHz, Integration Range: 12kHz – 20MHz 0.44 ps 20% to 80% 25 ps TBD ps 180 ps 50 % All parameters are measured at f ≤ 1GHz, unless otherwise noted. Special thermal considerations may be required. See Applications Section. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Measured on Aeroflex PN9000. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Measured at the output differential cross points. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points. LOW SKEW LVPECL FANOUT BUFFER 4 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Parameter Measurement Information 2V 2V VCC Qx SCOPE VCC LVPECL Qx SCOPE LVPECL nQx nQx VEE VEE -1.3V ± 0.165V -0.5V ± 0.125V 3.3V LVPECL Output Load AC Test Circuit 2.5V LVPECL Output Load AC Test Circuit VCC nQx Qx nCLK V Cross Points PP V nQy CMR CLK Qy tsk(o) VEE Differential Input Level Output Skew Par t 1 nCLK nQx CLK Qx nQy nQ0:nQ21 Par t 2 Q0:Q21 Qy tPD tsk(pp) Part-to-Part Skew LOW SKEW LVPECL FANOUT BUFFER Propagation Delay 5 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Parameter Measurement Information, continued nQ0:nQ21 Q0:Q21 80% 80% t PW t odc = VSW I N G PERIOD t PW Clock Outputs 20% 20% x 100% tF tR t PERIOD Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 1. Single-Ended Signal Driving Differential Input LOW SKEW LVPECL FANOUT BUFFER 6 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK HiPerClockS Input LVHSTL R1 50 IDT HiPerClockS LVHSTL Driver HiPerClockS Input LVPECL R2 50 R1 50 R2 50 R2 50 Figure 2B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100 Zo = 50Ω nCLK HiPerClockS Input LVPECL R1 84 R2 84 Receiver Figure 2D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 2C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V nCLK Zo = 50Ω LVDS 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω Figure 2F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 2E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver LOW SKEW LVPECL FANOUT BUFFER 7 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK Inputs LVPECL Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FIN FOUT Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω Figure 3A. 3.3V LVPECL Output Termination LOW SKEW LVPECL FANOUT BUFFER 125Ω 84Ω Figure 3B. 3.3V LVPECL Output Termination 8 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Termination for 2.5V LVPECL Outputs ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250 R3 250 50Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 4A. 2.5V LVPECL Driver Termination Example Figure 4B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 4C. 2.5V LVPECL Driver Termination Example LOW SKEW LVPECL FANOUT BUFFER 9 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER PIN LAND PATTERN (GROUND PAD) SOLDER PIN PAD Figure 5. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) LOW SKEW LVPECL FANOUT BUFFER 10 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Power Considerations This section provides information on power dissipation and junction temperature for the ICS853S024. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853S024 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 200mA = 693mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 24 * 30mW = 720mW Total Power_MAX (3.465V, with all outputs switching) = 693W + 720mW = 1.413W 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming 0 air flow and a multi-layer board, the appropriate value is 32.5°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 1.413 W * 32.5°C/W = 115.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 5. Thermal Resistance θJA for 64 Lead TQFP, EPad, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards LOW SKEW LVPECL FANOUT BUFFER 0 1 2.5 32.5°C/W 26.6°C/W 25.1°C/W 11 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW LOW SKEW LVPECL FANOUT BUFFER 12 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Reliability Information Table 6. θJA vs. Air Flow Table for a 64 Lead TQFP, E-Pad θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 32.5°C/W 26.6°C/W 25.1°C/W Transistor Count The transistor count for ICS853S024 is: 8336 LOW SKEW LVPECL FANOUT BUFFER 13 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Package Outline and Package Dimensions Package Outline - Y Suffix for 64 Lead TQFP, E-Pad -HD VERSION EXPOSED PAD DOWN Table 7. Package Dimensions for 64 Lead TQFP, E-Pad Symbol N A A1 A2 b c D&E D1 & E1 D2 & E2 D3 & E3 e L θ ccc JEDEC Variation: ACD All Dimensions in Millimeters Minimum Nominal Maximum 64 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 0.20 12.00 Basic 10.00 Basic 7.50 Ref. 4.5 5.0 5.5 0.50 Basic 0.45 0.60 0.75 0° 7° 0.08 Reference Document: JEDEC Publication 95, MS-026 LOW SKEW LVPECL FANOUT BUFFER 14 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Ordering Information Table 7. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 853S024AYLF ICS853S024AYLF Lead-Free, 64 Lead TQFP, E-Pad Tray 0°C to +70°C 853S024AYLFT ICS853S024AYLF Lead-Free, 64 Lead TQFP, E-Pad 500 Tape & Reel 0°C to +70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. LOW SKEW LVPECL FANOUT BUFFER 15 ICS853S024AY REV. A APRIL 30, 2008 ICS853S024 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER PRELIMINARY Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA