Application Note, V1.3, May 2007 ICE1PCS01 ICE1PCS01 Based Boost Type CCM PFC Design Guide − Control Loop Modeling Power Management & Supply N e v e r s t o p t h i n k i n g . Edition 2007-05-23 Published by Infineon Technologies Asia Pacific, 168 Kallang Way, 349253 Singapore, Singapore © Infineon Technologies AP 2005. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. ICE1PCS01 Revision History: Previous Version: Page 2007-05 V1.3 none Subjects (major changes since last revision) ICE1PCS01 Based Boost Type CCM PFC Design Guide − Control Loop Modeling: License to Infineon Technologies Asia Pacific Pte Ltd Author(s) Luo Junyang Liu Jianwei Jeoh Meng Kiat We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mailto:[email protected] ANP0013 ICE1PCS01 Table of Contents Page 1 Introduction.................................................................................................................................5 2 2.1 2.2 How to achieve PFC function without sinusoidal reference sensing .....................................7 Boost converter modeling .............................................................................................................7 PFC IC control principle with boost topology.................................................................................8 3 3.1 3.2 3.3 3.4 3.5 Current Loop Regulation and Transfer Function .....................................................................9 Current Averaging Circuit .............................................................................................................9 PWM comparator block ..............................................................................................................10 Boost converter stage.................................................................................................................10 Open loop transfer function gain for current loop ........................................................................11 Steady state solution of IL ...........................................................................................................11 4 4.1 4.1.1 4.1.2 4.2 4.3 4.4 4.5 4.6 4.7 Voltage Loop Compensation ...................................................................................................12 Boost converter output stage G3(s).............................................................................................12 ∆Vout / ∆Iout ..................................................................................................................................12 ∆Iout / ∆IL_rms ................................................................................................................................13 Small signal transfer function of ∆Vout/∆(M1M2) for voltage loop analysis ....................................14 Nonlinear block GNON(s)..............................................................................................................14 Error Amplifier compensation G1(s) ............................................................................................15 Feedback G4(s)...........................................................................................................................16 Overall Open Loop Transfer Function GV(s) ...............................................................................17 Enhance dynamic response........................................................................................................17 5 5.1 5.2 5.3 5.4 Design Example ........................................................................................................................19 Vcomp and M1, M2 value at full load condition...........................................................................19 Current Averaging Circuit ...........................................................................................................21 Current Loop Regulation.............................................................................................................21 Voltage Loop Regulation ............................................................................................................23 Application Note 4 2007-05-23 ICE1PCS01 Abstract A new continuous conduction mode (CCM) PFC controller, named ICE1PCS01, is developed based on a new control scheme. Compared to the conventional PFC solution, the new IC does not need the direct sinewave sensing reference signal from the AC mains. Average current control is implemented to achieve the unity power factor. This application note provides a model and a tool for evaluating and improving the control loop characteristics of ICE1PCS01-based PFC pre-regulators in boost topology. The goal is not only to ensure a narrow bandwidth in order to achieve a high Power Factor, but also to have enough phase margin so as to make sure the system is stable over a large range of operating conditions. The design example is demonstrated as well. 1 Introduction Traditional diode rectifiers used in front of the electronic equipment draw pulsed current from the utility line, which deteriorates the line voltage, produce radiated and conducted electromagnetic interference, leads to poor utilization of the capacity of the power sources. In compliance with IEC 61000-3-2 harmonic regulation, active power factor correction (PFC) circuit is getting more and more attention in recent years. For low power up to 200W, discontinuous conduction mode (DCM) PFC is popular due to its lower cost. Furthermore, there is only one control loop, i.e. voltage loop, in its transferring control blocks. The design is easy and simple for DCM operation. However, due to its inherent high current ripple, DCM is seldom to be used for high power applications. In high power applications, continuous conduction mode (CCM) PFC is more attractive. V, I OUT I IL IIN DCM operation CCM operation Figure 1 DCM and CCM PFC principle In the conventional CCM topology, there are two control loops called voltage loop and current loop in its transfer function. Because of this, the control circuit of CCM is complicated and the Pin count of CCM PFC controllers is often high. New CCM PFC controller, named ICE1PCS01, is developed to simplified and cost down the design. It has only 8 pins. Moreover, numerous protection features are integrated according to Failure Mode Effect Analysis (FMEA). The typical application of the new PFC controller, named ICE1PCS01, is shown in Figure 2. It has only 8 pins and there is no direct sin-wave sensing signal fed into the IC. Application Note 5 2007-05-23 ICE1PCS01 Rectifier EMI Filter L1 COUT R1 VOUT=400VDC T1 R2 RSENSE VIN=85V ...265V AC R3 ISENSE Auxiliary Supply GATE ICE1PCS01 VCC ICOMP FREQ RFREQ C1 Figure 2 GND VSENSE VCOMP R4 C2 C3 Typical application circuit of ICE1PCS01 In this application note, the control loop compensation design of ICE1PCS01 based boost topology CCM PFC is described in detail. Application Note 6 2007-05-23 ICE1PCS01 2 How to achieve PFC function without sinusoidal reference sensing 2.1 Boost converter modeling Figure 3 shows the inductor current waveform for boost converter operating in continuous conduction mode. iL diL I0 ton toff TSW Figure 3 inductor current waveform of boost converter operating in CCM mode assuming Vin is boost converter input DC voltage, Vout is the boost converter output voltage, L is the boost choke inductance, ton is the on time duration in one switching cycle, toff is the off time duration in one switching cycle, doff is the off time duty cycle and Tsw is the time duration in one switching cycle. During “on” interval, diL Vin = dt L (1) During “off” interval, diL Vin − Vout = dt L (2) And then the boost inductor current variation after one switching cycle is: diL = Vin − Vout ⋅ d off Vin V −V ⋅ TSW ⋅ ton + in out ⋅ toff = L L L (3) The instant boost inductor current after n switching cycle is: iL _ n = iL _ n −1 + Vin _ n − Vout _ n ⋅ d off _ n Application Note L ⋅ TSW (4) 7 2007-05-23 ICE1PCS01 2.2 PFC IC control principle with boost topology PFC IC control block is inserted in boost converter as shown in Figure 4. Vin iL _ n doff Figure 4 Boost converter Vin _ n − Vout _ n ⋅ d off _ n = iL _ n−1 + ⋅ TSW L iL IC PWM modulation doff=K*iL PFC current loop principle IC senses boost inductor average current, and calculate the off duty cycle to be proportional to inductor current, and then send such off duty cycle back to boost converter. The negative feedback loop can be seen from Figure 4. A small disturb increasing on iL will result in a little bit increasing on off duty cycle. The increasing off duty cycle will lead to decreasing of iL after processing by boost converter. In the stead state, (5) Vin = Vout ⋅ d off = Vout ⋅ K ⋅ iL Where, K is the modulation gain defined by IC. It can be seen that boost inductor current shape follows AC input voltage and it is how PFC function to be achieved. In the following sections, detail mathematical analysis of current loop and voltage loop will be described and the transfer function for each block is given in order to design IC external compensation network components. Application Note 8 2007-05-23 ICE1PCS01 3 Current Loop Regulation and Transfer Function The detail block diagram of current loop for ICE1PCS01 is shown in the Figure 5. The boost converter stage Kboost is elaborated in S-plane. Vin Vout M2 PWM Comparator Kc(S) Doff - X + iL 1/sL Boost Converter Power Stage Kboost(s) Vicomp Current Averaging Kave(S) M1 Figure 5 3.1 Block diagram of current loop Current Averaging Circuit IC sense the boost inductor current via shunt resistor Rsense as shown in Figure 2. The sensing signal is sent to Isense Pin. As the voltage in Isense Pin is negative signal together with switching ripple, IC need to do signal averaging and convert the polarity to positive for following PWM modulation blocks. The output of averaging block is Vicomp voltage at Icomp Pin. the block diagram of current averaging block is shown in Figure 6. To PWM comparator ISENSE Current Mirror 1:1 R7 7k ICOMP Current averaging circuit Cicomp I1=Vicomp/R501 IM=I1*M1 Multiplier OTA2 +/-50uA 1mS R501 49k M1 Offset_low load S2 5V Fault Figure 6 current averaging block diagram The transfer function of averaging circuit block can be derived as below. Application Note 9 2007-05-23 ICE1PCS01 K AVE ( s ) = Vicomp iL K 1 Rsense M1 = K 1C icomp 1+ s ⋅ M 1 g OTA 2 (6) where, K1 is a ratio between R501 and R7 which is equal to 7, Cicomp is the capacitor at Icomp Pin, gOTA2 is the trans-conductance of the error amplifier of OTA2 for current averaging, typical 1.1mS as shown in Datasheet, M1 is the variable controlled by voltage loop. The function of the averaging circuit is to filter out the switching current ripple. So the corner frequency of the averaging circuit fAVE must be lower than the switching frequency fSW. Then, C icomp ≥ 3.2 g OTA2 M 1 K 1 ⋅ 2πf AVE (7) PWM comparator block The averaged Vicomp signal is sent to PWM comparator block and compared with internal triangular ramp signal to derive duty cycle. The timing diagram of this block is shown in Figure 7. Ramp Vicomp PWM Comparator To PWM logic and gate driver block C1 Vicomp Gate drive From protection logic Vramp=M2*Kfq Oscillator Tosc Figure 7 The block diagram and timing sequence of PWM comparator block The operating principle is explained as following. Gate output is in “low” state in the beginning of the each cycle. Gate output is turned to “high” at the intersection of the triangular ramp signal and Vicomp signal. Gate output is turned to “low” by oscillator synchronous signal. Based on the operating principle, the transfer function of KC(s) is: K C (s) = d off Vicomp = 1 K FQ M 2 (8) Where, KFQ is a design constant which is equal to 9.183, M2 is the variable controlled by voltage loop. 3.3 Boost converter stage The transfer function of boost converter stage KBoost(s) can be obtain via State-Space Averaging method. Combining equation (1) and (2) by state –space averaging, Application Note 10 2007-05-23 ICE1PCS01 Vin − Vout d off V − Vout di L Vin d on + in d off = = dt L L L (9) Make Laplace transformation for equation (9) with assuming Vin and Vout are constant for current loop analysis, i L ( s ) = (Vin − Vout d off ( s )) 1 sL (10) The equation (10) has been described in current loop block diagram in Figure 5. Although Vin is not physically sensed by circuit, the input sinusoidal signal is presented in transfer functions only if boost topology is applied. 3.4 Open loop transfer function gain for current loop The open loop gain of current regulation loop is: K1 RsenseVout K FQ M 1 M 2 L V GC ( s ) = K AVE ( s ) K C ( s ) out = K1C icomp sL ) s (1 + s ⋅ M 1 g OTA2 (11) The selected Cicomp must also meet the requirement that the cross over frequency of the current loop fC is much lower than the switching frequency fSW. 3.5 Steady state solution of IL Solving the current loop in Figure 5, i L ( s ) = (Vin − Vout d off ( s )) 1 1 = (Vin − Vout K C ( s ) K AVE ( s )i L ( s )) sL sL Vin Vin sL sL = i L (s) = Vout K C ( s ) K AVE ( s ) 1 + GC ( s ) 1+ sL (12) For AC line frequency which is much lower than fC, then GC(s)>>1, K FQ M 1 M 2Vin Vin Vin K1 RsenseVout sL i L (s) = ≈ sL = K1Cicomp 1 + G C ( s ) GC ( s ) 1+ s ⋅ M 1 g OTA 2 (13) For AC line frequency which is also much lower than fAVE, then the steady state IL can be derived as IL = K FQ M 1 M 2Vin (14) K1 RsenseVout from the above steady state solution of IL, it can be seen that the choke current IL is always following input voltage Vin. This is how PFC function is achieved. Application Note 11 2007-05-23 ICE1PCS01 4 Voltage Loop Compensation The control loop block diagram for ICE1PCS01 based CCM PFC is shown in Figure 8 and Figure 9. There are four blocks in the loop. IC PWM Modulator G2(s) has been discussed in above Section 3. the rest of them are Error Amplifier G1(s), nonlinear block GNON(s), boost converter output stage G3(s) and Feedback Sensing G4(s). Vin Vcomp_DC 0V Vref + - Error Amplifier G1(s) Vcomp Nonlinear block GNON(s) M1M2 PWM Modulator G2(s) Vout Boost converter output Stage G3(s) iL 400V Vsense 5V Feedback G4(s) Figure 8 Large signal modeling of voltage loop PWM modulation G2(s) + ∆Vsense Voltage loop Error Amplifier G1(s) ∆Vcomp Nonlinear GNON(s) ∆ ( M 1M 2 ) Output Stage G3(s) ∆I L _ rms I L _ rms M 1M 2 + - Vinrms Vout _ AVE ∆I out Output Stage 1 sCout ∆Vout I L _ rms Vout _ AVE Feedback Figure 9 4.1 Small signal modeling of voltage loop Boost converter output stage G3(s) Boost converter output stage is described as influencing of variation on iL to bulk output voltage Vout. The transfer function of power stage, G3(s), is separated to two stages as: G3 ( s ) = ∆Vout ∆Vout ∆I out = ⋅ ∆I L _ rms ∆I out ∆I L _ rms (15) where Vout is the DC output voltage, Iout the DC output current and IL_rms is the boost inductor current. 4.1.1 ∆Vout / ∆Iout Under the above assumption, the power stage can be modeled as illustrated in Figure 10: a controlled current source (with a shunt resistor Re) that drives the output bulk capacitor Cout and the load resistance Rout (= Vout / Iout). The zero due to the ESR associated with Cout is far beyond the crossover frequency thus it is neglected. Application Note 12 2007-05-23 ICE1PCS01 Iout Figure 10 Re Cout Rout Vout Power stage modeling A few algebraic manipulations would show that the shunt resistor Re always equals the DC load resistance Rout, thus it changes depending on the power delivered by the system. There are two kinds of load in the application. Two cases will give a different result in case of resistive load or constant power load. For purely resistive load, the AC load resistance equals Ro. In case of constant power load like additional isolated PWM DC/DC converter, the AC load resistance is equal to -Ro (if the DC bus decreases, the current demanded of the PFC increases. hence the negative sign is shown.). As a result, the parallel combination with Re tends to infinity and the two resistances cancel. The current source drives only the output capacitor. The result is summarized as below: ∆Vout ∆I out Rout R C 2(1 + s ⋅ out out ) = 2 1 sC out Resistive Load (16) Constant Power Load In this application note, the calculation is only carried out for constant power load situation 4.1.2 ∆Iout / ∆IL_rms The current source Iout can be characterized with the following considerations as shown in Figure 11. The low frequency component of the boost diode current is found by averaging the discharge portion of the inductor current over a given switching cycle. The low frequency current, averaged over a mains half-cycle yields the DC output current Iout: IL_PK iL idiode IOUT Figure 11 Application Note The simplification and characterization for Iout / IL_rms 13 2007-05-23 ICE1PCS01 I out = 1 π π∫ 0 2Vinrms I L _ rms (1 − Don ) I L _ PK Sinαdα = πVout _ AVE π ∫ 0 ( Sinα ) 2 dα = Vinrms I L _ rms Vout _ AVE (17) So, V ∆I out = inrms ∆I L _ rms Vout _ AVE (18) where, Don is the switch duty cycle; α is the instantaneous phase angle of the mains voltage, Vinrms is the input RMS voltage value, IL_PK is choke current sinewave peak value and Vout_AVE is the averaging bulk DC output voltage. In case of constant power load, the transfer function of G3(s) is: G3 ( s ) = V ∆Vout ∆Vout ∆I out 1 = ⋅ = inrms ⋅ ∆I L _ rms ∆I out ∆I L _ rms Vout _ AVE sC out (19) Small signal transfer function of ∆Vout/∆(M1M2) for voltage loop analysis 4.2 There is a internal feedback from Vout to G2(s). this inner loop has to be solved to obtain the transfer function of ∆Vout/∆(M1M2). Rewrite the equation (14) at input voltage RMS point: I L _ rms = K FQ M 1 M 2Vinrms (20) K 1 RsenseVout making a perturbation on IL_rms, (M1M2), Vout, then ∆I L _ rms = I L _ rms M 1M 2 ∆( M 1 M 2 ) − I L _ rms Vout _ AVE ∆Vout (21) replacing ∆IL_rms by ∆Vout/G3(s) according to voltage loop block diagram, I L _ rms I L _ rms ∆Vout = ∆( M 1 M 2 ) − ∆Vout G3 ( s ) M 1 M 2 Vout _ AVE (22) then the transfer function of dVout/dVcomp is Vout _ AVE G 23 ( s ) = ∆Vout M 1M 2 = ∆( M 1 M 2 ) Vout _ AVE 2 C out = s +1 I L _ rmsVinrms 1 With f 23 = 3 2π K 1 RsenseVout _ AVE C out K FQ M 1 M 2Vinrms Vout _ AVE M 1M 2 (23) 3 K 1 RsenseVout _ AVE C out K FQ M 1 M 2Vinrms 2 s +1 , 2 Vout _ AVE G23 ( s) = 4.3 ∆Vout M 1M 2 = s ∆( M 1 M 2 ) 1+ 2πf 23 (24) Nonlinear block GNON(s) Application Note 14 2007-05-23 ICE1PCS01 The Vcomp voltage is sent to nonlinear gain block. The output of nonlinear is two internal variables, M1 and M2. The two variables are used to define boost choke current amplitude IL as in equation (14). The characteristic of nonlinear gain block is shown in Table 1 and Figure 12. The small signal gain between ∆(M1*M2) and ∆Vcomp can be derived as well at different operating point. Vcomp 0 1.5 1.85 2 2.5 3 3.5 4 4.5 5 5.5 5.6 6 6.5 7 M1 0.048 0.048 0.0517 0.0551 0.101 0.184 0.316 0.477 0.629 0.752 0.846 0.888 0.906 0.906 0.906 M2 1.330E-02 1.330E-02 1.920E-02 3.860E-02 1.790E-01 3.350E-01 5.080E-01 7.160E-01 9.830E-01 1.368E+00 1.879E+00 1.968E+00 1.982E+00 1.987E+00 1.987E+00 M1*M2 6.384E-04 6.384E-04 9.926E-04 2.127E-03 1.808E-02 6.164E-02 1.605E-01 3.415E-01 6.183E-01 1.029E+00 1.590E+00 1.748E+00 1.796E+00 1.800E+00 1.800E+00 Table 1 nonlinear block characteristic data M1 M2 M1*M2 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 Vcomp Figure 12 4.4 The characteristics of nonlinear block Error Amplifier compensation G1(s) The circuit of error amplifier compensation circuit is shown in Figure 13. The sensing voltage Vsense is compared to internal reference voltage 5V typical. The difference between Vsense and internal reference is sent to transconductance error amplifier and converted to a current source to charge or discharge the RC components in Vcomp Pin. Application Note 15 2007-05-23 ICE1PCS01 Vcomp Vsense OTA1 5V R4 C2 Figure 13 C3 Error Amplifier compensation G1(s) The transfer function is: G1 ( s) = ∆Vcomp ∆Vsense = ∆Vcomp ∆I OTA1 = ⋅ ∆I OTA1 ∆Vsense 1 + sR4 C 2 ⋅ g OTA1 R4 C 2 C 3 (C 2 + C 3 ) s (1 + s ) C 2 + C3 (25) where, gOTA1 is the trans-conductance of OTA1, 42uS typically for ICE1PCS01. With f CZ = 1 and f CP = 2πR4 C 2 1 , R4 C 2 C 3 2π C 2 + C3 g OTA1 (1 + s ) 2πf CZ G1 ( s) = (C 2 + C3 ) s (1 + s ) 2πf CP (26) The pole and zero are to regulate the overall voltage loop with the cross-over frequency below 100Hz and create the phase margin for the loop stability. 4.5 Feedback G4(s) The Feedback block is a simple voltage divider to monitor the bulk capacitor output voltage. The circuit is shown in Figure 14. Vout G4 ( s) = ∆Vsense R2 = R1 + R2 ∆Vout R1 (27) Vsense R2 Figure 14 Application Note 16 bulk voltage sensing divider 2007-05-23 ICE1PCS01 4.6 Overall Open Loop Transfer Function GV(s) With combining all of the blocks above, the overall open loop gain for voltage loop is equal to: GV ( s ) = G1 ( s )G NON ( s )G23 ( s )G4 ( s ) (28) Due to PF requirement, inherent PFC dynamic voltage loop compensation is always implemented with low bandwidth in order not to make the response for 2*fL ripple. For example, for 50Hz AC line input, PFC voltage loop bandwidth is normally set below 20Hz. The compensation circuit R4, C2 and C3 are used to optimize the loop gain and phase margin. 4.7 Enhance dynamic response As mentioned in Section 4.6, the inherent low bandwidth of voltage loop in PFC application will lead to slow response in case of sudden load step and result in large output overshoot or drop. Enhance dynamic response feature is integrated in ICE1PCS01 to have a fast response in the case of load step. The voltage loop with including enhance dynamic response block is shown in Figure 15. Vin Vcomp_DC 0V Vref + - Error Amplifier G1(s) Vcomp + +/- Nonlinear block GNON(s) M1M2 PWM Modulator G2(s) iL Boost converter output Stage G3(s) Vout 400V Vsense 5V Enhance dynamic Feedback G4(s) Figure 15 voltage loop block diagram including enhance dynamic response When Vsense voltage variation is within -5% to +5% of nominal value, there is no function of enhance dynamic response block. However, when Vsense variation is out of such +/-5% range, enhance block will add offset voltage on top of Vcomp voltage to influence the current amplitude. For Vsense variation < -5% of nominal value, the offset voltage is +2V maximum. For Vsense variation > +5% of nominal value, the offset voltage is -4V minimum. The timing diagram of enhance dynamic response operation is shown in Figure 16 with sudden load jump situation. It can be seen that during enhance dynamic operation, the high current of boost choke is delivered for fast response. Within half sinusoidal period, when Vsense operating around the boundary of -5% threshold, the first part of boost choke current follows high amplitude profile due to enhance mode offset and the rest of boost choke current come back to low amplitude profile without enhance mode offset. When Vsense voltage is pulled back within +/-5% range, enhance dynamic offset disappear and boost choke current waveform will stay as perfect sinusoidal shape. Application Note 17 2007-05-23 ICE1PCS01 Normal enhance Normal Vin Iin Vcomp 0 Pin Pin_ave 0 Ichg Ichg_ave 0 Vout Vout_ave nominal - 5% Figure 16 timing diagram for enhance dynamic operation Application Note 18 2007-05-23 ICE1PCS01 5 Design Example Assuming a 300W application with universal input AC voltage 85~265VAC, constant power load efficiency=88% Vout=400VDC Cout=220uF/450V fSW=125kHz Rsense=0.1ohm Boost choke inductance L=1.2mH Vsense divider: R1=390kohm*2=780kohm, R2=10kohm 5.1 Vcomp and M1, M2 value at full load condition (1) 85VAC: RMS AC input current under full load: I L _ rms _ 85 = Pout 300 = = 4.01A η ⋅ Vinrms _ 85 0.88 ⋅ 85 (29) From equation (14), M 1M 2 85VAC = I L _ rms _ 85 K1 RsenseVout K FQVinrms _ 85 = 4.01 ⋅ 7 ⋅ 0.1 ⋅ 400 = 1.438 9.183 ⋅ 85 (30) From table 1 and Figure 12, it can be obtained Vcomp M1 M2 M1*M2 5 0.752 1.368E+00 1.029E+00 5.5 0.846 1.879E+00 1.590E+00 With Linear approximation: Vcomp _ 85 = Vcomp _ 1 + Vcomp _ 85 = 5 + M 1M 2 85VAC − M 1M 2 Vcomp _ 1 M 1 M 2 Vcomp _ 2 − M 1 M 2 Vcomp _ 1 ⋅ (Vcomp _ 2 − Vcomp _ 1 ) 1.438 − 1.029 ⋅ (5.5 − 5) = 5.365V 1.59 − 1.029 M 1 85VAC = M 1 _ 1 + M 1_ 2 − M 1_1 Vcomp _ 2 − Vcomp _ 1 ⋅ (Vcomp _ 85 − Vcomp _ 1 ) M 1 85VAC 0.846 − 0.752 = 0.752 + ⋅ (5.365 − 5) = 0.821 5.5 − 5 M2 = M 2 _1 + M2 85VAC 85VAC (31) M 2 _ 2 − M 2 _1 Vcomp _ 2 − Vcomp _ 1 (32) ⋅ (Vcomp _ 85 − Vcomp _ 1 ) 1.879 − 1.368 = 1.368 + ⋅ (5.365 − 5) = 1.741 5.5 − 5 (33) The small signal gain of nonlinear block is Application Note 19 2007-05-23 ICE1PCS01 M 1 M 2 Vcomp _ 2 − M 1 M 2 Vcomp _ 1 G NON ( s ) 85VAC = Vcomp _ 2 − Vcomp _ 1 = 1.590 − 1.029 = 1.122 5.5 − 5 (34) The inherent pole of f23 is f 23 85VAC 1 3 K1 RsenseVout _ AVE C out = 2π = 1.5406Hz K FQ ⋅ ( M 1 M 2 ) 85VAC ⋅ Vinrms _ 85 (35) 2 (2) 265VAC RMS AC input current under full load: I L _ rms _ 265 = Pout 300 = = 1.286 A η ⋅ Vinrms _ 265 0.88 ⋅ 265 (36) From equation (14), M 1M 2 265VAC = I L _ rms _ 265 K1 RsenseVout K FQVinrms _ 265 = 1.286 ⋅ 7 ⋅ 0.1 ⋅ 400 = 0.148 9.183 ⋅ 265 (37) From table 1 and Figure 12, it can be obtained Vcomp M1 M2 M1*M2 3 0.184 3.350E-01 6.164E-02 3.5 0.316 5.080E-01 1.605E-01 With Linear approximation: Vcomp _ 265 = Vcomp _ 1 + Vcomp _ 265 = 3 + M1 M1 M2 M2 265VAC 265VAC 265VAC 265VAC M 1M 2 265VAC − M 1M 2 Vcomp _ 1 M 1 M 2 Vcomp _ 2 − M 1 M 2 Vcomp _ 1 ⋅ (Vcomp _ 2 − Vcomp _ 1 ) (38) 0.148 − 0.06164 ⋅ (3.5 − 3) = 3.437V 0.1605 − 0.06164 = M 1_1 + M 1_ 2 − M 1_1 Vcomp _ 2 − Vcomp _ 1 ⋅ (Vcomp _ 265 − Vcomp _ 1 ) 0.316 − 0.184 = 0.184 + ⋅ (3.437 − 3) = 0.299 3.5 − 3 = M 2 _1 + M 2 _ 2 − M 2 _1 Vcomp _ 2 − Vcomp _ 1 (39) ⋅ (Vcomp _ 265 − Vcomp _ 1 ) 0.508 − 0.335 = 0.335 + ⋅ (3.437 − 3) = 0.486 3.5 − 3 (40) The small signal gain of nonlinear block is G NON ( s ) 265VAC = M 1 M 2 Vcomp _ 2 − M 1 M 2 Vcomp _ 2 − Vcomp _ 1 Vcomp _ 1 = 0.1605 − 0.06164 = 0.198 3.5 − 3 (41) The inherent pole of f23 is Application Note 20 2007-05-23 ICE1PCS01 f 23 265VAC 1 = 2π 5.2 = 1.5412 Hz 3 K1 RsenseVout _ AVE C out K FQ ⋅ ( M 1 M 2 ) 265VAC ⋅ Vinrms _ 265 (42) 2 Current Averaging Circuit With gOTA2=1.1mS from Datasheet, M1@85VAC, and assuming fAVE=24kHz which is 5 times less than switching frequency 125kHz, then C icomp ≥ g OTA2 M 1 85VAC K 1 ⋅ 2πf AVE = 1.1E − 3 ⋅ 0.821 = 0.86nF 7 ⋅ 2π ⋅ 24 E 3 (43) Select Cicomp=1nF 5.3 Current Loop Regulation Insert M1 and M2 value in equation (11). The amplitude and phase angle of GC(s) is shown in Figure 17 to verify the stability of current loop and the requirement of fC less than switching frequency. Application Note 21 2007-05-23 ICE1PCS01 100 85VAC & full load 265VAC & full load 50 Gain(db) 0 -50 -100 -150 0 10 1 10 2 10 3 4 10 10 5 10 6 10 7 10 f(HZ) -90 85VAC & full load 265VAC & full load -100 -110 Phase Angle -120 -130 -140 -150 -160 -170 -180 0 10 1 10 2 10 3 4 10 10 5 10 6 10 7 10 f(HZ) Figure 17 The bode plot and phase angle for current loop The cross over frequency and phase margin are 2kHz and 85º for 85VAC, and 11kHz and 35º for 265VAC. Application Note 22 2007-05-23 ICE1PCS01 5.4 Voltage Loop Regulation From the above sections, it can be obtained: G1 ( s) = ∆Vcomp ∆Vsense G NON ( s) = = g OTA1 (1 + s ) 2πf CZ (C 2 + C 3 ) s(1 + s ) 2πf CP (44) ∆( M 1 M 2 ) ∆Vcomp (45) Vout _ AVE G23 ( s) = G4 ( s) = ∆Vout M 1M 2 = s ∆( M 1 M 2 ) 1+ 2πf 23 (46) ∆Vsense R2 5 = = = 0.0125 ∆Vout R1 + R2 400 (47) The open loop gain for voltage loop is to times all above factors together as: GV ( s ) = G1 ( s )G NON ( s )G23 ( s )G4 ( s ) G1(s) is used to provide enough phase margin and also limit the bandwidth below 20HZ. R4, C2 and C3 can be chosen as required. fCZ normally select to be compensate the pole in G23(s). fCP normally select to be 40~70Hz in order to fast put down the gain amplitude and reject the high frequency interference. In this example f23 is equal to 1.5406Hz at 85VAC and full load and 1.5412Hz at 265VAC and full load respectively. So the initial target is: fCZ is chosen to be close to 1.5Hz, and fCP is chosen to be 50Hz. C2 and C3 is calculated to obtain Gv(s) cross over frequency around 10Hz. The gain amplitude of GNON*G23*G4 in 85VAC and full load is shown in Figure 18. It can be seen that at f=10Hz, the gain is about 4.52dB. So G1 should provide the gain +4.52dB at f=10Hz. Considering that C2>>C3 due to fcz<fcp and 10Hz>>1Hz=fCZ, then G1 (10 Hz ) = g OTA1 10 Hz 1Hz = +4.52dB C 2 ⋅ 2π ⋅ 10 Hz (48) 10 Hz 1Hz = 3.97 µF C 2 = 4.52 10 20 ⋅ 2π ⋅ 10 Hz 42 ⋅ 10 −6 ⋅ 3.97uF is not common for ceramic type capacitor. So select C2=1uF, then fCZ is recalculated as: Application Note 23 2007-05-23 ICE1PCS01 G1 (10 Hz ) = f CZ = g OTA1 1 + (10 Hz = +4.52dB 10 Hz 2 = 4.33Hz (49) 1µF ⋅ 10 4.52 20 ⋅ 2π ⋅ 10 Hz −1 42 ⋅ 10 −6 1 = 4.33Hz then 2πR4 C 2 1 = 36.8kΩ 2π ⋅ 4.33 Hz ⋅ C 2 select R4=33kΩ, and C3 = )2 C 2 ⋅ 2π ⋅ 10 Hz according to f CZ = R4 = f CZ f CP = (50) 1 1 ≈ = 50 Hz R4 C 2 C 3 2πR4 C 3 2π C 2 + C3 1 = 96.5nF 2π ⋅ 50 Hz ⋅ R4 (51) select C3=100nF The gain amplitude and phase angle of overall voltage loop GV(s) at 85VAC and 265VAC in full load condition is shown in Figure 18 and Figure 19. At 85VAC, the cross over frequency fV is around 8.5Hz and the phase margin is about 62º. At 265VAC, the cross over frequency fV is around 14Hz and the phase margin is about 63º. Application Note 24 2007-05-23 ICE1PCS01 60 Gv=G1*Gnon*G23*G4 Gnon*G23*G4 40 20 Gain(db) 0 -20 -40 -60 -80 -100 -120 -1 10 0 10 1 2 10 10 3 10 4 10 f(HZ) -90 Gv=G1*Gnon*G23*G4 -100 -110 Phase Angle -120 -130 -140 -150 -160 -170 -180 -1 10 0 10 1 2 10 10 3 10 4 10 f(HZ) Figure 18 Application Note the bode plot and phase angle for voltage loop at 85VAC and full load 25 2007-05-23 ICE1PCS01 60 Gv=G1*Gnon*G23*G4 Gnon*G23*G4 40 20 Gain(db) 0 -20 -40 -60 -80 -100 -120 -1 10 0 10 1 2 10 10 3 10 4 10 f(HZ) -90 Gv=G1*Gnon*G23*G4 -100 -110 Phase Angle -120 -130 -140 -150 -160 -170 -180 -1 10 0 10 1 2 10 10 3 10 4 10 f(HZ) Figure 19 Application Note The bode plot and phase angle for voltage loop at 265VAC and full load 26 2007-05-23 ICE1PCS01 References [1] Infineon Technologies: ICE1PCS01 - Standalone Power Factor Correction Controller in Continuous Conduction Mode; Preliminary datasheet; Infineon Technologies; Munich; Germany; Sept. 2002. [2] Luo Junyang, Jeoh Meng Kiat, Huang Heng Cheong, A New Continuous Conduction Mode PFC IC With Average Current Mode Control, PEDS 2003; pp. 1110-1114, Nov 2003. [3] Luo Junyang, Jeoh Meng Kiat, Yew Ming Lik, 300W CCM PFC Evaluation Board with ICE1PCS01, CoolMOS™ and SiC Diode thinQ!™, Application note, Infineon Technologies, Munich, Germany, Oct. 2003. Application Note 27 2007-05-23