ISL70001SRH Features The ISL70001SRH is a radiation hardened and SEE hardened high efficiency monolithic synchronous buck regulator with integrated MOSFETs. This single chip power solution operates over an input voltage range of 3V to 5.5V and provides a tightly regulated output voltage that is externally adjustable from 0.8V to ~85% of the input voltage. Output load current capacity is 6A for TJ < +145°C. • Electrically Screened to DSCC SMD 5962-09225 The ISL70001SRH utilizes peak current-mode control with integrated compensation and switches at a fixed frequency of 1MHz. Two ISL70001SRH devices can be synchronized 180° out-of-phase to reduce input RMS ripple current. These attributes reduce the number and size of external components required, while providing excellent output transient response. The internal synchronous power switches are optimized for high efficiency and good thermal performance. The chip features a comparator type enable input that provides flexibility. It can be used for simple digital on/off control or, alternately, can provide undervoltage lockout capability by precisely sensing the level of an external supply voltage using two external resistors. A power-good signal indicates when the output voltage is within ±11% typical of the nominal output voltage. Regulator start-up is controlled by an analog soft-start circuit, which can be adjusted from approximately 2ms to 200ms using an external capacitor. The ISL70001SRH incorporates fault protection for the regulator. The protection circuits include input undervoltage, output undervoltage and output overcurrent. High integration makes the ISL70001SRH an ideal choice to power many of today’s small form factor applications. Two devices can be synchronized to provide a complete power solution for large scale digital ICs, like field programmable gate arrays (FPGAs), that require separate core and I/O voltages. • QML Qualified per MIL-PRF-38535 Requirements • Full Mil-Temp Range Operation (TA = -55°C to +125°C) • Radiation Hardness - Total Dose [50-300rad(Si)/s] . . . 100krad(Si) min • SEE Hardness - SEL and SEB LETeff . . . . . . 86.4MeV/mg/cm2 min - SEFI X-section (LETeff = 86.4MeV/mg/cm2) 1.4 x 10-6 cm2 max - SET LETeff (< 1 Pulse Perturbation) 86.4MeV/mg/cm2 min • High Efficiency > 90% • Fixed 1MHz Operating Frequency • Operates from 3V to 5.5V Supply • ±1% Reference Voltage over Line, Load, Temperature and Radiation • Adjustable Output Voltage - Two External Resistors Set VOUT from 0.8V to ~85% of VIN • Excellent Dynamic Response • Bi-directional SYNC Pin Allows Two Devices to be Synchronized 180° Out-of-Phase • Device Enable with Comparator Type Input • Power-Good Output Voltage Monitor • Adjustable Analog Soft-Start • Input Undervoltage, Output Undervoltage and Output Overcurrent Protection • Starts Into Pre-Biased Load Applications*(see page 16) • FPGA, CPLD, DSP, CPU Core or I/O Voltages • Low-Voltage, High-Density Distributed Power Systems Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed in the Ordering Information Table on page 2 must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-09225. A link is provided on our website for downloading. December 15, 2009 FN6947.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL70001SRH Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator with Integrated MOSFETs ISL70001SRH AVDD AGND DVDD DGND EN Functional Block Diagram POWER-ON RESET (POR) PORSEL PVINx SS SLOPE COMPENSATION SOFT START EA FB CURRENT SENSE PWM CONTROL LOGIC GM GATE DRIVE LXx COMPENSATION PGNDx UV POWER-GOOD PGOOD REF PWM REFERENCE 0.6V TDI BIT TDO TRIM ZAP SYNC M/S Ordering Information ORDERING NUMBER PART NUMBER (Note 2) TEMP. RANGE (°C) PACKAGE 5962R0922501QXC ISL70001SRHQF (Note 1) -55 to +125 48 Ld CQFP (Pb-Free) 5962R0922501VXC ISL70001SRHVF (Note 1) -55 to +125 48 Ld CQFP (Pb-Free) 5962R0922501V9A ISL70001SRHVX -55 to +125 Die ISL70001SRHF/PROTO ISL70001SRHF/PROTO (Note 1) -55 to +125 48 Ld CQFP (Pb-Free) ISL70001SRHX/SAMPLE ISL70001SRHX/SAMPLE -55 to +125 Die NOTE: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70001SRH. For more information on MSL please see techbrief TB363. 2 FN6947.0 December 15, 2009 ISL70001SRH Pin Configuration M/S ZAP TDI TDO PGOOD SS DVDD PVIN3 PVIN2 PVIN2 LX2 PGND2 PGND2 PGND1 PVIN1 LX1 PGND1 PVIN1 SYNC ISL70001SRH (48 LD CQFP) TOP VIEW 7 6 5 4 3 2 1 48 47 46 45 4443 42 8 41 LX3 9 40 PGND3 10 39 11 38 12 13 37 PGND3 PGND4 PGND4 36 LX4 35 PVIN3 DVDD 14 DGND DGND 15 34 PVIN4 PVIN4 16 33 PVIN5 32 PVIN5 LX5 PGND5 PGND5 PGND6 PGND6 PVIN6 LX6 PVIN6 PORSEL FB EN 17 31 18 19 20 21 22 23 24 25 26 27 28 29 30 AVDD AGND REF AGND Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1, 2, 27, 28, 29, 30, 37, 38, 39, 40, 47, 48 PGNDx These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins directly to the ground plane. These pins should also connect to the negative terminals of the input and output capacitors. Locate the input and output capacitors as close as possible to the IC. 3, 26, 31, 36, 41, 46 LXx These pins are the outputs of the corresponding internal power blocks and should be connected to the output filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize voltage undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The Schottky diode should be located as close as possible to the IC. 4, 5, 24, 25, 32, 33, 34, 35, 42, 43, 44, 45 PVINx These pins are the power supply inputs to the corresponding internal power blocks. These pins must be connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly to PGNDx with ceramic capacitors located as close as possible to the IC. 6 SYNC This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives the SYNC input of another ISL70001SRH. When configured as an input (Slave Mode), this pin accepts the SYNC output from another ISL70001SRH or an external clock. Synchronization of the slave unit is 180° out-of-phase with respect to the master unit. If synchronizing to an external clock, the clock must be SEE hardened and the frequency must be within the range of 1MHz ±20%. 7 M/S This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to DGND. 8 ZAP This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND. 9 TDI This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND. 10 TDO This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND. 3 FN6947.0 December 15, 2009 ISL70001SRH Pin Descriptions (Continued) PIN NUMBER PIN NAME DESCRIPTION 11 PGOOD This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin to DGND with a 10nF ceramic capacitor to mitigate SEE. 12 SS This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output ramp time in accordance with Equation 1: t SS = C SS ⋅ V REF ⁄ I SS (EQ. 1) Where: tSS = Soft-start output ramp time CSS = Soft-start capacitor VREF = Reference voltage (0.6V typical) ISS = Soft-start charging current (23µA typical) Soft-start time is adjustable from approximately 2ms to 200ms. The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive. 13, 14 DVDD These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together at the IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. 15, 16 DGND These pins are the digital ground associated with the internal digital control circuitry. Connect these pins directly to the ground plane. 17, 18 AGND These pins are the analog ground associated with the internal analog control circuitry. Connect these pins directly to the ground plane. 19 AVDD This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. 20 REF This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or sinking) is available from this pin. 21 FB This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and from FB to AGND to adjust the output voltage in accordance with Equation 2: V OUT = V REF ⋅ [ 1 + ( R T ⁄ R B ) ] (EQ. 2) Where: VOUT = Output voltage VREF = Reference voltage (0.6V typical) RT = Top divider resistor (Must be 1kΩ) RB = Bottom divider resistor The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate SEE and to improve stability margins. 22 EN This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a 10nF ceramic capacitor to mitigate SEE. 23 PORSEL This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply voltages between 5V and 3.3V, connect this pin to DGND. 4 FN6947.0 December 15, 2009 ISL70001SRH Typical Application Schematic PVIN1 LX1 PVIN2 LX2 PVIN3 LX3 PVIN4 LX4 PVIN5 LX5 5V 100µF 1µF 1µF 1µH LX6 PVIN6 1 470µF 20V 3A DVDD ISL70001SRH 0V TO 5.5V DGND 10nF 1µF SYNC AGND REF EN 10nF 499Ω PGOOD AVDD VSENSE 4.7nF 1kΩ FB 1µF 1 1.8V 6A 220nF M/S PORSEL TDI SS TDO 100nF PGND6 PGND5 PGND4 PGND3 PGND2 PGND1 ZAP FIGURE 1. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION 5 FN6947.0 December 15, 2009 ISL70001SRH Typical Application Schematic (Continued) PVIN1 LX1 PVIN2 LX2 PVIN3 LX3 PVIN4 LX4 PVIN5 LX5 3.3V 100µF 1µF 1µF 1µH LX6 PVIN6 1 1.8V 6A 470µF 20V 3A DVDD 1kΩ FB 1µF ISL70001SRH 0V TO 5.5V DGND 1 10nF 1µF SYNC AGND REF EN 10nF 499Ω PGOOD AVDD VSENSE 4.7nF 220nF M/S PORSEL TDI SS TDO 100nF PGND6 PGND5 PGND4 PGND3 PGND2 PGND1 ZAP FIGURE 2. 3.3V INPUT SUPPLY VOLTAGE WITH SLAVE MODE SYNCHRONIZATION 6 FN6947.0 December 15, 2009 ISL70001SRH Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V; GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V, SYNC = LXx = Open Circuit; PGOOD is pulled up to VIN with a 1k resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 3) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Operating Supply Current VIN = 5.5V 40 mA VIN = 3.6V 25 mA VIN = 5.5V, EN = GND 6 mA VIN = 3.6V, EN = GND 3 mA 0.6 V 0 % 0 µA Oscillator Accuracy 1 MHz External Oscillator Range 1 MHz Shutdown Supply Current OUTPUT VOLTAGE Reference Voltage Tolerance Output Voltage Tolerance VOUT = 0.8V to 2.5V for VIN = 4.5V to 5.5V, VOUT = 0.8V to 2.5V for VIN = 3V to 3.6V, IOUT = 0A to 6A (Notes 4, 5) Feedback (FB) Input Leakage Current VIN = 5.5V, VFB = 0.6V PWM CONTROL LOGIC Minimum LXx On Time VIN = 5.5V, Test Mode 110 ns Minimum LXx Off Time VIN = 5.5V, Test Mode 40 ns Minimum LXx On Time VIN = 3V, Test Mode 150 ns Minimum LXx Off Time VIN = 3V, Test Mode 50 ns Master/Slave (M/S) Input Voltage Input High Threshold 1.3 V Input Low Threshold 1.2 V 0 µA Master/Slave (M/S) Input Leakage Current VIN = 5.5V, M/S = GND or VIN Synchronization (SYNC) Input Voltage Input High Threshold, M/S = GND 1.7 V Input Low Threshold, M/S = GND 1.5 V Synchronization (SYNC) Input Leakage Current VIN = 5.5V, M/S = GND, SYNC = GND or VIN 0 µA Synchronization (SYNC) Output Voltage VIN - VOH @ IOH = -1mA 0.15 V VOL@ IOL = 1mA 0.15 V Upper Device rDS(ON) VIN = 3V, 0.4A Per Power Block, Test Mode (Note 5) 215 mΩ Lower Device rDS(ON) VIN = 3V, 0.4A Per Power Block, Test Mode (Note 5) 146 mΩ LXx Output Leakage VIN = 5.5V, EN = LXx = GND, Single LXx Output 0 µA VIN = 5.5V, EN = GND, LXx = VIN, Single LXx Output 0 µA Deadtime Within a Single Power Block or between Power Blocks (Note 5) 5 ns Efficiency VIN = 3.3V, VOUT = 1.8V, IOUT = 3A 90 % VIN = 5V, VOUT = 2.5V, IOUT = 3A 92 % POWER BLOCKS 7 FN6947.0 December 15, 2009 ISL70001SRH Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V; GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V, SYNC = LXx = Open Circuit; PGOOD is pulled up to VIN with a 1k resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 3) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER-ON RESET POR Select (PORSEL) Input High Threshold 1.4 V Input Low Threshold 1.2 V 0 µA POR Select (PORSEL) Input Leakage Current VIN = 5.5V, PORSEL = GND or VIN VIN POR Rising Threshold, PORSEL = VIN 4.25 V Hysteresis, PORSEL = VIN 325 mV Rising Threshold, PORSEL = GND 2.8 V Hysteresis, PORSEL = GND 175 mV Enable (EN) Input Voltage Rising/Falling Threshold 0.6 V Enable (EN) Input Leakage Current VIN = 5.5V, EN = GND or VIN 0 µA Enable (EN) Sink Current EN = 0.3V 11 µA SS = GND 23 µA Soft-Start Discharge ON-Resistance 2.2 Ω Soft-Start Discharge Time 256 Clock Cycles SOFT-START Soft-Start Source Current POWER-GOOD SIGNAL Rising Threshold VFB as a % of VREF, Test Mode 111 % Rising Hysteresis VFB as a % of VREF, Test Mode 3.5 % Falling Threshold VFB as a % of VREF, Test Mode 89 % Falling Hysteresis VFB as a % of VREF, Test Mode 3.5 % Power-Good Drive VIN = 3V, PGOOD = 0.4V, EN = GND Power-Good Leakage VIN = PGOOD = 5.5V mA 0 µA PROTECTION FEATURES Undervoltage Monitor Undervoltage Trip Threshold VIN = 3V, VFB as a % of VREF, Test mode 75 % Undervoltage Recovery Threshold VIN = 3V, VFB as a % of VREF, Test mode 88 % Overcurrent Trip Level LX4 Power Block, Test Mode, (Note 6) 1.9 A Overcurrent or Short-Circuit Duty-Cycle VIN = 3V, SS interval = 200µs, Test Mode, Fault interval divided by hiccup interval 0.8 % Overcurrent Monitor NOTES: 3. Typical values shown are not guaranteed. 4. Limits do not include tolerance of external feedback resistors. The 0A to 6A output current range may be reduced by Minimum LXx On Time and Minimum LXx Off Time specifications. 5. Limits established by characterization or analysis and are not production tested. 6. During an output short-circuit, peak current through the power block(s) can continue to build beyond the overcurrent trip level by up to 3A. With all six power blocks connected, peak current through the power blocks and output inductor could reach (6 x 2.5A) + 3A = 18A. The output inductor must support this peak current without saturating. 8 FN6947.0 December 15, 2009 ISL70001SRH Functional Description The ISL70001SRH is a monolithic, fixed frequency, current-mode synchronous buck regulator with user configurable power blocks. Two ISL70001SRH devices can be used to provide a total DC/DC solution for FPGAs, CPLDs, DSPs and CPUs. PVIN1 LX1 PGND1 PVIN2 LX2 PGND2 POWER BLOCK 1 POWER BLOCK 6 POWER BLOCK 2 POWER BLOCK 5 PVIN6 LX6 PGND6 PVIN5 LX5 PGND5 pilot. If VOUT is low, the current level of the pilot is increased and the trip off current level of the output is increased. The increased output current raises VOUT until it is in agreement with the reference voltage. Output Voltage Selection VREF = 0.6V CREF = 220nF RT = 1k CC = 4.7nF POWER BLOCK 3 POWER BLOCK 4 PVIN4 LX4 PGND4 VOUT COUT RT ERROR AMPLIFIER + CC FB PVIN3 LX3 PGND3 L LXx OUT VREF REF RB CREF FIGURE 4. OUTPUT VOLTAGE SELECTION FIGURE 3. POWER BLOCK DIAGRAM Power Blocks The power output stage of the regulator consists of six 1A capable power blocks that are paralleled to provide full 6A output current capability. The block diagram in Figure 3 shows a top level view of the individual power blocks. Each power block has a power supply input pin, PVINx, a phase output pin, LXx, and a power supply ground pin, PGNDx. All PVINx pins must be connected to a common power supply rail and all PGNDx pins must be connected to a common ground. LXx pins should be connected to the output inductor based on the required load current, but must include the LX4 pin. For example, if 3A of output current is needed, any three LXx pins can be connected to the inductor as long as one of them is the LX4 pin. The unused LXx pins should be left unconnected. Connecting all six LXx pins to the output inductor provides a maximum 6A of output current. See the “Typical Application Schematic” on page 5 for pin connection guidance. A scaled pilot device associated with each power block provides current feedback. Power block 4 contains the master pilot device and this is why it must be connected to the output inductor. Main Control Loop During normal operation, the internal top power switch is turned on at the beginning of each clock cycle. Current in the output inductor ramps up until the current comparator trips and turns off the top power MOSFET. The bottom power MOSFET turns on and the inductor current ramps down for the rest of the cycle. The current comparator compares the output current at the ripple current peak to a current pilot. The error amplifier monitors VOUT and compares it with an internal reference voltage. The output voltage of the error amplifier drives a proportional current to the 9 The output voltage of the ISL70001SRH can be adjusted using an external resistor divider as shown in Figure 4. RT should be selected as 1kΩ to mitigate SEE. RT should be shunted by a 4.7nF ceramic capacitor, CC, to mitigate SEE and to improve loop stability margins. The REF pin should be bypassed to AGND with a 220nF ceramic capacitor to mitigate SEE. It should be noted that no current (sourcing or sinking) is available from the REF pin. RB can be determined from Equation 3. The designer can configure the output voltage from 0.8V to 85% of the input voltage. (EQ. 3) V REF R B = R T ⋅ ------------------------------------V OUT – V REF Switching Frequency/Synchronization The ISL70001SRH features an internal oscillator running at a fixed frequency of 1MHz ±15% over recommended operating conditions. The regulator can be configured to run from the internal oscillator or can be synchronized to another ISL70001SRH or an SEE hardened external clock with a frequency range of 1MHz ±20%. To run the regulator from the internal oscillator, connect the M/S pin to DVDD. In this case the output of the internal oscillator appears on the SYNC pin. To synchronize the regulator to the SYNC output of another ISL70001SRH regulator or to an SEE hardened external clock, connect the M/S pin to DGND. In this case the SYNC pin is an input that accepts an external synchronizing signal. When synchronizing multiple devices, Slave regulators are synchronized 180° out-of-phase with respect to the SYNC output of a Master regulator or to an external clock. Operation Initialization The ISL70001SRH initializes based on the state of the power-on reset (POR) monitor of the PVINx inputs and the state of the EN input. Successful initialization prompts a soft-start interval and the regulator begins FN6947.0 December 15, 2009 ISL70001SRH slowly ramping the output voltage. Once the commanded output voltage is within the proper window of operation, the power-good signal changes state from low to high indicating proper regulator operation. Power-On Reset The EN pin should be bypassed to the AGND pin with a 10nF ceramic capacitor to mitigate SEE. VR = 0.6V IEN = 11µA CEN = 10nF VIN1 PVINx The POR circuitry prevents the controller from attempting to soft-start before sufficient bias is present at the PVINx pins. The POR threshold of the PVINx pins is controlled by the PORSEL pin. For a nominal 5V supply voltage, PORSEL should be connected to DVDD. For a nominal 3.3V supply voltage, PORSEL should be connected to DGND. For nominal supply voltages between 5V and 3.3V, PORSEL should be connected to DGND. The POR rising and falling thresholds are shown in the “Electrical Specifications” table on page 8. Hysteresis between the rising and falling thresholds insures that small perturbations on PVINx seen during turn-on/turn-off of the regulator do not cause inadvertent turn-off/turn-on of the regulator. When the PVINx pins are below the POR rising threshold, the internal synchronous power MOSFET switches are turned off and the LXx pins are held in a high-impedance state. Enable and Disable After the POR input requirement is met, the ISL70001SRH remains in shutdown until the voltage at the enable input rises above the enable threshold. As shown in Figure 5, the enable circuit features a comparator type input. In addition to simple logic on/off control, the enable circuit allows the level of an external voltage to precisely gate the turn-on/turn-off of the regulator. An internal IEN current sink with a typical value of 11µA is only active when the voltage on the EN pin is below the enable threshold. The current sink pulls the EN pin low. As VIN2 rises, the enable level is not set exclusively by the resistor divider from VIN2. With the current sink active, the enable level is defined by Equation 4. R1 is the resistor from the EN pin to VIN2 and R2 is the resistor from the EN pin to the AGND pin. R1 V ENABLE = V R ⋅ 1 + -------- + I EN ⋅ R1 R2 (EQ. 4) Once the voltage at the EN pin reaches the enable threshold, the IEN current sink turns off. With the part enabled and the IEN current sink off, the disable level is set by the resistor divider. The disable level is defined by Equation 5. (EQ. 5) R1 V DISABLE = V R ⋅ 1 + -------R2 The difference between the enable and disable levels provides adjustable hysteresis so that noise on VIN2 does not interfere with the enabling or disabling of the regulator. 10 VIN2 ENABLE COMPARATOR R1 EN + POR LOGIC - CEN VR R2 IEN FIGURE 5. ENABLE CIRCUIT Soft-Start Once the POR and enable circuits are satisfied, the regulator initiates a soft-start. Figure 6 shows that the soft-start circuit clamps the error amplifier reference voltage to the voltage on an external soft-start capacitor connected to the SS pin. The soft-start capacitor is charged by an internal ISS current source. As the soft-start capacitor is charged, the output voltage slowly ramps to the set point determined by the reference voltage and the feedback network. Once the voltage on the SS pin is equal to the internal reference voltage, the soft-start interval is complete. The controlled ramp of the output voltage reduces the inrush current during start-up. The soft-start output ramp interval is defined in Equation 6 and is adjustable from approximately 2ms to 200ms. The value of the soft-start capacitor, CSS, should range from 8.2nF to 8.2µF, inclusive. The peak inrush current can be computed from Equation 7. The soft-start interval should be selected long enough to insure that the peak inrush current plus the peak output load current does not exceed the overcurrent trip level of the regulator. V REF t SS = C SS ⋅ --------------I (EQ. 6) SS V OUT I INRUSH = C OUT ⋅ ---------------t (EQ. 7) SS The soft-start capacitor is immediately discharged by a 2.2Ω resistor whenever POR conditions are not met or EN is pulled low. The soft-start discharge time is equal to 256 clock cycles. FN6947.0 December 15, 2009 ISL70001SRH Undervoltage Protection VREF = 0.6V ISS = 23µA RD = 2.2Ω VOUT RT FB RB ERROR AMPLIFIER PWM LOGIC + + SS REF VREF CSS CREF RD ISS FIGURE 6. SOFT-START CIRCUIT Power-Good The power-good (PGOOD) pin is an open-drain logic output which indicates when the output voltage of the regulator is within regulation limits. The power-good pin pulls low during shutdown and remains low when the controller is enabled. After a successful soft-start, the PGOOD pin releases and the voltage rises with an external pull-up resistor. The power-good signal transitions low immediately when the EN pin is pulled low. The power-good circuitry monitors the FB pin and compares it to the rising and falling thresholds shown in the “Electrical Specifications” table on page 8. If the feedback voltage exceeds the typical rising limit of 111% of the reference voltage, the PGOOD pin pulls low. The PGOOD pin continues to pull low until the feedback voltage falls to a typical of 107.5% of the reference voltage. If the feedback voltage drops below a typical of 89% of the reference voltage, the PGOOD pin pulls low. The PGOOD pin continues to pull low until the feedback voltage rises to a typical 92.5% of the reference voltage. The PGOOD pin then releases and signals the return of the output voltage within the power-good window. A hysteretic comparator monitors the FB pin of the regulator. The feedback voltage is compared to an undervoltage threshold that is a fixed percentage of the reference voltage. Once the comparator trips, indicating a valid undervoltage condition, a 3-bit undervoltage counter increments. The counter is reset if the feedback voltage rises back above the undervoltage threshold plus a specified amount of hysteresis outlined in the “Electrical Specifications” table on page 8. If the 3-bit counter overflows, the undervoltage protection logic shuts down the regulator. After the regulator shuts down, it enters a delay interval, equivalent to the soft-start interval, allowing the device to cool. The undervoltage counter is reset entering the delay interval. The protection logic initiates a normal soft-start once the delay interval ends. If the output successfully soft-starts, the powergood signal goes high and normal operation continues. If undervoltage conditions continue to exist during the soft-start interval, the undervoltage counter must overflow before the regulator shuts down again. This hiccup mode continues indefinitely until the output soft-starts successfully. Overcurrent Protection A pilot device integrated into the PMOS transistor of Power Block 4 samples current each cycle. This current feedback is scaled and compared to an overcurrent threshold based on the number of Power Blocks connected. Each additional Power Block connected beyond Power Block 4 increases the overcurrent limit by 2A. For example, if three Power Blocks are connected, the typical current limit threshold would be 3 x 2A = 6A. If the sampled current exceeds the overcurrent threshold, a 3-bit overcurrent counter increments by one LSB. If the sampled current falls below the threshold before the counter overflows, the counter is reset. Once the overcurrent counter reaches 111, the regulator shuts down. Fault Monitoring and Protection After the regulator shuts down, it enters a delay interval, equivalent to the soft-start interval, allowing the device to cool. The overcurrent counter is reset entering the delay interval. The protection logic initiates a normal soft-start once the delay interval ends. If the output successfully soft-starts, the powergood signal goes high and normal operation continues. If overcurrent conditions continue to exist during the soft-start interval, the overcurrent counter must overflow before the regulator shut downs the output again. This hiccup mode continues indefinitely until the output soft-starts successfully. The ISL70001SRH actively monitors output voltage and current to detect fault conditions. Fault conditions trigger protective measures to prevent damage to the regulator and external load device. Note: It is recommended that a Schottky diode of appropriate rating be added from the LXx pins to the PGNDx pins to prevent severe negative ringing that can disturb the overcurrent counter. The PGOOD pin can be pulled up to any voltage from 0V to 5.5V, independent of the supply voltage. The pull-up resistor should have a nominal value from 1kΩ to 10kΩ. The PGOOD pin should be bypassed to DGND with a 10nF ceramic capacitor to mitigate SEE. 11 FN6947.0 December 15, 2009 ISL70001SRH Component Selection Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a power converter. It is assumed the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides a complete evaluation board that includes schematic, BOM, and an example PCB layout. Output Filter Design The output inductor and the output capacitor bank together form a low-pass filter responsible for smoothing the pulsating voltage at the phase node. The filter must also provide the transient energy until the regulator can respond. Since the filter has low bandwidth relative to the switching frequency, it limits the system transient response. The output capacitors must supply or sink current while the current in the output inductor increases or decreases to meet the load demand. OUTPUT CAPACITOR SELECTION The critical load parameters in choosing the output capacitors are the maximum size of the load step (ΔISTEP), the load-current slew rate (di/dt), and the maximum allowable output voltage deviation under transient loading (ΔVMAX). Capacitors are characterized according to their capacitance, ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance). At the beginning of a load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount shown in Equation 8. di ΔV MAX ≈ ESL × ----- + [ ESR × ΔI STEP ] dt (EQ. 8) The filter capacitors selected must have sufficiently low ESL and ESR such that the total output voltage deviation is less than the maximum allowable ripple. Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but larger ESR. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. Ceramic capacitors with X7R dielectric are recommended. Alternately, a combination of low ESR solid tantalum capacitors and ceramic capacitors with X7R dielectric may be used. and source the inductor AC ripple current, a voltage, VP-P(MAX), develops across the bulk capacitor according to Equation 9. ( V IN – V OUT )V OUT V P-P(MAX) = ESR × ----------------------------------------------------L OUT × f s × V IN (EQ. 9) Another consideration in selecting the output capacitors is loop stability. The total output capacitance sets the dominant pole of the PWM. Because the ISL70001SRH uses integrated compensation techniques, it necessary to restrict the output capacitance in order to optimize loop stability. The recommended load capacitance can be estimated using Equation 10. 1.8V C OUT = 75μF × NumberofLXxPinsConnected × ---------------V OUT (EQ. 10) OUTPUT INDUCTOR SELECTION Once the output capacitors are selected, the maximum allowable ripple voltage, VP-P(MAX), determines the lower limit on the inductance as shown in Equation 11. ( V IN – V OUT )V OUT L OUT ≥ ESR × -----------------------------------------------------f s × V IN × V P-P(MAX) (EQ. 11) Since the output capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductor must be capable of assuming the entire load current before the output voltage decreases more than ΔVMAX. This places an upper limit on inductance. Equation 12 gives the upper limit on output inductance for the case when the trailing edge of the current transient causes the greater output voltage deviation than the leading edge. Equation 13 addresses the leading edge. Normally, the trailing edge dictates the inductance selection because duty cycles are usually <50%. Nevertheless, both inequalities should be evaluated, and inductance should be governed based on the lower of the two results. In each equation, LOUT is the output inductance, COUT is the total output capacitance and ΔIL(P-P) is the peak to peak ripple current in the output inductor. 2 ⋅ C OUT ⋅ V OUT L OUT ≤ -------------------------------------------ΔV MAX – ( ΔI L(P-P) ⋅ ESR ) ( ΔI STEP ) 2 (EQ. 12) 2 ⋅ C OUT - ΔV MAX – ( ΔI L(P-P) ⋅ ESR ) ⎛ V IN – V OUT⎞ L OUT ≤ ---------------------------⎝ ⎠ ( ΔI STEP ) 2 (EQ. 13) The other concern when selecting an output inductor is to insure there is adequate slope compensation when the regulator is operated above 50% duty cycle. Since the internal slope compensation is fixed, output The ESR of the bulk capacitors is responsible for most of the output voltage ripple. As the bulk capacitors sink 12 FN6947.0 December 15, 2009 ISL70001SRH inductance should satisfy Equation 14 to insure this requirement is met. 4.32μH L OUT ≥ ---------------------------------------------------------------------------------------NumberofLXxPinsConnected (EQ. 14) Input Capacitor Selection Input capacitors are responsible for sourcing the AC component of the input current flowing into the switching power devices. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the switching power devices which is related to duty cycle. The maximum RMS current required by the regulator is closely approximated by Equation 15. I RMS = MAX 2 V 2 1 ⎛ V IN – V OUT V OUT⎞ ⎞ OUT ⎛ ----------------× ⎜I + ------ × ⎜ ---------------------------------- × -----------------⎟ ⎟ OUT 12 ⎝ L V V × f ⎝ ⎠ ⎠ MAX IN IN OUT s (EQ. 15) The important parameters to consider when selecting an input capacitor are the voltage rating and the RMS ripple current rating. For reliable operation, select capacitors with voltage ratings at least 1.5x greater than the maximum input voltage. The capacitor RMS ripple current rating should be higher than the largest RMS ripple current required by the circuit. Ceramic capacitors with X7R dielectric are recommended. Alternately, a combination of low ESR solid tantalum capacitors and ceramic capacitors with X7R dielectric may be used. The ISL70001SRH requires a minimum effective input capacitance of 100µF for stable operation. PCB Design PCB design is critical to high-frequency switching regulator performance. Careful component placement and trace routing are necessary to reduce voltage spikes and minimize undesirable voltage drops. Selection of a suitable thermal interface material is also required for optimum heat dissipation and to provide lead strain relief. PCB Plane Allocation Four layers of two ounce copper are recommended. Layer 2 should be a dedicated ground plane with all critical component ground connections made with vias to this layer. Layer 3 should be a dedicated power plane split between the input and output power rails. Layers 1 and 4 should be used primarily for signals, but can also provide additional power and ground islands as required. 13 PCB Component Placement Components should be placed as close as possible to the IC to minimize stray inductance and resistance. Prioritize the placement of bypass capacitors on the pins of the IC in the order shown: REF, SS, AVDD, DVDD, PVINx (high frequency capacitors), EN, PGOOD, PVINx (bulk capacitors). Locate the output voltage resistive divider as close as possible to the FB pin of the IC. The top leg of the divider should connect directly to the POL (Point Of Load) and the bottom leg of the divider should connect directly to AGND. The junction of the resistive divider should connect directly to the FB pin. Locate a Schottky clamp diode as close as possible to the LXx and PGNDx pins of the IC. A small series R-C snubber connected from the LXx pins to the PGNDx pins may be used to damp high frequency ringing on the LXx pins if desired. PCB Layout Use a small island of copper to connect the LXx pins of the IC to the output inductor on layers 1 and 4. Void the copper on layers 2 and 3 adjacent to the island to minimize capacitive coupling to the power and ground planes. Place most of the island of layer 4 to minimize the amount of copper that must be voided from the ground plane (layer 2). Keep all other signal traces as short as possible. For an example layout refer to ANxxxx. Thermal Management For optimum thermal performance, place a pattern of vias on the top layer of the PCB directly underneath the IC. Connect the vias to the ground plane on layer 2, which serves as a heatsink. To insure good thermal contact, thermal interface material such as a Sil-Pad or thermally conductive epoxy should be used to fill the gap between the vias and the bottom of the IC. Lead Strain Relief Use of a Sil-Pad or a thin layer of thermally conductive epoxy will raise the bottom of the IC from the PCB surface so that a slight bend can be added to the leads of the IC for strain relief. FN6947.0 December 15, 2009 ISL70001SRH Die Characteristics BACKSIDE FINISH Silicon Die Dimensions 5720µm x 5830µm (225.2 mils x 229.5 mils) Thickness: 483µm ± 25.4µm (19.0 mils ± 1 mil) ASSEMBLY RELATED INFORMATION Substrate Potential PGND Interface Materials ADDITIONAL INFORMATION GLASSIVATION Type: Silicon Oxide and Silicon Nitride Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm Worst Case Current Density < 2 x 105 A/cm2 TOP METALLIZATION Transistor Count Type: AlCu (0.5%) Thickness: 2.7µm ±0.4µm 25030 Layout Characteristics SUBSTRATE Type: Silicon Isolation: Junction Step and Repeat 5720µm x 5830µm Connect PGND to PGNDx Metallization Mask Layout ISL70001SRH LX1 SYNC PVIN1 PGND1 PGND2 LX2 PVIN2 PVIN3 M/S ZAP LX3 TDI TDO PGND3 PGOOD PGND4 SS LX4 DVDD PVIN4 PVIN5 DGND PGND LX5 AGND AVDD REF 14 FB EN PORSEL PVIN6 LX6 PGND6 PGND5 FN6947.0 December 15, 2009 ISL70001SRH TABLE 1. LAYOUT X-Y COORDINATES PAD NUMBER (µm) (µm) (µm) (µm) BOND WIRES PER PAD AVDD 15 478 263 135 135 1 REF 16 865 263 135 135 1 FB 17 1295 263 135 135 1 EN 18 1751 263 135 135 1 PORSEL 19 2151 263 135 135 1 PVIN6 20 2838 188 521 135 3 LX6 21 3449 188 521 135 3 PGND6 22 4060 188 521 135 3 PGND5 23 4845 188 521 135 3 LX5 24 5449 925 135 521 3 PVIN5 25 5449 1651 135 521 3 PVIN4 26 5449 2263 135 521 3 LX4 27 5449 2874 135 521 3 PGND4 28 5449 3485 135 521 3 PGND3 29 5449 4096 135 521 3 LX3 30 5449 4745 135 521 3 PVIN3 31 4941 5559 521 135 3 PVIN2 32 4137 5559 521 135 3 LX2 33 3449 5559 521 135 3 PGND2 34 2838 5559 521 135 3 PGND1 1 2227 5559 521 135 3 LX1 2 1578 5559 521 135 3 PVIN1 3 962 5559 521 135 3 SYNC 4 544 5559 135 135 1 M/S 5 226 5280 135 135 1 ZAP 6 226 4910 135 135 1 TDI 7 226 4540 135 135 1 TDO 8 226 4170 135 135 1 PGOOD 9 226 3777 135 135 1 SS 10 226 3425 135 135 1 DVDD 11 226 2566 135 333 2 DGND 12 226 1538 135 333 2 PGND 13 226 1018 135 135 1 AGND 14 226 654 135 135 1 X PAD NAME 15 Y dX dY FN6947.0 December 15, 2009 ISL70001SRH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION 12/15/09 FN6947.0 CHANGE Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL70001SRH To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6947.0 December 15, 2009