PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT µPD161661 POWER SUPPLY FOR TFT-LCD DRIVER DESCRIPTION The µPD161661 is a power supply IC for TFT-LCD driver. This ICs can generate the levels which TFT-LCD driver need, from single voltage input. FEATURES • To generate 3 levels from single voltage input • To integrate regulator circuit for source driver ORDERING INFORMATION Part number Package µPD161661P/W Chip/Wafer Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative. The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15917EJ1V0PM00 (1st edition) Date Published January 2002 NS CP(K) Printed in Japan © 2002 µPD161661 1. BLOCK DIAGRAM/SYSTEM DIAGRAM VDC C1+ VSS C1− C2+ DCON CR Oscillator C2− C3+ FS LFS DC/DC Converter Contorl Divider DC/DC Converter LPM RGONP EXRVS C3− C4+ C4− C5+ VDC x3 Regulator Control RC1 VDC x6 C5− RC2 RSEL VO VREG 0 V (VSS) VREF VDD1 VDD2 VREFSEL VREF VEE VS MVS RC1 RC1 ACS LACS TESTIN1TESTIN3 TESTOUT RC2 Remark /xxx indicates active low signal. 2 Preliminary Product Information S15917EJ1V0PM µPD161661 2. PIN CONFIGURATION (Pad Layout) Chip size: X = 3.60 mm, Y = 3.40 mm 2 Pad size : 100 x 100 µm TYP. (1) Alignment mark T.B.D. 24 DUMMY DUMMY C1− C1+ C2− C2+ C3− C3+ C4− C4+ C5− C5+ DUMMY (2) Arrangement 13 25 12 Chip Surface VDD1 DUMMY VDC (Bump size) VSS DUMMY VO VDD2 VS DUMMY Y MVS DUMMY X DUMMY DUMMY TESTIN1 DUMMY TESTIN2 DCON TESTIN3 RGONP LPM TESTOUT 36 D161661 1 DUMMY DUMMY VREF VSS LACS VREFSEL ACS RSEL FS LFS 48 EXRVS DUMMY 37 DUMMY DUMMY Remark T.B.D. : To be determined. Preliminary Product Information S15917EJ1V0PM 3 µPD161661 Table 2-1. Pad Layout Pad No. Pad name X[mm] Y[mm] Pad No. Pad name X[mm] Y[mm] 1 DUMMY 1632 −1237.5 37 DUMMY −1237.5 −1532 2 LPM 1632 −1012.5 38 EXRVS −1012.5 −1532 3 RGONP 1632 −787.5 39 LFS −787.5 −1532 4 DCON 1632 −562.5 40 FS −562.5 −1532 5 DUMMY 1632 −337.5 41 RSEL −337.5 −1532 6 DUMMY 1632 −112.5 42 ACS −112.5 −1532 7 MVS 1632 112.5 43 VREFSEL 112.5 −1532 8 VS 1632 337.5 44 LACS 337.5 −1532 9 VDD2 1632 562.5 45 VSS 562.5 −1532 10 VSS 1632 787.5 46 VREF 787.5 −1532 11 VDC 1632 1012.5 47 DUMMY 1012.5 −1532 12 DUMMY 1632 1237.5 48 DUMMY 1237.5 −1532 13 DUMMY 1237.5 1532 − 1012.5 1532 + 787.5 1532 − 562.5 1532 + 337.5 1532 − 112.5 1532 19 C3 + −112.5 1532 20 C4− −337.5 1532 21 + −562.5 1532 − −787.5 1532 + −1012.5 1532 14 15 16 17 18 22 4 C1 C1 C2 C2 C3 C4 C5 23 C5 24 DUMMY −1237.5 1532 25 DUMMY −1632 1237.5 26 VDD1 −1632 1012.5 27 DUMMY −1632 787.5 28 VO −1632 562.5 29 DUMMY −1632 337.5 30 DUMMY −1632 112.5 31 DUMMY −1632 −112.5 32 TESTIN1 −1632 −337.5 33 TESTIN2 −1632 −562.5 34 TESTIN3 −1632 −787.5 35 TESTOUT −1632 −1012.5 36 DUMMY −1632 −1237.5 Preliminary Product Information S15917EJ1V0PM µPD161661 3. PIN FUNCTIONS (1/2) Symbol Pin Name VDC Power supply VSS Ground Pad No. I/O 11 − 10, 45 − Description Power supply for logic circuit and DC/DC converter. Ground for logic circuit and DC/DC converter power supply. VDD1 DC/DC converter output 26 − x6 voltage boost output of DC/DC converter. Outputs a potential that is VDC boosted to six times the original level. Use this pin connected to a voltage stabilization capacitor. VDD2 DC/DC converter output 9 − x3 voltage boost output of DC/DC converter. Outputs a potential that is VDC boosted to three times the original level. Use this pin connected to a voltage stabilization capacitor. VO Rectangle signal output for 28 − negative boost Rectangle signal output for negative boost. A potential that is VDC boosted to five times the original level is used for the VO voltage range. A negative power supply can be created for gate IC bottom output by connecting an external component to this pin. VS Regulator output 8 − Regulator output for source driver. Use this pin connected to a voltage stabilization capacitor. VREF Reference voltage input/output 46 I/O Reference voltage input/output of VS regulator. The internal reference supply voltage is used when VREFSEL = L. At this time, this pin can also be used as the reference voltage output of the negative power supply regulator incorporated in the gate driver, etc. When VREFSEL = H, the external reference voltage can be input as the regulator reference voltage. DCON DC/DC converter control 4 I DC/DC converter ON/OFF control. Use this pin connected to DC/DC converter control pin (DCON) of source driver or the control port output of CPU. DCON = H : DC/DC converter ON DCON = L : DC/DC converter OFF RGONP Regulator control 3 I Regulator ON/OFF control for source driver voltage (VS). Use this pin connected to the regulator control pin (RGONP) of the source driver or the control port output of CPU. RGONP = H : Regulator ON RGONP = L : Regulator OFF EXRVS VS regulating resistor selection 38 I This pin selects whether to use the internal feedback resistor or connect an external resistor for the VS regulator amplifier. When external resistor connection is selected, configure a feedback circuit between the MVS, VS, and VSS pins by connecting an external resistor. EXRVS = H: External resistor connection EXRVS = L: Internal feedback resistor used. Preliminary Product Information S15917EJ1V0PM 5 µPD161661 (2/2) Symbol MVS Pin Name VS regulator input Pad No. I/O Description 7 − Feedback input (+) of the regulator amplifier for VS output. This pin is used as follows according to the setting of EXRVS. EXRVS = H : To connect external resistor. EXRVS = L : Leave it open. RSEL Internal resistor selection for 41 I regulator This pin selects the internal resistor for the regulator and sets the source driver supply voltage output from the VS pin as follows. Note that this pin setting is valid when EXRVS = L. RSEL = H: 5.0 V VS output voltage RSEL = L: 4.0 V VS output voltage VREFSEL Regulator reference voltage 43 I input selection This pin selects external or internal reference voltage of VS regulator. When external reference is selected, input reference voltage from VREF pin. VREFSEL = H : External reference voltage is selected. VREFSEL = L : Internal reference voltage is selected. LPM Low power mode signal 2 I Control signal for low power mode. LPM = H : Low power mode LPM = L : Normal mode The settings made by the LACS and LFS pins are valid in the low power mode, and settings made by the ACS and FS pins are valid in the normal mode. Connect to low power mode setting pin (LPMP) of source driver or control port output of CPU. ACS Amp current selection 42 I To select Amp current in normal mode. For detail, refer to 4. MODE DESCRIPTION. LACS Amp current selection 44 I To select Amp current in low power mode. For detail, refer to 4. MODE DESCRIPTION. FS OSC frequency selection 40 I To select OSC frequency for DC/DC converter when in normal mode. For detail, refer to 4. MODE DESCRIPTION. LFS Low power mode 39 I OSC frequency selection To select OSC frequency for DC/DC converter in low power mode. For detail, refer to 4. MODE DESCRIPTION. + − + − + − + − + − C1 , C1 C2 , C2 Capacitor connect pin for 15, 14 boost 17, 16 C3 , C3 C4 , C4 C5 , C5 − Capacitor connect pin for boost of DC/DC converter. + 19, 18 The capacitance and tolerance of each capacitor are 21, 20 shown below. 23, 22 Capacitance : 1 µF Tolerance : 10 V TESTIN1 to Test 32 to 34 I TESTIN3 IC test mode pin. Normally, leave it open. TESTOUT TEST output 35 O DUMMY Dummy pin 1, 5, 6, 12, − IC test mode pin. Normally, leave it open. Dummy pin. Leave it open. 13, 24, 25, 27, 29 to 31, 36, 37, 47, 48 6 − Connect these pins between each Cn and Cn . Preliminary Product Information S15917EJ1V0PM µPD161661 4. MODE DESCRIPTION DC/DC converter control DCON H DC/DC converter ON L DC/DC converter OFF H Regulator ON L Regulator OFF (VS output : High impedance) Regulator control RGONP VS regulating resistor EXRVS H External resistor L Internal resistor Regulator reference voltage input selection VREFSEL H VREF : External reference voltage input L VREF : Internal reference voltage output VS regulator selection VS RSEL H 5.0 V L 4.0 V Amp current selection ACS, LACS Note Note VS Source current Sink current H 3 mA > 0.5 µA 1 µA L 3 mA > 5 µA 10 µA ACS : Selection of current during normal driving LACS : Selection of current in low power mode Amp current OSC frequency selection FS, LFS Note Note OSC H fOSC/8 L fOSC/2 FS : Selection of current during normal driving LFS : Selection of current in low power mode Preliminary Product Information S15917EJ1V0PM 7 µPD161661 Low power mode selection LPM Drive mode H Low power mode The settings made by LACS and LFS are valid. L Normal mode The settings made by AC and FS are valid. 8 Preliminary Product Information S15917EJ1V0PM µPD161661 Figure 4-1. Example of Internal/External resistor for the regulator <Internal resistor [EXRVS = L]> VREG VREF VREFSEL VREF VS MVS <External resistor [EXRVS = L]> VREG VREF VREFSEL VREF VS MVS Rb VS Ra Remark VS = (1+Rb/Ra) VREF Preliminary Product Information S15917EJ1V0PM 9 µPD161661 5. POWER ON/OFF SEQUENCE 5.1 Power ON Sequence T.B.D. 10 Preliminary Product Information S15917EJ1V0PM µPD161661 5.2 Power OFF Sequence T.B.D. Preliminary Product Information S15917EJ1V0PM 11 µPD161661 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V) Parameter Symbol Supply Voltage VDC Input Voltage VI Input Current II Output Voltage VDD1 Output Current IO Rating Unit –0.5 to + 6.0 V −0.5 to VDC + 0.5 V ±10 mA –0.5 to +38 V ±10 mA Operating Ambient Temperature TA −30 to +85 °C Storage Temperature −55 to +125 °C Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = –30 to +85°°C, VSS = 0 V) Parameter Symbol Supply Voltage VDC Input Voltage VI Condition MIN. TYP. MAX. Unit 2.50 2.85 3.60 V VDC V 0 Electrical Characteristics (Unless otherwise specified, TA = –30 to +85°°C, VDC = 2.5 to 3.6 V, VSS = 0 V) Parameter Symbol High Level Input Voltage VIH Low Level Output Voltage VIL Boost Voltage VDD1 Boost Voltage VDD1 Condition MIN. TYP. MAX. 0.7 VDC ACS (LACS) = H, FS (LFS) = L, Unit V 0.3 VDC V 5 VDC 6 VDC V 5 VDC 6 VDC V IDD1 = 100 µA ACS (LACS) = H, FS (LFS) = H, IDD1 = 100 µA Output Voltage VS1 Rsel = H, FS (LFS) = L, 4.5 5 5.5 V 3.5 4 4.5 V T.B.D. µA T.B.D. µA 2.75 V IS = 3.0 mA Output Voltage VS2 Rsel = L, FS (LFS) = L, IS = 3.0 mA VDC Static Current Consumption VDC1 ACS (LACS) = H, FS (LFS) = L, IDD1 = IS = 0.0 mA VDC Static Current Consumption Ivdcd ACS (LACS) = H, FS (LFS) = L, IDD1 = IS = 0.0 mA VREF Voltage 12 2.25 Preliminary Product Information S15917EJ1V0PM 2.50 µPD161661 [MEMO] Preliminary Product Information S15917EJ1V0PM 13 µPD161661 [MEMO] 14 Preliminary Product Information S15917EJ1V0PM µPD161661 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Product Information S15917EJ1V0PM 15