ISL70419SEH Datasheet

Radiation Hardened 36V Quad Precision Low Power
Operational Amplifier With Enhanced SET Performance
ISL70419SEH
Features
The ISL70419SEH contains four very high precision amplifiers
featuring the perfect combination of low noise vs power
consumption. Low offset voltage, low IBIAS current and low
temperature drift making them the ideal choice for applications
requiring both high DC accuracy and AC performance. The
combination of high precision, low noise, low power and small
footprint provides the user with outstanding value and flexibility
relative to similar competitive parts.
• Electrically screened to DLA SMD# 5962-14226
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
The ISL70419SEH is offered in a 14 Ld hermetic ceramic
flatpack package. The device is offered in an industry standard
pin configuration and operates over the extended temperature
range from -55°C to +125°C.
Applications
• Precision instrumentation
• Spectral analysis equipment
• Active filter blocks
• Thermocouples and RTD reference buffers
• Data acquisition
• Low input offset voltage. . . . . . . . . . . . . . . . . . . ±110µV, Max.
• Superb offset temperature coefficient. . . . . . . 1µV/°C, Max.
• Input bias current . . . . . . . . . . . . . . . . . . . . . . . . . ±15nA, Max.
• Input bias current TC . . . . . . . . . . . . . . . . . . . . ±5pA/°C, Max.
• Low current consumption . . . . . . . . . . . . . . . . . . . . . . . 440µA
• Voltage noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8nV/Hz
• Wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 36V
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
• Radiation environment
- SEB LETTH (VS = ±18V) . . . . . . . . . . . . . 86.4 MeV•cm2/mg
- SET recovery time . . . . . . . . . . ≤ 10µs at 60 MeV•cm2/m
- SEL immune (SOI process)
- Total dose HDR (50-300rad(Si)/s) . . . . . . . . . . 300krad(Si)
- Total dose LDR (10mrad(Si)/s) . . . . . . . . . . . 100krad(Si) *
* Product capability established by initial characterization. The
EH version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate.
Related Literature
• Power supply control
AN1936, ISL70419SEHEV1Z Evaluation Board User’s Guide
10
CH2 = VOUT - B
9
C1
V+
ISL70419SEH
VIN
R2
1.84k
4.93k
3.3nF
OUTPUT
+
7
6
5
4
3
2
C2
V-
SALLEN-KEY LOW PASS FILTER (fC = 10kHz)
FIGURE 1. TYPICAL APPLICATION
July 11, 2014
FN8653.0
SET DURATION (µs)
8.2nF
R1
VS = ±15V
8
1
1
0
-8
-6
-4
-2
0
SET EXTREME DEVIATION(V)
2
4
FIGURE 2. SET DEVIATION vs DURATION FOR LET = 60 MeV•cm2/mg
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL70419SEH
Ordering Information
ORDERING/SMD NUMBER
(Note 2)
PART NUMBER
(Note 1)
TEMPERATURE RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962F1422601VXC
ISL70419SEHVF
-55 to +125
14 Ld Flatpack with EPAD
K14.C
ISL70419SEHF/PROTO
ISL70419SEHF/PROTO
-55 to +125
14 Ld Flatpack with EPAD
K14.C
5962F1422601V9AX
ISL70419SEHVX
-55 to +125
DIE
ISL70419SEHX/SAMPLE
ISL70419SEHX/SAMPLE
-55 to +125
DIE
ISL70419SEHEV1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
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ISL70419SEH
Pin Configuration
ISL70419SEH
(14 LD FLATPACK)
TOP VIEW
OUT_A
1
-IN_A
2
+IN_A
14
OUT_D
13
-IN_D
3
12
+IN_D
V+
4
11
V-
+IN_B
5
10
+IN_C
9
-IN_C
8
OUT_C
-IN_B
6
OUT_B
7
A
- +
- +
B
D
+ -
+ C
Pin Descriptions
PIN NUMBER
PIN NAME
EQUIVALENT CIRCUIT
1
OUT_A
Circuit 2
Amplifier A output
2
-IN_A
Circuit 1
Amplifier A inverting input
3
+IN_A
Circuit 1
Amplifier A non-inverting input
4
V+
Circuit 3
Positive power supply
5
+IN_B
Circuit 1
Amplifier B non-inverting input
6
-IN_B
Circuit 1
Amplifier B inverting input
7
OUT_B
Circuit 2
Amplifier B output
8
OUT_C
Circuit 2
Amplifier C output
9
-IN_C
Circuit 1
Amplifier C inverting input
10
+IN_C
Circuit 1
Amplifier C non-inverting input
11
V-
Circuit 3
Negative power supply
12
+IN_D
Circuit 1
Amplifier D non-inverting input
13
-IN_D
Circuit 1
Amplifier D inverting input
14
OUT_D
Circuit 2
Amplifier D output
EPAD
N/A
EPAD under Package (Unbiased, tied to package lid)
V+
500Ω
V+
500Ω
IN-
IN+
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VCIRCUIT 2
3
V+
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
V-
CIRCUIT 1
DESCRIPTION
V-
CIRCUIT 3
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ISL70419SEH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Supply Voltage (LET = 86.4 MeV•cm2/mg). . . . . . . . . . . . . 36V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input current for Input Voltage >V+ or <V-. . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration (1 output at a time). . . . . . . . . . . . . . . . Indefinite
ESD Rating
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV
Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
14 Ld Flatpack (Notes 3, 4). . . . . . . . . . . . .
35
8
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX) . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V (±5V) to 30V (±15V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For JC, the "case temp" location is the center of the package underside.
Electrical Specifications
VS ± 15V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300rad(Si)/s; or across a total
ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s.
PARAMETER
VOS
DESCRIPTION
Offset Voltage Drift
IB
Input Bias Current
TCIB
Input Bias Current Temperature
Coefficient
IOS
Input Offset Current
VCM
CMRR
MIN
(Note 5)
Input Offset Voltage
TCVOS
TCIOS
TEST CONDITIONS
guaranteed by characterization not tested
-2.5
TYP
MAX
(Note 5)
UNITS
10
85
µV
110
µV
0.1
1
µV/°C
0.08
2.5
nA
TA = -55°C to +125°C
-5
5
nA
over high and low dose radiation
-15
15
nA
guaranteed by characterization not tested
-5
1
5
pA/°C
-2.5
0.08
2.5
nA
3
nA
TA = -55°C to +125°C
-3
over high and low dose radiation
-10
Input Offset Current Temperature
Coefficient
guaranteed by characterization not tested
-3
Input Voltage Range
guaranteed by CMRR test
-13
Common-Mode Rejection Ratio
VCM = -13V to +13V
120
0.42
145
120
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±20V
120
10
nA
3
pA/°C
13
V
dB
dB
145
120
dB
dB
AVOL
Open-Loop Gain
VO = -13V to +13V, RL = 10k to ground
3,000
14,000
V/mV
VOH
Output Voltage High
RL = 10k to ground
13.5
13.7
V
13.2
RL = 2k to ground
13.3
13.0
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4
V
13.55
V
V
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ISL70419SEH
Electrical Specifications
VS ± 15V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300rad(Si)/s; or across a total
ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued)
PARAMETER
VOL
DESCRIPTION
Output Voltage Low
TEST CONDITIONS
MIN
(Note 5)
RL = 10k to ground
RL = 2k to ground
IS
ISC
VSUPPLY
MAX
(Note 5)
UNITS
-13.7
-13.5
V
-13.2
V
-13.3
V
-13.0
V
0.625
mA
0.75
mA
-13.55
Supply Current/Amplifier
0.44
Short-Circuit Current
Supply Voltage Range
TYP
43
guaranteed by PSRR
± 2.25
mA
± 20
V
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
AV = 1k, RL = 2k
1.5
MHz
enVp-p
Voltage Noise VP-P
0.1Hz to 10Hz
0.25
µVP-P
en
Voltage Noise Density
f = 10Hz
10
nV/Hz
en
Voltage Noise Density
f = 100Hz
8.2
nV/Hz
en
Voltage Noise Density
f = 1kHz
8
nV/Hz
en
Voltage Noise Density
f = 10kHz
8
nV/Hz
in
Current Noise Density
f = 1kHz
0.1
pA/Hz
Total Harmonic Distortion
1kHz, G = 1, VO = 3.5VRMS, RL = 2k
0.0009
%
1kHz, G = 1, VO = 3.5VRMS, RL = 10k
0.0005
%
0.5
V/µs
THD + N
TRANSIENT RESPONSE
SR
Slew Rate, VOUT 20% to 80%
AV = 11, RL = 2kVO = 4VP-P
0.3
0.2
tr, tf,
Small Signal
ts
tOL
OS+
OS-
V/µs
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 50mVP-P,
RL = 10kto VCM
130
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 50mVP-P, RL = 10kto VCM
130
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P, RL = 5kto VCM
21
µs
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P, RL = 5kto VCM
24
µs
Settling Time to 0.1%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P, RL = 5kto VCM
13
µs
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P, RL = 5kto VCM
18
µs
Output Positive Overload Recovery Time
AV = -100, VIN = 0.2VP-P, RL = 2kto VCM
5.6
µs
Output Negative Overload Recovery Time AV = -100, VIN = 0.2VP-P, RL = 2kto VCM
10.6
µs
AV = 1, VOUT = 10VP-P, Rf = 0
RL = 2kto VCM
15
%
AV = 1, VOUT = 10VP-P, Rf = 0
RL = 2kto VCM
15
Positive Overshoot
Negative Overshoot
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5
450
ns
625
ns
600
ns
700
ns
33
%
%
33
%
July 11, 2014
FN8653.0
ISL70419SEH
Electrical Specifications VS ± 5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; or over a total
ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s.
PARAMETER
VOS
DESCRIPTION
Offset Voltage Drift
IB
Input Bias Current
TCIB
Input Bias Current Temperature
Coefficient
IOS
Input Offset Current
VCM
CMRR
MIN
(Note 5)
Input Offset Voltage
TCVOS
TCIOS
CONDITIONS
guaranteed by characterization not
tested
-2.5
TYP
MAX
(Note 5)
UNIT
10
150
µV
250
µV
0.1
1
µV/°C
0.08
2.5
nA
TA = -55°C to +125°C
-5
5
nA
over high and low dose radiation
-15
15
nA
guaranteed by characterization not
tested
-5
1
5
pA/°C
-2.5
0.08
2.5
nA
TA = -55°C to +125°C
-3
3
nA
over high and low dose radiation
-10
10
nA
Input Offset Current Temperature
Coefficient
guaranteed by characterization not
tested
-3
3
pA/°C
Input Voltage Range
guaranteed by CMRR test
Common-Mode Rejection Ratio
VCM = -3V to +3V
0.42
-3
120
3
145
120
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±5V
120
dB
145
dB
120
AVOL
Open-Loop Gain
VO = -3.0V to +3.0V
RL = 10k to ground
VOH
Output Voltage High
RL = 10k to ground
dB
3,000
14,000
3.5
3.7
V/mV
V
3.2
RL = 2k to ground
3.3
V
3.55
V
3.0
VOL
Output Voltage Low
RL = 10k to ground
RL = 2k to ground
IS
ISC
Supply Current/Amplifier
V
-3.7
-3.55
0.44
Short-Circuit Current
V
dB
43
-3.5
V
-3.2
V
-3.3
V
-3.0
V
0.625
mA
0.75
mA
mA
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
AV = 1k, RL = 2k
1.5
MHz
enp-p
Voltage Noise
0.1Hz to 10Hz
0.25
µVP-P
en
Voltage Noise Density
f = 10Hz
12
nV/Hz
en
Voltage Noise Density
f = 100Hz
8.6
nV/Hz
en
Voltage Noise Density
f = 1kHz
8
nV/Hz
en
Voltage Noise Density
f = 10kHz
8
nV/Hz
in
Current Noise Density
f = 1kHz
0.1
pA/Hz
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Electrical Specifications VS ± 5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; or over a total
ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
TRANSIENT RESPONSE
Slew Rate, VOUT 20% to 80%
AV = 11, RL = 2kVO = 4VP-P
0.5
V/µs
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 50mVP-P,
RL = 10kto VCM
130
ns
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 50mVP-P,
RL = 10kto VCM
130
ns
Settling Time to 0.1%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P,
RL = 5kto VCM
12
µs
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P,
RL = 5kto VCM
19
µs
Output Positive Overload Recovery Time
AV = -100, VIN = 0.2VP-P
RL = 2kto VCM
7
µs
Output Negative Overload Recovery Time
AV = -100, VIN = 0.2VP-P
RL = 2kto VCM
5.8
µs
OS+
Positive Overshoot
AV = 1, VOUT = 10VP-P, Rf = 0
RL = 2kto VCM
15
%
OS-
Negative Overshoot
AV = 1, VOUT = 10VP-P, Rf = 0
RL = 2kto VCM
15
%
SR
tr, tf,
Small Signal
ts
tOL
NOTE:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified.
100
100
VS = ±15V
75
60
40
25
VOS (µV)
VOS (µV)
50
0
-25
20
0
-20
-40
-50
-60
-75
-100
-70
VS = ±5V
80
-80
-50
-30
-10
10
30
50
70
90
110
-100
-70
130
-50
-30
-10
10
TEMPERATURE (°C)
FIGURE 3. VOS vs TEMPERATURE
300
300
200
200
100
100
IB- (pA)
IB+ (pA)
90
110
130
0
-100
0
-100
-200
-200
-300
-300
-400
-400
-50
-30
-10
10
30
50
70
90
110
VS = ±15V
400
-500
-70
130
-50
-30
-10
10
30
50
70
90
110
130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. IB+ vs TEMPERATURE
FIGURE 6. IB- vs TEMPERATURE
500
500
VS = ±5V
400
400
300
300
200
200
100
100
IB- (pA)
IB+ (pA)
70
500
VS = ±15V
400
0
-100
-100
-200
-300
-300
-400
-400
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
FIGURE 7. IB+ vs TEMPERATURE
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90
110
130
VS = ±5V
0
-200
-500
-70
50
FIGURE 4. VOS vs TEMPERATURE
500
-500
-70
30
TEMPERATURE (°C)
-500
-70
-50
-30
-10
10
30
50
70
90
110
130
TEMPERATURE (°C)
FIGURE 8. IB- vs TEMPERATURE
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FN8653.0
ISL70419SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
500
500
VS = ±15V
300
300
200
200
100
100
0
-100
0
-100
-200
-200
-300
-300
-400
-400
-500
-70
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
VS = ±5V
400
IOS (pA)
IOS (pA)
400
-500
-70
130
-50
FIGURE 9. IOS vs TEMPERATURE
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
130
FIGURE 10. IOS vs TEMPERATURE
0.65
25000
0.60
VO = ±13V
0.50
AVOL (V/mV)
ISUPPLY (mA)
0.55
15V
0.45
5V
0.40
20000
15000
0.35
0.30
-70
-50
-30
-10
10
30
50
70
90
110
10000
-75
130
-50
-25
0
TEMPERATURE (°C)
25
50
75
100
125
150
TEMPERATURE (°C)
FIGURE 11. SUPPLY CURRENT PER AMP vs TEMPERATURE
FIGURE 12. AVOL vs TEMPERATURE
-120
-120
VS = ±2.25V TO ±20V
VCM = ±13V
-125
-130
CMRR (dB)
PSRR (dB)
-130
-135
-140
-140
-150
-145
-150
-70
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
FIGURE 13. PSRR vs TEMPERATURE
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90
110
130
-160
-70
-50
-30
-10
10
30
50
70
90
110
130
TEMPERATURE (°C)
FIGURE 14. CMRR vs TEMPERATURE
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ISL70419SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
-20
60
ISC+ AT ±15V
50
-30
45
-35
40
35
25
-55
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
-60
-70
130
-30
-10
10
30
50
70
90
110
130
FIGURE 16. SHORT CIRCUIT CURRENT vs TEMPERATURE
100
75
80
VOS(µ) -55°C
60
25
40
VOS (µV)
50
0
-25
VOSD(µ) +25°C
-50
+125°C
20
+25°C
0
-55°C
-20
VOSD(µ) +125°C
-75
-100
-50
TEMPERATURE (°C)
100
VOS (µV)
-45
-50
FIGURE 15. SHORT CIRCUIT CURRENT vs TEMPERATURE
-40
-15
-10
-5
0
VCM (V)
5
10
-60
-5
15
13.9
1
3
5
-13.1
VS = +15V
RL = 10kΩ
-13.2
-13.5
VOL (V)
-13.4
13.7
13.6
13.5
-13.6
-13.7
13.4
-13.8
13.3
-13.9
13.2
-14.0
-50
-30
VS = +15V
RL = 10kΩ
-13.3
13.8
13.1
-70
-1
FIGURE 18. INPUT VOS vs INPUT COMMON MODE VOLTAGE,
VS = ±5V
14.1
14.0
-3
VCM (V)
FIGURE 17. INPUT VOS vs INPUT COMMON MODE VOLTAGE,
VS = ±15
VOH (V)
-40
30
20
-70
ISC- AT ±15V
-25
ISC- (mA)
ISC+ (mA)
55
-10
10
30
50
70
TEMPERATURE (°C)
FIGURE 19. VOUT vs TEMPERATURE
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10
90
110
130
-14.1
-70
-50
-30
-10
10
30
50
70
90
110
130
TEMPERATURE (°C)
FIGURE 20. VOUT vs TEMPERATURE
July 11, 2014
FN8653.0
ISL70419SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
14.1
-13.1
14.0
13.9
-13.3
-13.4
13.8
-13.5
13.7
VOL (V)
VOH (V)
VS = +15V
RL = 2kΩ
-13.2
VS = +15V
RL = 2kΩ
13.6
13.5
-13.6
-13.7
-13.8
13.4
-13.9
13.3
-14.0
13.2
-14.1
13.1
-70
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
-14.2
-70
130
-10
INPUT NOISE VOLTAGE (nV/√Hz)
150
100
50
0
-50
-100
-150 V+ = 36.4V
-200 Rg = 10, Rf = 100k
50
70
90
110
130
AV = 10,000
0
1
2
3
4
5
6
7
8
9
VS = ±18.2V
AV = 1
10
1
10
1
10
FIGURE 23. INPUT NOISE VOLTAGE 0.1Hz to 10Hz
OPEN LOOP GAIN (dB) PHASE (°)
VS = ±18.2V
AV = 1
100
1k
FREQUENCY (Hz)
10k
FIGURE 25. INPUT NOISE CURRENT SPECTRAL DENSITY
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11
1k
10k
100k
FIGURE 24. INPUT NOISE VOLTAGE SPECTRAL DENSITY
1
10
100
FREQUENCY (Hz)
TIME (s)
INPUT NOISE CURRENT (pA/√Hz)
30
100
200
0.1
1
10
FIGURE 22. VOUT vs TEMPERATURE
250
INPUT NOISE VOLTAGE (nV)
-30
TEMPERATURE (°C)
FIGURE 21. VOUT vs TEMPERATURE
-250
-50
100k
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 10pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m
PHASE
GAIN
1
10
100
1k
10k 100k
1M 10M 100M
FREQUENCY (Hz)
FIGURE 26. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10k
CL = 10pF
July 11, 2014
FN8653.0
ISL70419SEH
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 100pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m 1
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
220
VS = ±2.5V
200
180
PHASE
VS = ±5V
160
CMRR (dB)
OPEN LOOP GAIN (dB) PHASE (°)
Typical Performance Curves
GAIN
140
120
VS = ±15V
100
80
60
RL = INF
40
CL = 10pF
SIMULATION
20
0
1m 10m 100m
10 100 1k 10k 100k 1M 10M 100M
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 27. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10k
CL = 100pF
FIGURE 28. CMRR vs FREQUENCY, VS = ±2.25, ±5V, ±15V
120
70
110
60
100
PSRR+ AND PSRR- VS = ±2.25V
90
RL = INF
CL = 4pF
40
AV = +1
30
VCM = 1VP-P
GAIN (dB)
PSRR (dB)
70
50
10
30
20
AV = 10
Rg = 10k, Rf = 100k
AV = 1
PSRR+ AND PSRR- VS = ±15V
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 29. PSRR vs FREQUENCY, VS = ±5V, ±15V
FIGURE 30. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
4
2
Rf = Rg = 100k
2
RL = 10k
1
0
0
Rf = Rg = 10k
-4
-1
GAIN (dB)
-2
Rf = Rg = 1k
-6
Rf = Rg = 100
-8 VS = ±20V
RL = 10k
-10
CL = 4pF
-12
AV = +2
-14 VOUT = 50mVP-P
-16
10
Rg = OPEN, Rf = 0
-10
10
10M
VS = ±20V
CL = 4pF
RL = 10k
VOUT = 50mVP-P
AV = 100
0
0
NORMALIZED GAIN (dB)
40
10
20
-10
Rg = 1k, Rf = 100k
50
80
60
Rg = 100, Rf = 100k
AV = 1000
100
-3
-6
-7
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 31. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE
Rf/Rg
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RL = 1k
-4
-5
1k
RL = 4.99k
-2
-8
10
VS = ±20V
RL = 499
CL = 4pF
AV = +1
RL = 100
VOUT = 50mVP-P
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 32. GAIN vs FREQUENCY vs RL
July 11, 2014
FN8653.0
ISL70419SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
12
2
VS = ±2.5V
RL = 10k
10
8
CL = 0.01µF
GAIN (dB)
GAIN (dB)
-1
4
2
CL = 47pF
0
-2
CL = 4pF
CL = 470pF
-6
CL = 1000pF
100
10k
1k
100k
1M
VS = ±15V
-2
-3
VS = ±20V
-4
-5 CL = 4pF
RL = 10k
-6
AV = +1
-7 V
OUT = 50mVP-P
CL = 100pF
CL = 270pF
-4
-8
10
VS = ±5V
0
AV = +1
VOUT = 50mVP-P
6
VS = ±2.25V
1
-8
10M
10
10k
1k
100k
FREQUENCY (Hz)
100
FREQUENCY (Hz)
FIGURE 33. GAIN vs FREQUENCY vs CL
LARGE SIGNAL TRANSIENT RESPONSE (V)
160
120
VS = ±15V
RL-DRIVER CH. = OPEN
60
RL-RECEIVING CH. = 10k
CL = 4pF
40
AV = +1
20
VSOURCE = 1VP-P
0
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 35. CROSSTALK, VS = ±15V
1.6
1.5
SLEW RATE (V/ µs)
1.4
SR+
1.3
1.2
1.1
SR-
1.0
0.9
0.8
0.6
-70
RL = 2k, 10k
CL = 7pF
AV = 1
VOUT = 4VP-P
VS = ±5V, ±15V
0.7
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
FIGURE 37. SLEW RATE vs TEMPERATURE VS = ±5V, ±15V
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2.4
2.0
1.6
1.2
VS = ±15V, RL = 2k, 10k
0.8
0.4
0
VS = ±5V, RL = 2k, 10k
-0.4
-0.8
CL = 4pF
AV = +1
VOUT = 4VP-P
-1.2
-1.6
-2.0
-2.4
0
10
20
30
40
50
60
TIME (µs)
70
80
90
100
FIGURE 36. LARGE SIGNAL TRANSIENT RESPONSE vs RL VS = ±5V,
±15V
130
SMALL SIGNAL TRANSIENT RESPONSE (mV)
CROSSTALK (dB)
140
80
10M
FIGURE 34. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
180
100
1M
60
50
40
VS =±5, ±15V
30
RL = 10k
CL = 4pF
AV = +1
VOUT = 50mVP-P
20
10
0
-10
0
5
10
15
20
25
TIME (µs)
30
35
40
FIGURE 38. SMALL SIGNAL TRANSIENT RESPONSE, VS = ±5V, ±15V
July 11, 2014
FN8653.0
ISL70419SEH
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
0
INPUT VOLTAGE (V)
-0.04
OUTPUT AT VS = ±15V
-0.08
-0.16
-0.20
-0.24
-0.28
10
20
30
40
12
0.20
10
0.16
6
4
2
0
OUTPUT AT VS= ±5V
0
0.24
8
RL = 2k
CL = 4pF
AV = -100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
-0.12
14
50
60
TIME (µs)
70
80
90
-2
100
0
RL = 2k
CL = 4pF
AV = -100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
0.12
0.08
0.04
-2
-4
-6
0
-8
-0.08
INPUT
OUTPUT AT VS = ±15V
-0.04
0
10
20
30
40
50
60
-10
70
80
90
-12
100
FIGURE 40. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V, ±15V
80
6
VS = ±15V
RL = 10k
AV = 1
VOUT = 50mVP-P
60
5
4
3
O
SH
O
O
T
VE
R
40
-
SH
O
O
T
+
50
VIN and VOUT (V)
70
VE
R
30
20
2
VOUT AT -55°C
1
0
-1
-2
VOUT AT +125°C
-4
10
-5
1
10
100
1k
10k
100k
CAPACITANCE (pF)
FIGURE 41. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V
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-6
RL = 10k
CL = 7pF
AV = 1
VIN = ±5.9VP-P
VOUT AT +25°C
-3
O
OVERSHOOT (%)
2
OUTPUT AT VS = ±5V
TIME (µs)
FIGURE 39. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V, ±15V
0
4
OUTPUT VOLTAGE (V)
INPUT
INPUT VOLTAGE (V)
0.04
OUTPUT VOLTAGE (V)
Typical Performance Curves
VS = ±5V
VIN
0
0.2
0.4
0.6
0.8
1.0 1.2
TIME (ms)
1.4
1.6
1.8
2.0
FIGURE 42. OUTPUT PHASE REVERSAL RESPONSE vs TEMPERATURE
July 11, 2014
FN8653.0
ISL70419SEH
Post High Dose Radiation Characteristics Unless otherwise specified, VS ± 15V, VCM = 0, VO = 0V, TA = +25°C. This data is
typical mean test data post radiation exposure at a high dose rate of 50 - 300rad(Si)/s. This data is intended to show typical parameter shifts due to high
dose rate radiation. These are not limits nor are they guaranteed.
25
3
20
15
10
1
VOS (µV)
SUPPLY CURRENT (mA)
2
0
-1
ICC HDR BIASED
IEE HDR BIASED
ICC HDR GROUNDED
IEE HDR GROUNDED
5
0
-5
CHA HDR BIASED
CHB HDR BIASED
CHC HDR BIASED
CHD HDR BIASED
-10
-15
-2
-20
-3
0
50
100
150
200
250
-25
300
0
50
100
krad(Si)
4
4
3
3
2
2
1
1
IB- (nA)
IB+ (nA)
5
0
-1
-3
-4
-5
50
100
250
300
CHA HDR GROUNDED
CHB HDR GROUNDED
CHC HDR GROUNDED
CHD HDR GROUNDED
0
-1
-2
150
200
250
-4
300
CHA HDR GROUNDED
CHB HDR GROUNDED
CHC HDR GROUNDED
CHD HDR GROUNDED
CHA HDR BIASED
CHB HDR BIASED
CHC HDR BIASED
CHD HDR BIASED
-3
-5
0
200
FIGURE 44. VOS vs HIGH DOSE RATE RADIATION
5
CHA HDR BIASED
CHB HDR BIASED
CHC HDR BIASED
CHD HDR BIASED
150
krad(Si)
FIGURE 43. SUPPLY CURRENT vs HIGH DOSE RATE RADIATION
-2
CHA HDR GROUNDED
CHB HDR GROUNDED
CHC HDR GROUNDED
CHD HDR GROUNDED
0
50
100
150
200
250
300
krad(Si)
krad(Si)
FIGURE 45. IB+ vs HIGH DOSE RATE RADIATION
FIGURE 46. IB- vs HIGH DOSE RATE RADIATION
5
4
3
IOS (nA)
2
1
0
-1
CHA HDR GROUNDED
CHB HDR GROUNDED
CHC HDR GROUNDED
CHD HDR GROUNDED
CHA HDR BIASED
CHB HDR BIASED
CHC HDR BIASED
CHD HDR BIASED
-2
-3
-4
-5
0
50
100
150
200
250
300
krad(Si)
FIGURE 47. IOSvs HIGH DOSE RATE RADIATION
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FN8653.0
ISL70419SEH
2.5
50
2.0
40
1.5
30
ICC GROUNDED
ICC BIASED
1.0
20
0.5
VOS (µV)
SUPPLY CURRENT (mA)
Post Low Dose Radiation Characteristics Unless otherwise specified, VS ± 15V, VCM = 0, VO = 0V, TA = +25°C. This data is
typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low
dose rate radiation. These are not limits nor are they guaranteed
0
-0.5
0
-10
-1.0
CHA BIASED
CHC BIASED
CHA GROUNDED
CHC GROUNDED
-20
IEE GROUNDED
IEE BIASED
-1.5
-30
-2.0
-2.5
10
-40
0
10
20
30
40
-50
50
krad(Si)
0
10
10
5
5
IB- (nA)
IB+ (nA)
15
0
CHB BIASED
CHD BIASED
CHA BIASED
CHC BIASED
CHA GROUNDED
CHC GROUNDED
-10
0
10
30
40
50
30
40
0
CHA BIASED
CHC BIASED
CHA GROUNDED
CHC GROUNDED
-5
CHB GROUNDED
CHD GROUNDED
20
20
FIGURE 49. VOS vs LOW DOSE RATE RADIATION
15
-5
10
krad(Si)
FIGURE 48. SUPPLY CURRENT vs LOW DOSE RATE RADIATION
-15
CHB BIASED
CHD BIASED
CHB GROUNDED
CHD GROUNDED
-10
-15
50
krad(Si)
0
10
20
CHB BIASED
CHD BIASED
CHB GROUNDED
CHD GROUNDED
30
40
50
krad(Si)
FIGURE 50. IB+ vs LOW DOSE RATE RADIATION
FIGURE 51. IB- vs LOW DOSE RATE RADIATION
10
8
6
IOS (nA)
4
2
0
-2
CHB BIASED
CHD BIASED
CHA BIASED
CHC BIASED
CHA GROUNDED
CHC GROUNDED
-4
-6
CHB GROUNDED
CHD GROUNDED
-8
-10
0
10
20
30
40
50
krad(Si)
FIGURE 52. IOS vs LOW DOSE RATE RADIATION
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Applications Information
V+
Functional Description
The ISL70419SEH contains four, low noise precision op amps.
These devices are fabricated in a new precision 40V
complementary bipolar DI process. A super-beta NPN input stage
with input bias current cancellation provides low input bias
current (180pA typical), low input offset voltage (13µV typical),
low input noise voltage (8nV/Hz), and low 1/f noise corner
frequency (~8Hz). These amplifiers also feature high open loop
gain (14kV/mV) for excellent CMRR (145dB) and THD+N
performance (0.0005% at 3.5VRMS, 1kHz into 2k). A
complementary bipolar output stage enables high capacitive
load drive without external compensation.
Operating Voltage Range
The devices are designed to operate over the 4.5V (±2.25V) to
36V (±18V) voltage range and are fully characterized at 10V
(±5V) and 30V (±15V). The Power Supply Rejection Ratio typically
exceeds 140dB over the full operating voltage range and 120dB
minimum over the -55°C to +125°C temperature range. The
worst case common mode input voltage range over-temperature
is 2V to each rail. With ±15V supplies, CMRR performance is
typically >130dB over-temperature. The minimum CMRR
performance over the -55°C to +125°C temperature range is
>120dB for power supply voltages from ±5V (10V) to ±15V (30V).
Input Performance
The super-beta NPN input pair provides excellent frequency
response while maintaining high input precision. High NPN beta
(>1000) reduces input bias current while maintaining good
frequency response, low input bias current and low noise. Input
bias cancellation circuits provide additional bias current
reduction to <5nA, and excellent temperature stabilization.
Figures 6 through 8 show the high degree of bias current stability
at ±5V and ±15V supplies that is maintained across the -55°C to
+125°C temperature range. The low bias current TC also
produces very low input offset current TC, which reduces DC
input offset errors in precision, high impedance amplifiers.
The +25°C maximum input offset voltage (VOS) is 75µV at ±15V
supplies. Input offset voltage temperature coefficients (VOSTC) is a
maximum of ±1.0µV/°C. The VOS temperature behavior is smooth
(Figures 3 through 4) maintaining constant TC across the entire
temperature range.
- 500
VIN
+ 500
VOUT
RL
V-
FIGURE 53. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
The series resistors limit the high feed-through currents that can
occur in pulse applications when the input dV/dT exceeds the
0.5V/µs slew rate of the amplifier. Without the series resistors, the
input can forward-bias the anti-parallel diodes causing current to
flow to the output resulting in severe distortion and possible diode
failure.
Figure 36 provides an example of distortion free large signal
response using a 4VP-P input pulse with an input rise time of <1ns.
The series resistors enable the input differential voltage to be
equal to the maximum power supply voltage (36V) without
damage.
In applications where one or both amplifier input terminals are at
risk of exposure to high voltages beyond the power supply rails,
current limiting resistors may be needed at the input terminal to
limit the current through the power supply ESD diodes to 20mA
max.
Output Current Limiting
The output current is internally limited to approximately ±45mA
at +25°C and can withstand a short circuit to either rail as long
as the power dissipation limits are not exceeded. This applies to
only 1 amplifier at a time for the quad op amp. Continuous
operation under these conditions may degrade long term
reliability. Figures 15 and Figure 16 on page 10 show the current
limit variation with temperature.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL70419SEH is immune to output phase reversal,
even when the input voltage is 1V beyond the supplies.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, series connected
500 current limiting resistors and an anti-parallel diode pair
across the inputs (Figure 53).
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Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
T JMAX = T MAX +  JA xPD MAXTOTAL
(EQ. 1)
where:
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated using Equation 2:
V OUTMAX
PD MAX = V S  I qMAX +  V S - V OUTMAX   ---------------------------RL
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the application
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ISL70419SEH
Package Characteristics
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 30kÅ
Weight of Packaged Device
0. 6043 Grams (Typical)
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Potential: Unbiased; tied to EPAD
Case Isolation to Any Lead: 20 x 109 Ω (min)
PROCESS
Dielectrically Isolated Complementary Bipolar - PR40
ASSEMBLY RELATED INFORMATION
Die Characteristics
SUBSTRATE POTENTIAL
Die Dimensions
Floating
2406µm x 2935µm (95mils x 116mils)
Thickness: 483µm ± 25µm (19mils ± 1 mil)
ADDITIONAL INFORMATION
Interface Materials
WORST CASE CURRENT DENSITY
< 2 x 105 A/cm2
GLASSIVATION
Type: Nitrox
Thickness: 15kÅ
Metallization Mask Layout
-IN_A
OUT_A
OUT_D
-IN_D
+IN_A
+IN_D
PLACE HOLDER
V+
V-
+IN_B
+IN_C
-IN_B
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19
OUT_B
OUT_C
-IN_C
July 11, 2014
FN8653.0
ISL70419SEH
TABLE 1. DIE LAYOUT X-Y COORDINATES
PAD NAME
PAD NUMBER
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
BOND WIRES
PER PAD
OUT_A
3
-445.5
1308.5
70
70
1
-IN_A
4
-815
1308.5
70
70
1
+IN_A
5
-1040.5
1092
70
70
1
V+
9
-1044
0
70
70
1
+IN_B
13
-1040.5
-1092
70
70
1
-IN_B
14
-815
-1308.5
70
70
1
OUT_B
15
-445.5
-1308.5
70
70
1
OUT_C
16
445.5
-1308.5
70
70
1
-IN_C
17
815
-1308.5
70
70
1
+IN_C
18
1040.5
-1092
70
70
1
V-
22
1044
0
70
70
1
+IN_D
26
1040.5
1092
70
70
1
-IN_D
1
815
1308.5
70
70
1
OUT_D
2
445.5
1308.5
70
70
1
NOTE:
6. Origin of coordinates is the center of die.
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July 11, 2014
FN8653.0
ISL70419SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Revision.
DATE
REVISION
July 11, 2014
FN8653.1
CHANGE
Modified in Features on page 1
SEL/SEB LETTH (VS = ±36V). . . . . . . . . 86.4 MeV•cm2/mg
to
SEB LETTH (VS = ±18V). . . . . . . . . 86.4 MeV•cm2/mg
Added in Features on page 1
"SEL Immune (SOI Process)"
under in the radiation environment section
June 24, 2014
FN8653.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
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FN8653.0
ISL70419SEH
Package Outline Drawing
K14.C
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 0, 9/12
A
A
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.390 (9.91)
0.376 (9.55)
1
TOP VIEW
0.022 (0.56)
0.005 (0.13)
MIN
3
0.015 (0.38)
0.115 (2.92)
0.009 (0.23)
0.045 (1.14)
0.085 (2.16)
0.026 (0.66)
5
0.260 (6.60)
0.248 (6.30)
-C-
BOTTOM
METAL
0.183 (4.65)
0.370 (9.40)
0.167 (4.24)
0.270 (6.86)
-H-
0.03 (0.76) MIN
6
SEATING AND
BASE PLANE
0.004 (0.10)
-D-
SIDE VIEW
BOTTOM METAL
0.005 (0.127) REF.
OFFSET FROM
CERAMIC EDGE
OPTIONAL
PIN 1 INDEX
BOTTOM VIEW
NOTES:
0.006 (0.15)
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark.
LEAD FINISH
0.004 (0.10)
2. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
BASE
METAL
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
22
0.004 (0.10)
4. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. The bottom of the package is a solderable metal surface.
2
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3. Measure dimension at all four corners.
5. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
0.022 (0.56)
0.015 (0.38)
SECTION A-A
0.009 (0.23)
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Dimensions: INCH (mm). Controlling dimension: INCH.
July 11, 2014
FN8653.0