LTC3899 - 60V Low IQ, Triple Output, Buck/Buck/Boost Synchronous Controller

LTC3899
60V Low IQ, Triple
Output, Buck/Buck/Boost
Synchronous Controller
DESCRIPTION
FEATURES
Dual Buck Plus Single Boost Synchronous Controllers
n Wide Bias Input Voltage Range: 4.5V to 60V
n Outputs Remain in Regulation Through Cold Crank
Down to a 2.2V Input Supply Voltage
n Buck and Boost Output Voltages Up to 60V
n Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE)
n No External Bootstrap Diodes Required
n Low Operating I : 29μA (One Channel On)
Q
n100% Duty Cycle for Boost Synchronous MOSFET
n Phase-Lockable Frequency (75kHz to 850kHz)
n Programmable Fixed Frequency (50kHz to 900kHz)
n Very Low Dropout Operation: 99% Duty Cycle (Bucks)
n Low Shutdown I : 3.6μA
Q
n Fixed or Adjustable Boost Output Voltage Saves I
Q
n Small 38-Lead 5mm × 7mm QFN and TSSOP Packages
The LTC®3899 is a high performance triple output (buck/
buck/boost) DC/DC switching regulator controller that
drives all N-channel synchronous power MOSFET stages.
The constant frequency current mode architecture allows
a phase-lockable frequency of up to 850kHz. The LTC3899
operates from a wide 4.5V to 60V input supply range.
When biased from the output of the boost converter or
another auxiliary supply, the LTC3899 can operate from
an input supply as low as 2.2V after start-up.
n
The gate drive for the LTC3899 can be programmed from
5V to 10V to allow the use of logic-level or standard-level
FETs and to maximize efficiency. Internal switches in the
top gate drivers eliminate the need for external bootstrap
diodes. The 29μA no-load quiescent current extends operating run time in battery-powered systems. OPTI-LOOP®
compensation allows the transient response to be optimized
over a wide range of output capacitance and ESR values.
APPLICATIONS
Automotive Always-On and Start-Stop Systems
Distributed DC Power Systems
n Multioutput Buck-Boost Applications
n
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620,
6144194, 6177787, 6580258.
n
TYPICAL APPLICATION
High Efficiency Wide Input Range Dual 5V/8.5V Converter
VOUT3
REGULATED AT 10V
WHEN VIN < 10V
FOLLOWS VIN WHEN
VIN > 10V
95
RUN1, 2, 3 VBIAS
TG1
VFB3
3mΩ
TG3
SW3
33µF
BG3
0.1µF
4.9µH
SW1
9mΩ
BG1
VOUT1
5V
5A
LTC3899
SENSE3–
SENSE3+
4.7µF
0.1µF
BOOST1
BOOST3
1.2µH
VIN = 12V
VOUT = 5V
94 Burst Mode OPERATION
SENSE1+
SENSE1–
357k
VFB1
68.1k
DRVCC
INTVCC
ITH1,2,3 BOOST2
SW2
0.1µF
6.5µH
BG2
VPRG3
92
91
90
89
TG2
DRVSET
220µF
93
EFFICIENCY (%)
33µF
0.1µF
VIN
2.2V TO 60V
(START-UP
ABOVE 5V)
Efficiency vs Output Current
SENSE2+
SENSE2–
GND
VFB2
15mΩ
VOUT2
8.5V
3A
88
0.01
GATE DRIVE (DRVCC)
5V
6V
8V
10V
0.1
1
OUTPUT CURRENT(A)
10
3899 TA01b
649k
68.1k
68µF
3899 TA01a
3899fa
For more information www.linear.com/LTC3899
1
LTC3899
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 3)
Bias Input Supply Voltage (VBIAS)............... –0.3V to 65V
Topside Driver Voltages
BOOST1, BOOST2, BOOST3................... –0.3V to 76V
Switch Voltage (SW1, SW2, SW3)................. –5V to 70V
DRVCC, (BOOST1-SW1), (BOOST2-SW2),
(BOOST3-SW3)............................................–0.3V to 11V
BG1, BG2, BG3, TG1, TG2, TG3........................... (Note 8)
RUN1, RUN2, RUN3 Voltages...................... –0.3V to 65V
SENSE1+, SENSE2+, SENSE1–
SENSE2– Voltages...................................... –0.3V to 65V
SENSE3+, SENSE3– Voltages...................... –0.3V to 65V
PLLIN/MODE, FREQ, DRVSET Voltages........ –0.3V to 6V
EXTVCC Voltage.......................................... –0.3V to 14V
ITH1, ITH2, ITH3, VFB1, VFB2 Voltages.......... –0.3V to 6V
VFB3 Voltage............................................... –0.3V to 65V
VPRG3, Voltage............................................ –0.3V to 6V
TRACK/SS1, TRACK/SS2, SS3 Voltages....... –0.3V to 6V
Operating Junction Temperature Range (Note 2)
LTC3899E, LTC3899I.......................... –40°C to 125°C
LTC3899H........................................... –40°C to 150°C
LTC3899MP........................................ –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
36 TG1
SENSE1–
4
35 SW1
FREQ
5
34 BOOST1
PLLIN/MODE
6
33 BG1
SS3
7
32 SW3
SENSE3+
8
31 TG3
SENSE3–
9
30 BOOST3
VFB3 10
ITH3 11
39
GND
38 37 36 35 34 33 32
29 BG3
31 SW1
FREQ 1
30 BOOST1
PLLIN/MODE 2
SS3 3
29 BG1
SENSE3+ 4
28 SW3
SENSE3– 5
27 TG3
VFB3 6
28 VBIAS
INTVCC 12
27 EXTVCC
RUN1 13
26 BOOST3
39
GND
ITH3 7
25 BG3
INTVCC 8
24 VBIAS
RUN1 9
23 EXTVCC
26 DRVCC
RUN2 10
22 DRVCC
RUN2 14
25 BG2
RUN3 11
21 BG2
RUN3 15
24 BOOST2
20 DRVSET
TJMAX = 150°C, θJA = 25°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
SW2
TG2
TRACK/SS2
21 TRACK/SS2
ITH2 19
ITH2
22 TG2
VFB2 18
DRVSET
SENSE2+ 17
20 BOOST2
13 14 15 16 17 18 19
VFB2
23 SW2
SENSE2– 12
SENSE2+
SENSE2– 16
FE PACKAGE
38-LEAD PLASTIC TSSOP
2
TG1
37 TRACK/SS1
3
VPRG3
2
ITH1
VFB1
SENSE1+
TOP VIEW
VFB1
38 VPRG3
SENSE1+
1
SENSE1–
ITH1
TRACK/SS1
TOP VIEW
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 150°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
3899fa
For more information www.linear.com/LTC3899
LTC3899
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
LTC3899EFE#PBF
LTC3899EFE#TRPBF
LTC3899IFE#PBF
LTC3899IFE#TRPBF
LTC3899HFE#PBF
LTC3899HFE#TRPBF
LTC3899MPFE#PBF
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3899FE
38-Lead Plastic TSSOP
–40°C to 125°C
LTC3899FE
38-Lead Plastic TSSOP
–40°C to 125°C
LTC3899FE
38-Lead Plastic TSSOP
–40°C to 150°C
LTC3899MPFE#TRPBF
LTC3899FE
38-Lead Plastic TSSOP
–55°C to 150°C
LTC3899EUHF#PBF
LTC3899EUHF#TRPBF
3899
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 125°C
LTC3899IUHF#PBF
LTC3899IUHF#TRPBF
3899
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 125°C
LTC3899HUHF#PBF
LTC3899HUHF#TRPBF
3899
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 150°C
LTC3899MPUHF#PBF
LTC3899MPUHF#TRPBF
3899
38-Lead (5mm × 7mm) Plastic QFN
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VBIAS = 12V, VRUN1,2,3 = 5V, VEXTVCC = 0V, VDRVSET =
0V, VPRG3 = Float unless otherwise noted.
SYMBOL
PARAMETER
VBIAS
Bias Input Supply Operating Voltage Range
VFB1,2
Buck Regulated Feedback Voltage
VFB3
Boost Regulated Feedback Voltage
CONDITIONS
MIN
TYP
4.5
(Note 4) ITH1,2 Voltage = 1.2V
0°C to 85°C
(Note 4) ITH3 Voltage = 1.2V
VPRG3 = FLOAT
VPRG3 = 0V
VPRG3 = INTVCC
MAX
UNITS
60
V
l
0.792
0.788
0.800
0.800
0.808
0.812
V
V
l
l
l
1.182
9.78
11.74
1.200
10.00
12.00
1.218
10.22
12.26
V
V
V
IFB1,2
Buck Feedback Current
(Note 4)
–2
±50
nA
IFB3
Boost Feedback Current
(Note 4)
VPRG3 = FLOAT
VPRG3 = 0V
VPRG3 = INTVCC
±0.01
4
5
±0.05
6
7
µA
µA
µA
VREFLNREG
Reference Voltage Line Regulation
(Note 4) VBIAS = 4.5V to 60V
0.002
0.02
%/V
VLOADREG
Output Voltage Load Regulation
(Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 0.7V
l
0.01
0.1
%
(Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 2V
l
–0.01
–0.1
%
gm1,2,3
Transconductance Amplifier gm
(Note 4) ITH1,2,3 = 1.2V, Sink/Source 5µA
2
mmho
3899fa
For more information www.linear.com/LTC3899
3
LTC3899
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VBIAS = 12V, VRUN1,2,3 = 5V, VEXTVCC = 0V, VDRVSET =
0V, VPRG3 = Float unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
IQ
Input DC Supply Current
(Note 5), VDRVSET = 0V
Pulse-Skipping or Forced Continuous Mode
(One Channel On)
RUN1 = 5V and RUN2,3 = 0V or
RUN2 = 5V and RUN1,3 = 0V or
RUN3 = 5V and RUN1,2 = 0V,
VFB1,2 = 0.83V (No Load), VFB3 = 1.25V
Pulse-Skipping or Forced Continuous Mode
(All Channels On)
RUN1,2,3 = 5V, VFB1,2 = 0.83V (No Load),
VFB3 = 1.25V
Sleep Mode (One Channel On, Buck)
RUN1 = 5V and RUN2,3 = 0V or
RUN2 = 5V and RUN1,3 = 0V
VFB1,2 = 0.83V (No Load)
Sleep Mode (One Channel On, Boost)
Sleep Mode (Buck and Boost Channel On)
UVLO
MIN
TYP
MAX
UNITS
1.6
1.6
0.8
mA
3
mA
29
55
µA
RUN3 = 5V and RUN1,2 = 0V, VFB3 = 1.25V
29
50
µA
RUN1 = 5V and RUN2 = 0V or
RUN2 = 5V and RUN1 = 0V, RUN3 = 5V,
VFB1,2 = 0.83V (No Load), VFB3 = 1.25V
34
55
µA
Sleep Mode (All Three Channels On)
RUN1,2,3 = 5V, VFB1,2 = 0.83V (No Load),
VFB3 = 1.25V
39
60
µA
Shutdown
RUN1,2,3 = 0V
3.6
10
µA
Undervoltage Lockout
DRVCC Ramping Up
DRVSET = 0V or RDRVSET ≤ 100kΩ
DRVSET = INTVCC
l
l
4.0
7.5
4.2
7.8
V
V
DRVCC Ramping Down
DRVSET = 0V or RDRVSET ≤ 100kΩ
DRVSET = INTVCC
l
l
3.6
6.4
3.8
6.7
4.0
7.0
V
V
7
10
13
%
±1
µA
l
VOVL1,2
Buck Feedback Overvoltage Protection
Measured at VFB1,2 Relative to Regulated VFB1,2
ISENSE1,2+
SENSE+ Pin Current
Bucks (Channels 1 and 2)
ISENSE3+
SENSE+ Pin Current
Boost (Channel 3)
170
ISENSE1,2–
SENSE– Pins Current
Bucks (Channels 1 and 2)
VOUT1,2 < VINTVCC – 0.5V
VOUT1,2 > VINTVCC + 0.5V
700
ISENSE3–
SENSE– Pin Current
Boost (Channel 3) VSENSE+, VSENSE– = 12V
DFMAX(TG)
Maximum Duty Factor for TG
Bucks (Channels 1,2) in Dropout, FREQ = 0V
Boost (Channel 3) in Overvoltage
DFMAX(BG)
Maximum Duty Factor for BG
Bucks (Channels 1,2) in Overvoltage
Boost (Channel 3)
ITRACK/SS1,2
Soft-Start Charge Current
VTRACK/SS1,2 = 0V
ISS
Soft-Start Charge Current
VSS3 = 0V
VRUN1,2,3 ON
RUN Pin On Threshold
VRUN1, VRUN2, VRUN3 Rising
l
VFB1,2 = 0.7V, VSENSE1,2– = 3.3V,
VFB3 = 1.1V, VSENSE3+ = 12V
l
97.5
8
µA
±1
µA
µA
±1
µA
99
100
%
%
100
96
%
%
10
12
µA
8
10
12
µA
1.22
1.275
1.33
V
VRUN1,2,3 Hyst RUN Pin Hysteresis
75
VSENSE(MAX)
Maximum Current Sense Threshold
VSENSE(CM)
SENSE3 Pins Common Mode Range
(BOOST Converter Input Supply Voltage)
65
75
2.2
mV
85
mV
60
V
Gate Driver
TG1,2,3
Pull-Up On-Resistance
Pull-Down On-Resistance
VDRVSET = INTVCC
2.2
1.0
Ω
Ω
BG1,2,3
Pull-Up On-Resistance
Pull-Down On-Resistance
VDRVSET = INTVCC
2.2
1.0
Ω
Ω
4
3899fa
For more information www.linear.com/LTC3899
LTC3899
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VBIAS = 12V, VRUN1,2,3 = 5V, VEXTVCC = 0V, VDRVSET =
0V, VPRG3 = Float unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
BDSW1,2,3
BOOST to DRVCC Switch On-Resistance
VSW = 0V, VDRVSET = INTVCC
MIN
TYP
3.7
MAX
UNITS
Ω
TG1,2,3 tr
TG1,2,3 tf
TG Transition Time:
Rise Time
Fall Time
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
BG1,2,3 tr
BG1,2,3 tf
BG Transition Time:
Rise Time
Fall Time
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
TG1,2/BG1,2
t1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC
55
ns
BG1,2/TG1,2
t1D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC
50
ns
TG3/BG3 t1D
CH3 Top Gate Off to Bottom Gate On Delay
Bottom Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC
85
ns
BG3/TG3 t1D
CH3 Bottom Gate Off to Top Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC
80
ns
tON(MIN)1,2
Buck Minimum On-Time
(Note 7) VDRVSET = INTVCC
80
ns
tON(MIN)3
Boost Minimum On-Time
(Note 7) VDRVSET = INTVCC
120
ns
DRVCC Linear Regulator
VDRVCC(INT)
DRVCC Voltage from Internal VBIAS LDO
VEXTVCC = 0V
7V < VBIAS < 60V, DRVSET = 0V
11V < VBIAS < 60V, DRVSET = INTVCC
VLDOREG(INT)
DRVCC Load Regulation from VBIAS LDO
ICC = 0mA to 50mA, VEXTVCC = 0V
VDRVCC(EXT)
DRVCC Voltage from Internal EXTVCC LDO
7V < VEXTVCC < 13V, DRVSET = 0V
11V < VEXTVCC < 13V, DRVSET = INTVCC
VLDOREG(EXT)
DRVCC Load Regulation from Internal
EXTVCC LDO
ICC = 0mA to 50mA, VEXTVCC = 8.5V,
VDRVSET = 0V
VEXTVCC
EXTVCC LDO Switchover Voltage
EXTVCC Ramping Positive
DRVSET = 0V or RDRVSET ≤ 100kΩ
DRVSET = INTVCC
VLDOHYS
EXTVCC Hysteresis
VDRVCC(50kΩ)
Programmable DRVCC
RDRVSET = 50kΩ, VEXTVCC = 0V
VDRVCC(70kΩ)
Programmable DRVCC
RDRVSET = 70kΩ, VEXTVCC = 0V
VDRVCC(90kΩ)
Programmable DRVCC
RDRVSET = 90kΩ, VEXTVCC = 0V
9.0
V
105
kHz
5.8
9.6
5.8
9.6
4.5
7.4
6.4
6.0
10.0
6.2
10.4
V
V
0.9
2.0
%
6.0
10.0
6.2
10.4
V
V
0.7
2.0
%
4.7
7.7
4.9
8.0
V
V
250
mV
5.0
V
7.0
7.6
V
Oscillator and Phase-Locked Loop
f25kΩ
Programmable Frequency
RFREQ =25kΩ, PLLIN/MODE = DC Voltage
f65kΩ
Programmable Frequency
RFREQ = 65kΩ, PLLIN/MODE = DC Voltage
f105kΩ
Programmable Frequency
RFREQ = 105kΩ, PLLIN/MODE = DC Voltage
fLOW
Low Fixed Frequency
VFREQ = 0V, PLLIN/MODE = DC Voltage
fHIGH
High Fixed Frequency
VFREQ = INTVCC, PLLIN/MODE = DC Voltage
fSYNC
Synchronizable Frequency
PLLIN VIH
PLLIN VIL
PLLIN/MODE Input High Level
PLLIN/MODE Input Low Level
375
440
505
835
kHz
kHz
320
350
380
kHz
485
535
585
kHz
850
kHz
0.5
V
V
PLLIN/MODE = External Clock
l
75
PLLIN/MODE = External Clock
PLLIN/MODE = External Clock
l
l
2.5
BOOST3 Charge Pump
IBST3
BOOST3 Charge Pump Available Output
Current
FREQ = 0V, PLLIN/MODE = INTVCC
VBOOST3 = 16.5V, VSW3 = 12V
VBOOST3 = 19V, VSW3 = 12V
75
35
µA
µA
3899fa
For more information www.linear.com/LTC3899
5
LTC3899
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Ratings for extended periods may affect device reliability and
lifetime.
Note 2: The LTC3899 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3899E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3899I is guaranteed
over the –40°C to 125°C operating junction temperature range, the
LTC3899H is guaranteed over the –40°C to 150°C operating junction
temperature range, and the LTC3899MP is tested and guaranteed over
the –55°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors. The junction
temperature (TJ, in °C) is calculated from the ambient temperature
(TA, in °C) and power dissipation (PD, in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA = 34°C/W for the QFN package and where θJA = 25°C/W for the
TSSOP package.
6
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC3899 is tested in a feedback loop that servos VITH1,2,3 to a
specified voltage and measures the resultant VFB1,2,3. The specification at
85°C is not tested in production and is assured by design, characterization
and correlation to production testing at other temperatures (125°C for
the LTC3899E and LTC3899I, 150°C for the LTC3899H and LTC3899MP).
For the LTC3899I and LTC3899H, the specification at 0°C is not tested in
production and is assured by design, characterization and correlation to
production testing at –40°C. For the LTC3899MP, the specification at 0°C
is not tested in production and is assured by design, characterization and
correlation to production testing at –55°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current >40% of IMAX (See Minimum On-Time
Considerations in the Applications Information section).
Note 8: Do not apply a voltage or current source to these pins. They must be
connected to capacitive loads only, otherwise permanent damage may occur.
3899fa
For more information www.linear.com/LTC3899
LTC3899
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current (Buck)
FCM LOSS
70
60
50
PULSE-SKIPPING
LOSS
100
BURST LOSS
PULSE-SKIPPING
40 EFFICIENCY
FCM EFFICIENCY
30
20
FIGURE 12 CIRCUIT
VIN = 10V
VOUT = 5V
10
0
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
10
96
VIN = 10V
VIN = 20V
VIN = 30V
70
60
50
40
30
20
1
10
90
80
1000
POWER LOSS (mW)
EFFICIENCY (%)
80
98
0
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
3899 G01
88
86
VOUT
100mV/DIV
AC COUPLED
IL
2A/DIV
IL
2A/DIV
3899 G04
Inductor Current at Light Load
(Buck)
80
10
10
20
30
40
INPUT VOLTAGE (V)
50
60
3899 G03
VOUT
100mV/DIV
AC COUPLED
IL
2A/DIV
50µs/DIV
VIN = 12V
VOUT = 5V
FIGURE 12 CIRCUIT
50µs/DIV
VIN = 12V
VOUT = 5V
FIGURE 12 CIRCUIT
3899 G05
RUN1, 2
5V/DIV
VOUT2
2V/DIV
Burst Mode
OPERATION
1A/DIV
VOUT1
2V/DIV
PULSESKIPPING
MODE
2ms/DIV
FIGURE 12 CIRCUIT
3899 G06
Buck Regulated Feedback Voltage
vs Temperature
FORCED
CONTINUOUS
MODE
3899 G07
0
Load Step (Buck)
Forced Continuous Mode
Soft Start-Up (Buck)
2µs/DIV
FIGURE 12 CIRCUIT
VOUT = 5V
ILOAD = 4A
82
Load Step (Buck)
Pulse-Skipping Mode
VOUT
100mV/DIV
AC COUPLED
VIN = 12V
VOUT = 5V
ILOAD = 1mA
FIGURE 12 CIRCUIT
90
3899 G02
Load Step (Buck)
Burst Mode Operation
50µs/DIV
VIN = 12V
VOUT = 5V
FIGURE 12 CIRCUIT
DRVSET = INTVCC
DRVSET = 0V
92
84
FIGURE 12 CIRCUIT
VOUT = 5V
Burst Mode OPERATION
10
0.1
94
EFFICIENCY (%)
BURST EFFICIENCY
Efficiency vs Input Voltage (Buck)
100
3899 G08
808
REGULATED FEEDBACK VOLTAGE (mV)
90
10000
EFFICIENCY (%)
100
Efficiency
vs Output Current (Buck)
806
804
802
800
798
796
794
792
-75 -50 -25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3899 G09
3899fa
For more information www.linear.com/LTC3899
7
LTC3899
TYPICAL PERFORMANCE CHARACTERISTICS
EFFICIENCY (%)
60
50
40
30
100
PULSE-SKIPPING
LOSS
10
BURST
LOSS
VIN = 5V
1
VOUT = 10V
20
10
0
0.0001
FCM EFFICIENCY
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
10
1.35
96
1000
POWER LOSS (mW)
70
1.4
DRVSET = INTVCC
DRVSET = 0V
98
FCM LOSS
PULSE-SKIPPING
EFFICIENCY
80
100
10000
BURST EFFICIENCY
Shutdown (RUN) Threshold
vs Temperature
Efficiency
vs Input Voltage (Boost)
RUN PIN VOLTAGE (V)
90
EFFICIENCY (%)
100
Efficiency and Power Loss
vs Output Current (Boost)
94
92
90
88
86
84
FIGURE 12 CIRCUIT
VOUT = 10V
ILOAD = 2A
82
80
0.1
2
4
6
8
INPUT VOLTAGE (V)
10
1.25
1.2
1.1
1.05
1
-75 -50 -25
12
Load Step (Boost)
Burst Mode Operation
VOUT
500mV/DIV
AC COUPLED
VOUT
500mV/DIV
AC COUPLED
IL
5A/DIV
IL
5A/DIV
IL
5A/DIV
100µs/DIV
VIN = 5V
VOUT = 10V
FIGURE 12 CIRCUIT
Inductor Current at Light Load
(Boost)
0 25 50 75 100 125 150
TEMPERATURE (°C)
3899 G12
Load Step (Boost)
Pulse-Skipping Mode
3899 G13
FALLING
1.15
VOUT
500mV/DIV
AC COUPLED
100µs/DIV
VIN = 5V
VOUT = 10V
FIGURE 12 CIRCUIT
RISING
3899 G11
3899 G10
Load Step (Boost)
Forced Continuous Mode
1.3
100µs/DIV
VIN = 5V
VOUT = 10V
FIGURE 12 CIRCUIT
3899 G14
3899 G15
Boost Regulated Feedback
Voltage vs Temperature
Soft Start-Up (Boost)
RUN3
5V/DIV
FORCED
CONTINUOUS
MODE
Burst Mode
OPERATION
5A/DIV
VOUT3
2V/DIV
PULSESKIPPING
MODE
GND
2µs/DIV
VIN = 7V
VOUT = 10V
ILOAD = 1mA
FIGURE 12 CIRCUIT
3899 G16
2ms/DIV
FIGURE 12 CIRCUIT
3899 G17
REGULATED FEEDBACK VOLTAGE (V)
1.212
1.209
1.206
1.203
1.2
1.197
1.194
1.191
1.188
-75 -50 -25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3899 G18
8
3899fa
For more information www.linear.com/LTC3899
LTC3899
TYPICAL PERFORMANCE CHARACTERISTICS
9
8
7
5
EXTVCC = 0V
5.8
5.6
EXTVCC = 8.5V
5
4.8
4.6
4.4
4.2
4
0 5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V)
25
50
75
100
LOAD CURRENT (mA)
400
300
SENSE3 PINS (BOOST)
200
300
0
-75 -50 -25
BOOST
70
BUCK
60
50
40
30
20
10
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3899 G25
VIN = 12V
SENSE3+ PIN
140
120
100
80
60
20
VOUT < INTVCC – 0.5V
0
-75 -50 -25
0 25 50 75 100 125 150
TEMPERATURE (°C)
SENSE3– PIN
0 25 50 75 100 125 150
TEMPERATURE (°C)
3899 G23
MAXIMUM CURRENT SENSE VOLTAGE (mV)
80
EXTVCC RISING
40
100
90
DRVSET = GND
160
400
Maximum Current Sense
Threshold vs Duty Cycle
MAXIMUM CURRENT SENSE VOLTAGE (µA)
180
500
0 5 10 15 20 25 30 35 40 45 50 55 60 65
VSENSE COMMON MODE VOLTAGE (V)
DRVCC
6
Boost SENSE Pin Total Input
Current vs Temperature
200
100
EXTVCC FALLING
3899 G21
VOUT > INTVCC + 0.5V
3899 G22
0
3899 G20
600
100
0
7
EXTVCC FALLING
4
-75 -50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
150
SENSE CURRENT (µA)
500
DRVSET = INTVCC
EXTVCC RISING
200
700
SENSE CURRENT (µA)
SENSE CURRENT (µA)
SENSE1, 2 PINS (BUCK)
600
125
900
800
DRVCC
8
Buck SENSE– Pin Input Bias
Current vs Temperature
SENSE Pins Total Input Current
vs VSENSE Voltage
700
9
5
VBIAS = 12V
DRVSET = GND
0
EXTVCC Switchover and DRVCC
Voltages vs Temperature
10
EXTVCC = 5V
3899 G19
800
11
5.4
5.2
DRVSET = GND
6
6.2
6
DRVCC VOLTAGE (V)
DRVCC VOLTAGE (V)
10
DRVCC VOLTAGE (V)
6.4
DRVSET = INTVCC
DRVCC and EXTVCC
vs Load Current
100
3899 G24
Maximum Current Sense
Threshold vs ITH Voltage
TRACK/SS Pull-Up Current
vs Temperature
12
5% DUTY CYCLE
11.5
80
PULSE-SKIPPING
60
TRACK/SS CURRENT (µA)
11
DRVCC Line Regulation
Burst Mode
OPERATION
40
20
0
FORCED CONTINUOUS MODE
–20
–40
0
0.2
0.4
0.6 0.8
VITH (V)
1
1.2
11
10.5
10
9.5
9
8.5
1.4
3899 G26
8
-75 -50 -25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3899 G27
3899fa
For more information www.linear.com/LTC3899
9
LTC3899
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Current vs
Input Voltage
Shutdown Current vs Temperature
8
VBIAS = 12V
70
6
5
4
3
2
QUIESCENT CURRENT (µA)
12
SHUTDOWN CURRENT (µA)
10
8
6
4
2
1
0
-75 -50 -25
0
0 25 50 75 100 125 150
TEMPERATURE (°C)
30
20
7.5
500
450
400
FREQ = GND
350
6.5
100 200 300 400 500 600 700 800
FEEDBACK VOLTAGE (mV)
5
4.5
10
5
4
150°C
25°C
–55°C
FREQ = 350kHz
10MΩ LOAD BETWEEN BOOST3 AND SW3
3
2
1
5 10 15 20 25 30 35 40 45 50 55 60 65
SW3 VOLTAGE (V)
3899 G34
10
CHARGE PUMP CHARGING CURRENT (µA)
6
0 25 50 75 100 125 150
TEMPERATURE (°C)
BOOST3 Charge Pump Charging
Current vs Switch Voltage
120
100
7
FALLING
3899 G33
BOOST3 Charge Pump Charging
Current vs Frequency
8
DRVSET = GND
3899 G32
BOOST3 Charge Pump Output
Voltage vs SW3 Voltage
9
RISING
3
-75 -50 -25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3899 G31
FALLING
5.5
3.5
0
DRVSET = INTVCC
6
4
10
300
-75 -50 -25
RISING
7
DRVCC VOLTAGE (V)
30
0 25 50 75 100 125 150
TEMPERATURE (°C)
Undervoltage Lockout Threshold
vs Temperature
FREQ = INTVCC
550
80
40
DRVSET = GND
20
8
90
50
DRVSET = INTV CC
3899 G30
600
FREQUENCY (kHz)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
100
0
40
Oscillator Frequency vs
Temperature
60
DRVSET = 70kΩ
50
3899 G29
Buck Foldback Current
0
60
0
–75 –50 –25
0 5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V)
3899 G28
70
VBIAS = 12V
ONE CHANNEL ON
Burst Mode OPERATION
10
90
80
–55°C
70
25°C
60
50
40
150°C
30
20
10
VBOOST3 = 16.5V
VSW3 = 12V
0
100
200 300 400 500 600 700
OPERATING FREQUENCY (kHz)
800
3899 G35
CHARGE PUMP CHARGING CURRENT (µA)
SHUTDOWN CURRENT (µA)
7
BOOST3 – SW3 VOLTAGE (V)
Quiescent Current vs Temperature
80
14
110
– 55°C
100
90
80
VBOOST3 – VSW3 = 4.5V
70
25°C
150°C
60
50
40
30
20
10
0
VBOOST3 – VSW3 = 7.0V
–55°C
25°C
150°C
FREQ = 350kHz
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SW3 VOLTAGE (V)
3899 G36
3899fa
For more information www.linear.com/LTC3899
LTC3899
PIN FUNCTIONS
(QFN/TSSOP)
FREQ (Pin 1/ Pin 5): The frequency control pin for the
internal VCO. Connecting this pin to GND forces the VCO
to a fixed low frequency of 350kHz. Connecting this pin
to INTVCC forces the VCO to a fixed high frequency of
535kHz. Other frequencies between 50kHz and 900kHz can
be programmed using a resistor between FREQ and GND.
The resistor and an internal 20µA source current create a
voltage used by the internal oscillator to set the frequency.
PLLIN/MODE (Pin 2/Pin 6): External Synchronization
Input to Phase Detector and Forced Continuous Mode
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG1 signal to be
synchronized with the rising edge of the external clock,
and the regulators will operate in forced continuous mode.
When not synchronizing to an external clock, this input,
which acts on all three controllers, determines how the
LTC3899 operates at light loads. Pulling this pin to ground
selects Burst Mode operation. An internal 100k resistor to
ground also invokes Burst Mode operation when the pin is
floated. Tying this pin to INTVCC forces continuous inductor
current operation. Tying this pin to a voltage greater than
1.1V and less than INTVCC – 1.3V selects pulse-skipping
operation. This can be done by connecting a 100k resistor
from this pin to INTVCC.
INTVCC (Pin 8/Pin 12): Output of the Internal 5V Low
Dropout Regulator. The low voltage analog and digital
circuits are powered from this voltage source. A low ESR
0.1µF ceramic bypass capacitor should be connected
between INTVCC and GND, as close as possible to the IC.
INTVCC should not be used to power or bias any external
circuitry other than to configure FREQ, PLLIN/MODE,
DRVSET AND VPRG3 pins.
RUN1, RUN2, RUN3 (Pins 9, 10, 11/ Pins 13, 14, 15):
Run Control Inputs for Each Controller. Forcing any of these
pins below 1.2V shuts down that controller. Forcing all of
these pins below 0.7V shuts down the entire LTC3899,
reducing quiescent current to approximately 3.6µA.
DRVSET (Pin 16/Pin 20): Sets the regulated output voltage of the DRVCC LDO regulator. Connecting this pin to
GND sets DRVCC to 6V whereas connecting it to INTVCC
sets DRVCC to 10V. Voltages between 5V and 10V can be
programmed by placing a resistor (50k to 100k) between
the DRVSET pin and GND. The DRVSET pin also determines
the higher or lower DRVCC UVLO and EXTVCC switchover
thresholds, as listed on the Electrical Characteristics table.
Connecting DRVSET to GND or programming DRVSET with
a resistor chooses the lower thresholds whereas tying
DRVSET to INTVCC chooses the higher thresholds. When
programming DRVSET with a resistor, do not choose a
resistor value less than 50k (unless shorting DRVSET to
GND) or higher than 100k.
DRVCC (Pin 22/Pin 26): Output of the Internal or External
Low Dropout (LDO) Regulator. The gate drivers are powered from this voltage source. The DRVCC voltage is set
by the DRVSET pin. Must be decoupled to ground with a
minimum of 4.7µF ceramic or other low ESR capacitor.
Do not use the DRVCC pin for any other purpose.
EXTVCC (Pin 23/Pin 27): External Power Input to an Internal LDO Connected to DRVCC. This LDO supplies DRVCC
power, bypassing the internal LDO powered from VBIAS
whenever EXTVCC is higher than its switchover threshold
(4.7V or 7.7V depending on the DRVSET pin). See EXTVCC
Connection in the Applications Information section. Do not
float or exceed 14V on this pin. Do not connect EXTVCC to
a voltage greater than VBIAS. Connect to GND if not used.
VBIAS (Pin 24/Pin 28): Main Supply Pin. A bypass capacitor
should be tied between this pin and the GND pin.
BG1, BG2, BG3 (Pins 29, 21, 25/Pins 33, 25, 29): High
Current Gate Drives for Bottom N-Channel MOSFETs.
Voltage swing at these pins is from ground to DRVCC.
BOOST1, BOOST2, BOOST3 (Pins 30, 20, 26/Pins 34,
24, 30): Bootstrapped Supplies to the Topside Floating
Drivers. Capacitors are connected between the BOOST and
SW pins. Voltage swing at BOOST1 and BOOST2 pins is
from approximately DRVCC to (VIN1,2 + DRVCC). Voltage
swing at BOOST3 is from DRVCC to (VOUT3 + DRVCC).
SW1, SW2, SW3 (Pins 31, 19, 28/Pins 35, 23, 32):
Switch Node Connections to Inductors.
TG1, TG2, TG3 (Pins 32, 18, 27/Pins 36, 22, 31): High
Current Gate Drives for Top N-Channel MOSFETs. These are
the outputs of floating drivers with a voltage swing equal
to DRVCC superimposed on the switch node voltage SW.
3899fa
For more information www.linear.com/LTC3899
11
LTC3899
PIN FUNCTIONS
(QFN/TSSOP)
TRACK/SS1, TRACK/SS2, SS3 (Pins 33, 17, 3/Pins 37,
21, 7): External Tracking and Soft-Start Input. For the buck
channels, the LTC3899 regulates the VFB1,2 voltage to the
smaller of 0.8V, or the voltage on the TRACK/SS1,2 pin.
For the boost channel, the LTC3899 regulates the VFB3
voltage to the smaller of 1.2V, or the voltage on the SS3
pin. An internal 10µA pull-up current source is connected
to this pin. A capacitor to ground at this pin sets the ramp
time to final regulated output voltage. Alternatively, a resistor divider on another voltage supply connected to the
TRACK/SS pins of the buck channels allow the LTC3899
buck outputs to track the other supply during start-up.
VPRG3 (Pin 34/Pin 38): Channel 3 Output Control Pin.
This pin sets the boost channel to adjustable output mode
using external feedback resistors or fixed 10V/12V output
mode. Floating this pin allows the output to be programmed
through the VFB3 pin using external resistors, regulating
VFB3 to the 1.2V reference. Connecting this pin to GND or
INTVCC programs the output to 10V or 12V (respectively),
and VFB3 is used to sense the output voltage.
ITH1, ITH2, ITH3 (Pins 35, 15, 7/Pins 1, 19, 11): Error
Amplifier Outputs and Switching Regulator Compensation
Points. Each associated channel’s current comparator trip
point increases with this control voltage.
12
VFB1, VFB2 (Pins 36, 14/Pins 2, 18): These pins receive the
remotely sensed feedback voltage for each buck controller
from an external resistive divider across the output.
VFB3 (Pins 6/Pins 10): If VPRG3 is floating, this pin receives
the remotely sensed feedback voltage for the boost controller from an external resistive divider across the output.
If VPRG3 is tied to GND or INTVCC, this pin receives the
remotely sensed output voltage of the boost controller.
SENSE1+, SENSE2+, SENSE3+ (Pins 37, 13, 4/Pins 3,
17, 8): The (+) Input to the Differential Current Comparators. The ITH pin voltage and controlled offsets between
the SENSE– and SENSE+ pins in conjunction with RSENSE
set the current trip threshold. For the boost channel, the
SENSE3+ pin supplies current to the current comparator.
SENSE1–, SENSE2–, SENSE3– (Pins 38, 12, 5/Pins 4,
16, 9): The (–) Input to the Differential Current Comparators. When SENSE1,2– for the buck channels is greater
than INTVCC, then SENSE1,2– pin supplies current to the
current comparator.
GND (Exposed Pad Pin 39/Exposed Pad Pin 39): Ground.
The exposed pad must be soldered to the PCB for rated
electrical and thermal performance.
3899fa
For more information www.linear.com/LTC3899
LTC3899
FUNCTIONAL DIAGRAMS
BUCK CHANNELS 1 AND 2
FREQ
DRVCC
VIN1,2
20µA
BOOST1,2
CLK2
VCO CLK1
DROPOUT
DET
PFD
S
Q
R
Q
TOP
TG1,2
BOT
CB
CIN
SW1,2
TOP ON
DRVCC
SWITCHING
LOGIC
SHDN
COUT
BG1,2
BOT
VOUT1,2
GND
L
SYNC
DET
PLLIN/MODE
+
–
0.425V
100k
+
–
ICMP
–+
RSENSE
SLEEP
+
+– –
IR
SENSE1,2+
3mV
2.8V
0.65V
SENSE1,2–
–
EA +
+
SLOPE COMP
OV
3.5V
150nA
SHDN
RST
2(VFB)
FOLDBACK
+
–
RB
VFB1,2
0.80V
TRACK/SS
0.88V
RA
CC
ITH1,2
CC2
10µA
RC
TRACK/SS1,2
CSS
SHDN
RUN1,2
3899 FD
20µA
DRVSET
2.00V
1.20V
EXTVCC
DRVCC LDO/
UVLO CONTROL
VBIAS
R
4R
+
–
DRVCC
EN
+
–
EN
4.7V/
7.7V
–
+
INTVCC
LDO
INTVCC
3899fa
For more information www.linear.com/LTC3899
13
LTC3899
FUNCTIONAL DIAGRAMS
BOOST CHANNEL 3
DRVCC
CHARGE
PUMP
BOOST3
CLK1
S
Q
R
Q
BOTTOM
TOP
VOUT3
CB
TG3
COUT
SW3
SHDN
SWITCHING
LOGIC
DRVCC
BOT
CIN
BG3
VIN3
GND
PLLIN/MODE
+
–
0.425V
+
–
ICMP
SLEEP
+
+– –
–+
L
RSENSE
IR
SENSE3–
3mV
2.8V
0.7V
SENSE3+
SLOPE COMP
+
–
SNSLO
2V
VPRG3
EA
OV
3.5V
RB
VFB3
–
+
+
1.2V
SS3
+
–
1.32V
CC
ITH3
150nA
CC2
10µA
SHDN
VOUT3
RA
RC
SS3
CSS
SNSLO
RUN3
3899 FD02
OPERATION
(Refer to the Functional Diagrams)
Main Control Loop
The LTC3899 uses a constant frequency, current mode
step-down architecture. The two buck controllers, channels
1 and 2, operate 180° out of phase with each other. The
boost controller, channel 3, operates in phase with channel 1. During normal operation, the external top MOSFET
for the buck channels (the external bottom MOSFET for
the boost controller) is turned on when the clock for that
channel sets the RS latch, and is turned off when the
main current comparator, ICMP, resets the RS latch. The
14
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier, EA. The error amplifier
compares the output voltage feedback signal at the VFB
pin (which is generated with an external resistor divider
connected across the output voltage, VOUT, to ground)
to the internal 0.800V reference voltage (1.2V reference
voltage for the boost). When the load current increases,
it causes a slight decrease in VFB relative to the reference,
which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
3899fa
For more information www.linear.com/LTC3899
LTC3899
OPERATION
(Refer to the Functional Diagrams)
After the top MOSFET for the bucks (the bottom MOSFET
for the boost) is turned off each cycle, the bottom MOSFET
is turned on (the top MOSFET for the boost) until either the
inductor current starts to reverse, as indicated by the current
comparator IR, or the beginning of the next clock cycle.
DRVCC/EXTVCC/INTVCC Power
Power for the top and bottom MOSFET drivers is derived
from the DRVCC pin. The DRVCC supply voltage can be
programmed from 5V to 10V through control of the
DRVSET pin. When the EXTVCC pin is tied to a voltage
below its switchover voltage (4.7V or 7.7V depending
on the DRVSET voltage), the VBIAS LDO (low dropout
linear regulator) supplies power from VBIAS to DRVCC. If
EXTVCC is taken above its switchover voltage, the VBIAS
LDO is turned off and an EXTVCC LDO is turned on. Once
enabled, the EXTVCC LDO supplies power from EXTVCC
to DRVCC. Using the EXTVCC pin allows the DRVCC power
to be derived from a high efficiency external source such
as one of the LTC3899 buck regulator outputs.
Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each
cycle through an internal switch whenever SW goes low.
For buck channels 1 and 2, if the input voltage decreases
to a voltage close to its output, the loop may enter dropout
and attempt to turn on the top MOSFET continuously. The
dropout detector detects this and forces the top MOSFET off
for about one-twelfth of the clock period every tenth cycle
to allow CB to recharge, resulting in about 99% duty cycle.
The INTVCC supply powers most of the other internal circuits
in the LTC3899. The INTVCC LDO regulates to a fixed value
of 5V and its power is derived from the DRVCC supply.
Shutdown and Start-Up (RUN, TRACK/SS Pins)
The three channels of the LTC3899 can be independently
shut down using the RUN1, RUN2 and RUN3 pins. Pulling a RUN pin below 1.20V shuts down the main control
loop for that channel. Pulling all three pins below 0.7V
disables all controllers and most internal circuits, including
the DRVCC and INTVCC LDOs. In this state, the LTC3899
draws only 3.6μA of quiescent current.
Releasing a RUN pin allows a small 150nA internal current
to pull up the pin to enable that controller. Each RUN pin
may be externally pulled up or driven directly by logic. Each
RUN pin can tolerate up to 65V (absolute maximum), so it
can be conveniently tied to VBIAS in always-on applications
where one or more controllers are enabled continuously
and never shut down.
The start-up of each controller’s output voltage VOUT
is controlled by the voltage on the TRACK/SS pin
(TRACK/SS1 for channel 1, TRACK/SS2 for channel 2,
SS3 for channel 3). When the voltage on the TRACK/SS
pin is less than the 0.8V internal reference for the bucks
and the 1.2V internal reference for the boost, the LTC3899
regulates the VFB voltage to the TRACK/SS pin voltage
instead of the corresponding reference voltage. This allows the TRACK/SS pin to be used to program a soft-start
by connecting an external capacitor from the TRACK/SS
pin to GND. An internal 10μA pull-up current charges this
capacitor creating a voltage ramp on the TRACK/SS pin. As
the TRACK/SS voltage rises linearly from 0V to 0.8V/1.2V
(and beyond up to about 4V), the output voltage VOUT rises
smoothly from zero (VIN for the boost) to its final value.
Alternatively the TRACK/SS pins for buck channels 1 and 2
can be used to cause the start-up of VOUT to track that of
another supply. Typically, this requires connecting to the
TRACK/SS pin an external resistor divider from the other
supply to ground (see Applications Information section).
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode)
(PLLIN/MODE Pin)
The LTC3899 can be enabled to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode,
or forced continuous conduction mode at low load currents.
To select Burst Mode operation, tie the PLLIN/MODE pin to
GND. To select forced continuous operation, tie the PLLIN/
MODE pin to INTVCC. To select pulse-skipping mode, tie
the PLLIN/MODE pin to a DC voltage greater than 1.1V and
less than INTVCC – 1.3V. This can be done by connecting
a 100kΩ resistor between PLLIN/MODE and INTVCC.
When a controller is enabled for Burst Mode operation,
the minimum peak current in the inductor is set to approximately 25% of the maximum sense voltage (30%
3899fa
For more information www.linear.com/LTC3899
15
LTC3899
OPERATION
(Refer to the Functional Diagrams)
for the boost) even though the voltage on the ITH pin
indicates a lower value. If the average inductor current is
higher than the load current, the error amplifier, EA, will
decrease the voltage on the ITH pin. When the ITH voltage drops below 0.425V, the internal sleep signal goes
high (enabling sleep mode) and both external MOSFETs
are turned off. The ITH pin is then disconnected from the
output of the EA and parked at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3899 draws.
If one channel is in sleep mode and the other two are
shut down, the LTC3899 draws only 29μA of quiescent
current (with DRVSET = 0V). If two channels are in sleep
mode and the other shut down, it draws only 34μA of
quiescent current. If all three controllers are enabled in
sleep mode, the LTC3899 draws only 39μA of quiescent
current. In sleep mode, the load current is supplied by
the output capacitor. As the output voltage decreases,
the EA’s output begins to rise. When the output voltage
drops enough, the ITH pin is reconnected to the output
of the EA, the sleep signal goes low, and the controller
resumes normal operation by turning on the top external
MOSFET (the bottom external MOSFET for the boost) on
the next cycle of the internal oscillator.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET (the top external MOSFET for the boost) just
before the inductor current reaches zero, preventing it
from reversing and going negative. Thus, the controller
operates discontinuously.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than in
Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and
less interference to audio circuitry. In forced continuous
mode, the output ripple is independent of load current.
Clocking the LTC3899 from an external source enables
forced continuous mode (see the Frequency Selection
and Phase-Locked Loop section).
16
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3899 operates in PWM pulse-skipping mode
at light loads. In this mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator, ICMP, may remain tripped for several cycles
and force the external top MOSFET (bottom for the boost)
to stay off for the same number of cycles (i.e., skipping
pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous
operation, exhibits low output ripple as well as low audio
noise and reduced RF interference as compared to Burst
Mode operation. It provides higher low current efficiency
than forced continuous mode, but not nearly as high as
Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3899’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to GND, tied to
INTVCC or programmed through an external resistor. Tying
FREQ to GND selects 350kHz while tying FREQ to INTVCC
selects 535kHz. Placing a resistor between FREQ and GND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 10.
A phase-locked loop (PLL) is available on the LTC3899
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3899’s phase detector adjusts the voltage (through an
internal lowpass filter) of the VCO input to align the turnon of controller 1’s external top MOSFET (and controller
3’s external bottom MOSFET) to the rising edge of the
synchronizing signal. Thus, the turn-on of controller 2’s
external top MOSFET is 180° out of phase to the rising
edge of the external clock source.
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LTC3899
OPERATION
(Refer to the Functional Diagrams)
The VCO input voltage is prebiased to the operating frequency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3899’s phase-locked
loop is from approximately 55kHz to 1MHz, with a guarantee to be between 75kHz and 850kHz. In other words, the
LTC3899’s PLL is guaranteed to lock to an external clock
source whose frequency is between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.1V (falling). It is recommended
that the external clock source swings from ground (0V)
to at least 2.5V.
Boost Controller Operation When VIN > VOUT
When the input voltage to the boost channel rises above
its regulated VOUT voltage, the controller can behave differently depending on the mode, inductor current and
VIN voltage. In forced continuous mode, the loop works
to keep the top MOSFET on continuously once VIN rises
above VOUT. An internal charge pump delivers current to
the boost capacitor from the BOOST3 pin to maintain a
sufficiently high TG voltage. Because the LTC3899 uses
internal switches and does not require external bootstrap
diodes, the charge pump only has to overcome small
leakage currents (board leakage, etc.).
In pulse-skipping mode, if VIN is between 0% and 10%
above the regulated VOUT voltage, TG3 turns on if the
inductor current rises above approximately 3% of the
programmed ILIM current. If the part is programmed in
Burst Mode operation under this same VIN window, then
TG3 turns on at the same threshold current as long as
the chip is awake (one of the buck channels is awake and
switching). If both buck channels are asleep or shut down
in this VIN window, then TG3 will remain off regardless of
the inductor current.
inductor current. In Burst Mode operation, however, the
internal charge pump turns off if the entire chip is asleep
(if the two buck channels are also asleep or shut down).
With the charge pump off, there would be nothing to prevent the boost capacitor from discharging, resulting in an
insufficient TG voltage needed to keep the top MOSFET
completely on. The charge pump turns back on when the
chip wakes up, and it remains on as long as one of the
buck channels is actively switching.
Boost Controller at Low SENSE Pin Common Voltage
The current comparator of the boost controller is powered
directly from the SENSE3+ pin and can operate to voltages
as low as 2.2V. Since this is lower than the VBIAS UVLO of
the chip, VBIAS can be connected to the output of the boost
controller, as illustrated in the typical application circuit in
Figure 12. This allows the boost controller to handle input
voltage transients down to 2.2V while maintaining output
voltage regulation. If SENSE3+ falls below 2.0V, then
switching stops and SS3 is pulled low. If SENSE3+ rises
back above 2.2V, the SS3 pin will be released, initiating a
new soft-start sequence.
Buck Controller Output Overvoltage Protection
The two buck channels have an overvoltage comparator
that guards against transient overshoots as well as other
more serious conditions that may overvoltage the output.
When the VFB1,2 pin rises by more than 10% above its
regulation point of 0.800V, the top MOSFET is turned off
and the bottom MOSFET is turned on until the overvoltage
condition is cleared.
Buck Foldback Current
When the buck output voltage falls to less than 70% of
its nominal level, foldback current limiting is activated,
progressively lowering the peak current limit in proportion
to the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the VFB1,2 voltage is keeping up with
the TRACK/SS1,2 voltage). There is no foldback current
limiting for the boost channel.
If VIN rises more than 10% above the regulated VOUT voltage
in any mode, the controller turns on TG3 regardless of the
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17
LTC3899
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic LTC3899
application circuit. LTC3899 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs and Schottky diodes are selected. Finally,
input and output capacitors are selected.
the SENSE3– pin allows the current comparator to be used
in inductor DCR sensing.
Filter components mutual to the sense lines should be
placed close to the LTC3899, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing is
used (Figure 2b), R1 should be placed close to the switching node, to prevent noise from coupling into sensitive
small-signal nodes.
TO SENSE FILTER
NEXT TO THE CONTROLLER
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the current comparators.
CURRENT FLOW
Buck Controllers (SENSE1+/SENSE1–, SENSE2+/SENSE2–):
The common mode voltage range on these pins is 0V to
65V (absolute maximum), enabling the LTC3899 to regulate buck output voltages up to a nominal 60V (allowing
margin for tolerances and transients). The SENSE+ pin
is high impedance over the full common mode range,
drawing at most ±1μA. This high impedance allows the
current comparators to be used in inductor DCR sensing.
The impedance of the SENSE– pin changes depending on
the common mode voltage. When SENSE– is less than
INTVCC – 0.5V, a small current of less than 1μA flows out
of the pin. When SENSE– is above INTVCC + 0.5V, a higher
current (≈700μA) flows into the pin. Between INTVCC –
0.5V and INTVCC + 0.5V, the current transitions from the
smaller current to the higher current.
Boost Controller (SENSE3+/SENSE3–): The common
mode input range for these pins is 2.2V to 60V, allowing
the boost converter to operate from inputs over this full
range. The SENSE3+ pin also provides power to the current comparator and draws about 170μA during normal
operation (when not shut down or asleep in Burst Mode
operation). There is a small bias current of less than 1μA
that flows into the SENSE3– pin. This high impedance on
18
INDUCTOR OR RSENSE
3899 F03
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
The current comparators have a maximum threshold
VSENSE(MAX) of 75mV. The current comparator threshold
voltage sets the peak of the inductor current, yielding
a maximum average output current, IMAX, equal to the
peak value less half the peak-to-peak ripple current, ∆IL.
To calculate the sense resistor value, use the equation:
RSENSE =
VSENSE(MAX)
∆I
IMAX + L
2
When using the buck controllers in very low dropout conditions, the maximum output current level will be reduced
due to the internal compensation required to meet stability
criteria for buck regulators operating at greater than 50%
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LTC3899
APPLICATIONS INFORMATION
VIN1,2
(VOUT3)
BOOST
TG
LTC3899
RSENSE
SW
VOUT1,2
(VIN3)
BG
SENSE1,2+
(SENSE3–)
CAP
PLACED NEAR SENSE PINS
SENSE1,2–
(SENSE3+)
GND
3899 F04a
(2a) Using a Resistor to Sense Current
VIN1,2
(VOUT3)
BOOST
INDUCTOR
TG
LTC3899
L
SW
DCR
VOUT1,2
(VIN3)
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such
an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
DCR sensing.
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
BG
SENSE1,2+
(SENSE3–)
SENSE1,2–
(SENSE3+)
RSENSE(EQUIV) =
R1
C1*
R2
GND
*PLACE C1 NEAR SENSE PINS
(R1||R2) • C1 = L/DCR
RSENSE(EQ) = DCR(R2/(R1+R2))
3899 F04b
(2b) Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
duty factor. A curve is provided in the Typical Performance
Characteristics section to estimate this reduction in peak
inductor current depending upon the operating duty factor.
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3899 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
VSENSE(MAX)
∆I
IMAX + L
2
To ensure that the application will deliver full load current over the full operating temperature range, determine
RSENSE(EQUIV), keeping in mind that the minimum value
for the maximum current sense threshold (VSENSE(MAX))
for the LTC3899 is 65mV.
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value (RD), use the divider ratio:
RD =
RSENSE(EQUIV)
DCRMAX at TL(MAX)
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19
LTC3899
APPLICATIONS INFORMATION
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1|| R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ±1μA current.
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
The equivalent resistance R1||R2 is scaled to the temperature inductance and maximum DCR:
The inductor value has a direct effect on ripple current.
The inductor ripple current, ∆IL, decreases with higher
inductance or higher frequency. For the buck controllers,
∆IL increases with higher VIN:
L
R1R2 =
(DCR at 20°C)•C1

The sense resistor values are:
R1R2
R1•RD
R1=
; R2 =
RD
1−RD

( VIN(MAX) − VOUT ) • VOUT
R1
For the boost controller, the maximum power loss in R1
will occur in continuous mode at VIN = 1/2 • VOUT:
PLOSS R1=
( VOUT(MAX) − VIN ) • VIN
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduces
conduction losses and provides higher efficiency at heavy
loads. Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
20
 V 
1
VOUT  1− OUT 
VIN 
( f ) (L )

For the boost controller, ∆IL increases with higher VOUT:
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS R1=
∆IL =
∆IL =

1
V 
VIN  1− IN 
( f ) (L )  VOUT 
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3(IMAX). The maximum
∆IL occurs at the maximum input voltage for the bucks
and VIN = 1/2 • VOUT for the boost.
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit (30% for the boost) determined
by RSENSE. Lower inductor values (higher ∆IL) will cause
this to occur at lower load currents, which can cause a dip
in efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
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LTC3899
APPLICATIONS INFORMATION
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Power MOSFET and Schottky Diode
(Optional) Selection
Two external power MOSFETs must be selected for each
controller in the LTC3899: one N-channel MOSFET for the
top switch (main switch for the bucks, synchronous for the
boost), and one N-channel MOSFET for the bottom switch
(main switch for the boost, synchronous for the bucks).
VOUT
VIN
Buck Sync Switch Duty Cycle =
VIN − VOUT
VIN
Boost Main Switch Duty Cycle =
VOUT − VIN
VOUT
Boost Sync Switch Duty Cycle =
VIN
VOUT
The MOSFET power dissipations at maximum output
current are given by:
2
V
PMAIN_BUCK = OUT IOUT(MAX) (1+δ ) RDS(ON) +
VIN
 IOUT(MAX) 
 (R )(C
(VIN )2 
 DR MILLER )•
2



1
1 

+

 (f)
 VDRVCC − VTHMIN VTHMIN 
2
V −V
PSYNC _BUCK = IN OUT IOUT(MAX) (1+δ ) RDS(ON)
VIN
(
The peak-to-peak drive levels are set by the DRVCC voltage. This voltage can range from 5V to 10V depending on
configuration of the DRVSET pin. Therefore, both logic-level
and standard-level threshold MOSFETs can be used in
most applications depending on the programmed DRVCC
voltage. Pay close attention to the BVDSS specification for
the MOSFETs as well.
)
(
The LTC3899’s unique ability to adjust the gate drive level
between 5V to 10V (OPTI-DRIVE) allows an application
circuit to be precisely optimized for efficiency. When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and
the input current decreases, then the efficiency has improved. If there is no change in input current, then there
is no change in efficiency.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
Buck Main Switch Duty Cycle =
PMAIN_BOOST =
)
( VOUT − VIN ) VOUT
(IOUT(MAX) )
2
•
VIN2

 V 3  I
(1+δ )RDS(ON) +  OUT   OUT(MAX)  •
2
 VIN  


1
1 
+
(RDR ) (CMILLER ) • 
 (f)
 VDRVCC − VTHMIN VTHMIN 
2
V
PSYNC _BOOST = IN IOUT(MAX) (1+δ ) RDS(ON)
VOUT
(
)
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
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21
LTC3899
APPLICATIONS INFORMATION
Both MOSFETs have I2R losses while the main N-channel
equations for the buck and boost controllers include an
additional term for transition losses, which are highest at
high input voltages for the bucks and low input voltages
for the boost. For VIN < 20V (higher VIN for the boost)
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V (lower VIN for the boost)
the transition losses rapidly increase to the point that the
use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET
losses for the buck controllers are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Optional Schottky diodes placed across the synchronous
MOSFET conduct during the dead-time between the conduction of the two power MOSFETs. This prevents the
body diode of the synchronous MOSFET from turning
on, storing charge during the dead-time and requiring a
reverse recovery period that could cost as much as 3%
in efficiency at high VIN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
Boost CIN, COUT Selection
The input ripple current in a boost converter is relatively
low (compared with the output ripple current), because
this current is continuous. The boost input capacitor CIN
voltage rating should comfortably exceed the maximum
input voltage. Although ceramic capacitors can be relatively
tolerant of overvoltage conditions, aluminum electrolytic
capacitors are not. Be sure to characterize the input voltage
for any possible overvoltage transients that could apply
excess stress to the input capacitors.
22
The value of CIN is a function of the source impedance, and
in general, the higher the source impedance, the higher the
required input capacitance. The required amount of input
capacitance is also greatly affected by the duty cycle. High
output current applications that also experience high duty
cycles can place great demands on the input supply, both
in terms of DC current and ripple current.
In a boost converter, the output has a discontinuous current,
so COUT must be capable of reducing the output voltage
ripple. The effects of ESR (equivalent series resistance)
and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage.
The steady ripple due to charging and discharging the
bulk capacitance is given by:
Ripple =
(
IOUT(MAX) • VOUT − VIN(MIN)
COUT • VOUT • f
)V
where COUT is the output filter capacitor.
The steady ripple due to the voltage drop across the ESR
is given by:
∆VESR = IL(MAX) • ESR
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings such as OS-CON and POSCAP.
Buck CIN, COUT Selection
The selection of CIN for the two buck controllers is simplified
by the 2-phase architecture and its impact on the worstcase RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case
capacitor RMS current occurs when only one controller
is operating. The controller with the highest (VOUT)(IOUT)
product needs to be used in the formula shown in Equa-
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LTC3899
APPLICATIONS INFORMATION
tion 1 to determine the maximum RMS capacitor current
requirement. Increasing the output current drawn from
the other controller will actually decrease the input RMS
ripple current from its maximum value. The opt-of-phase
technique typically reduces the input capacitor’s RMS
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
1/2
I
CIN Required IRMS ≈ MAX  ( VOUT ) ( VIN − VOUT )
(1)
VIN
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3899, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The benefit of the LTC3899 2-phase operation can be calculated by using Equation 1 for the higher power controller
and then calculating the loss that would have resulted if
both controller channels switched on at the same time.
The total RMS power lost is lower when both controllers
are operating due to the reduced overlap of current pulses
required through the input capacitor’s ESR. This is why
the input capacitor’s requirement calculated above for the
worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefit of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The drains of the top MOSFETs should be placed within
1cm of each other and share a common CIN(s). Separating
the drains and CIN may produce undesirable voltage and
current resonances at VIN.
A small (0.1μF to 1μF) bypass capacitor between the chip
VBIAS pin and ground, placed close to the LTC3899, is also
suggested. A 10Ω resistor placed between CIN (C1) and
the VBIAS pin provides further isolation.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:


1

∆VOUT ≈ ∆IL  ESR +


8 • f •COUT 

where f is the operating frequency, COUT is the output
capacitance and ∆IL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ∆IL increases with input voltage.
Setting Buck Output Voltage
The LTC3899 output voltages for the buck controllers are
set by an external feedback resistor divider carefully placed
across the output, as shown in Figure 3. The regulated
output voltage is determined by:

R 
VOUT = 0.8V  1+ B 
 RA 
To improve the frequency response, a feedforward capacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
VOUT
LTC3899
RB
CFF
VFB
RA
3899 F05
Figure 3. Setting Buck Output Voltage
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LTC3899
APPLICATIONS INFORMATION
Setting Boost Output Voltage (VPRG3 Pin)
Through control of the VPRG3 pin the boost controller
output voltage can be set by an external feedback resistor divider or programmed to a fixed 10V or 12V output.
Floating VPRG3 allows the boost output voltage to be set
by an external feedback resistor divider placed across
the output, as shown in Figure 4a. The regulated output
voltage is determined by:

R 
VOUT(BOOST) = 1.2V  1+ B 
 RA 
Tying the VPRG3 to INTVCC or GND configures the boost
controller in fixed output voltage mode. Figure 4b shows
how the VFB3 pin is used to sense the output voltage in
this mode. Tying VPRG3 to INTVCC programs the boost
output to 12V, whereas tying VPRG3 to GND programs
the output to 10V.
LDOs. In this state, the LTC3899 draws only 3.6µA of
quiescent current.
Releasing a RUN pin allows a small 150nA internal current
to pull up the pin to enable that controller. Because of
condensation or other small board leakage pulling the pin
down, it is recommended the RUN pins be externally pulled
up or driven directly by logic. Each RUN pin can tolerate
up to 65V (absolute maximum), so it can be conveniently
tied to VBIAS in always-on applications where one or more
controllers are enabled continuously and never shut down.
The RUN pins can be implemented as a UVLO by connecting them to the output of an external resistor divider
network off VBIAS, as shown in Figure 5.
VBIAS
1/3 LTC3899
RB
RUN
RA
3899 F13
VOUT3
LTC3899
(FLOAT)
Figure 5. Using the RUN Pins as a UVLO
RB
CFF
VPRG3 VFB3
The rising and falling UVLO thresholds are calculated using
the RUN pin thresholds and pull-up current:
RA
 R 
VUVLO(RISING) = 1.275V  1+ B  – 150nA •RB
 RA 
3899 F06a
(4a) Setting Boost Output Using External Resistors
LTC3899
INTVCC/GND
VPRG3 VFB3
COUT
VOUT3
12V/10V
3899 F06b
(4b) Setting Boost to Fixed 12V/10V Output
Figure 4. Setting CH3 Output Voltage
RUN Pins
The LTC3899 is enabled using the RUN1, RUN2 and RUN3
pins. The RUN pins have a rising threshold of 1.275V with
75mV of hysteresis. Pulling a RUN pin below 1.2V shuts
down the main control loop for that channel. Pulling all
three RUN pins below 0.7V disables the controllers and
most internal circuits, including the DRVCC and INTVCC
24
 R 
VUVLO(FALLING) = 1.20V  1+ B  – 150nA •RB
 RA 
Tracking and Soft-Start (TRACK/SS1, TRACK/SS2,
SS3 Pins)
The start-up of each VOUT is controlled by the voltage on the TRACK/SS pin (TRACK/SS1 for channel 1,
TRACK/SS2 for channel 2, SS3 for channel 3). When the
voltage on the TRACK/SS pin is less than the internal
0.8V reference (1.2V reference for the boost channel),
the LTC3899 regulates the VFB pin voltage to the voltage
on the TRACK/SS pin instead of the internal reference.
The TRACK/SS pin can be used to program an external
soft-start function or to allow VOUT to track another supply during start-up.
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Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 6.
An internal 10μA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
The LTC3899 will regulate its feedback voltage (and hence
VOUT) according to the voltage on the TRACK/SS pin, allowing VOUT to rise smoothly from 0V (VIN for the boost)
to its final regulated value. The total soft-start time will
be approximately:
Alternatively, the TRACK/SS1 and TRACK/SS2 pins
for the two buck controllers can be used to track two
(or more) supplies during start-up, as shown qualitatively in Figures 7a and 7b. To do this, a resistor divider
should be connected from the master supply (VX) to the
TRACK/SS pin of the slave supply (VOUT), as shown in
Figure 8. During start-up VOUT will track VX according to
the ratio set by the resistor divider:
GND
3899 F07
Figure 6. Using the TRACK/SS Pin to Program Soft-Start
VX(MASTER)
R
+R
• TRACKA TRACKB
R A +RB
VOUT(SLAVE)
TIME
3889 F08a
(7a) Coincident Tracking
VX(MASTER)
OUTPUT (VOUT)
1.2V
tSS_BOOST = CSS •
10µA
VX
RA
=
VOUT R TRACKA
CSS
OUTPUT (VOUT)
0.8V
tSS_BUCK = CSS •
10µA
LTC3899
TRACK/SS
VOUT(SLAVE)
TIME
For coincident tracking (VOUT = VX during start-up),
3899 F08b
(7b) Ratiometric Tracking
RA = RTRACKA
Figure 7. Two Different Modes of Output Voltage Tracking
RB = RTRACKB
VOUT
DRVCC and INTVCC Regulators (OPTI-DRIVE)
The LTC3899 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power
at the DRVCC pin from either the VBIAS supply pin or the
EXTVCC pin depending on the connections of the EXTVCC
and DRVSET pins. A third P-channel LDO supplies power
at the INTVCC pin from the DRVCC pin. DRVCC powers the
gate drivers whereas INTVCC powers much of the LTC3899’s
internal circuitry. The VBIAS LDO and the EXTVCC LDO
regulate DRVCC between 5V to 10V, depending on how
the DRVSET pin is set. Each of these LDOs can supply a
RB
VFB1,2
RA
VX
LTC3899
RTRACKB
TRACK/SS1,2
RTRACKA
3899 F09
Figure 8. Using the TRACK/SS Pin for Tracking
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LTC3899
APPLICATIONS INFORMATION
peak current of at least 50mA and must be bypassed to
ground with a minimum of 4.7μF ceramic capacitor. Good
bypassing is needed to supply the high transient currents
required by the MOSFET gate drivers and to prevent interaction between the channels. The INTVCC supply must
be bypassed with a 0.1μF ceramic capacitor.
The DRVSET pin programs the DRVCC supply voltage as
well as the DRVCC UVLO and EXTVCC switchover threshold
voltages. Table 1 summarizes the different DRVSET pin
configurations along with the voltage settings that go with
each configuration. Tying the DRVSET pin to INTVCC programs DRVCC to 10V and chooses the higher UVLO/EXTVCC
thresholds. Tying the DRVSET pin to GND programs DRVCC
to 6V and chooses the lower UVLO/EXTVCC thresholds.
By placing a 50k to 100k resistor between DRVSET and
GND the DRVCC voltage can be programmed between 5V
to 10V, as shown in Figure 9. With a resistor on DRVSET,
the lower UVLO/EXTVCC thresholds are chosen.
Table 1
DRVSET PIN
DRVCC
VOLTAGE
DRVCC UVLO
RISING / FALLING
THRESHOLDS
EXTVCC
SWITCHOVER
THRESHOLD
0V
6V
4.0V / 3.8V
4.7V
INTVCC
10V
7.5V / 6.7V
7.7V
Resistor to GND
50k to 100k
5V to 10V
4.0V / 3.8V
4.7V
11
DRVCC VOLTAGE (V)
10
9
8
7
6
5
4
50 55 60 65 70 75 80 85 90 95 100
DRVSET PIN RESISTOR (kΩ)
3899 F10
Figure 9. Relationship Between DRVCC Voltage
and Resistor Value at DRVSET Pin
26
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3899 to be
exceeded. The DRVCC current, which is dominated by the
gate charge current, may be supplied by either the VBIAS
LDO or the EXTVCC LDO. When the voltage on the EXTVCC
pin is less than its switchover threshold (4.7V or 7.7V as
determined by the DRVSET pin described above), the VBIAS
LDO is enabled. Power dissipation for the IC in this case
is highest and is equal to VBIAS • IDRVCC. The gate charge
current is dependent on operating frequency as discussed
in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given
in Note 2 of the Electrical Characteristics. For example,
using the LTC3899 in the QFN package, the DRVCC current
is limited to less than 40mA from a 40V supply when not
using the EXTVCC supply at a 70°C ambient temperature:
TJ = 70°C + (40mA)(40V)(34°C/W) = 125°C
To prevent the maximum junction temperature from being exceeded, the VBIAS supply current must be checked
while operating in forced continuous mode (PLLIN/MODE
= INTVCC) at maximum VBIAS.
When the voltage applied to EXTVCC rises above its
switch­over threshold, the VBIAS LDO is turned off and the
EXTVCC LDO is enabled. The EXTVCC LDO remains on as
long as the voltage applied to EXTVCC remains above the
switchover threshold minus the comparator hysteresis.
The EXTVCC LDO attempts to regulate the DRVCC voltage
to the voltage as programmed by the DRVSET pin, so while
EXTVCC is less than this voltage, the LDO is in dropout
and the DRVCC voltage is approximately equal to EXTVCC.
When EXTVCC is greater than the programmed voltage,
up to an absolute maximum of 14V, DRVCC is regulated
to the programmed voltage.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from one of the LTC3899’s
switching regulator outputs (4.7V/7.7V ≤ VOUT ≤ 14V)
during normal operation and from the VBIAS LDO when
the output is out of regulation (e.g., start-up, short circuit).
If more current is required through the EXTVCC LDO than
is specified, an external Schottky diode can be added
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between the EXTVCC and DRVCC pins. In this case, do not
apply more than 10V to the EXTVCC pin and make sure
that EXTVCC ≤ VBIAS.
Significant efficiency and thermal gains can be realized
by powering DRVCC from the output, since the VIN current resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
For 5V to 14V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to
an 8.5V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + (40mA)(8.5V)(34°C/W) = 82°C
However, for 3.3V and other low voltage outputs, additional
circuitry is required to derive DRVCC power from the output.
The following list summarizes the four possible connections for EXTVCC:
1.EXTVCC grounded. This will cause DRVCC to be powered
from the internal VBIAS regulator resulting in increased
power dissipation in the LTC3899 at high input voltages.
2. EXTVCC connected directly to the output of one of the
buck regulators. This is the normal connection for a 5V
to 14V regulator and provides the highest efficiency.
3. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 14V range, it may be
used to power EXTVCC providing it is compatible with
the MOSFET gate drive requirements. Ensure that
EXTVCC < VBIAS.
4. EXTVCC connected to an output-derived boost network
off one of the buck regulators. For 3.3V and other low
voltage regulators, efficiency gains can still be realized
by connecting EXTVCC to an output-derived voltage that
has been boosted to greater than 4.7V/7.7V.
Topside MOSFET Driver Supply (CB)
External bootstrap capacitors, CB, connected to the BOOST
pins supply the gate drive voltage for the topside MOSFET.
The LTC3899 features an internal switch between DRVCC
and the BOOST pin for each controller. These internal
switches eliminate the need for external bootstrap diodes
between DRVCC and BOOST. Capacitor CB in the Functional
Diagram is charged through this internal switch from DRVCC
when the SW pin is low. When the topside MOSFET is to
be turned on, the driver places the CB voltage across the
gate-source of the MOSFET. This enhances the top MOSFET switch and turns it on. The switch node voltage, SW,
rises to VIN and the BOOST pin follows. With the topside
MOSFET on, the boost voltage is above the input supply:
VBOOST = VIN + VDRVCC (VBOOST = VOUT + VDRVCC for the
boost controller). The value of the boost capacitor, CB,
needs to be 100 times that of the total input capacitance
of the topside MOSFET(s).
Fault Conditions: Buck Current Limit and
Current Foldback
The LTC3899 includes current foldback for the buck channels to help limit load current when the output is shorted
to ground. If the buck output voltage falls below 70% of
its nominal output level, then the maximum sense voltage is progressively lowered from 100% to 40% of its
maximum selected value. Under short-circuit conditions
with very low duty cycles, the buck channel will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
on-time, tON(MIN), of the LTC3899 (≈80ns), the input voltage and inductor value:
V 
∆IL(SC) = tON(MIN)  IN 
 L 
The resulting average short-circuit current is:
1
ISC = 40% •ILIM(MAX) − ∆IL(SC)
2
Fault Conditions: Buck Overvoltage Protection
(Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of one of the buck
regulators rises much higher than nominal levels. The
crowbar causes huge currents to flow, that blow the fuse
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LTC3899
APPLICATIONS INFORMATION
to protect against a shorted top MOSFET if the short occurs while the controller is operating.
A comparator monitors the buck output for overvoltage
conditions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously for
as long as the overvoltage condition persists; if VOUT returns
to a safe level, normal operation automatically resumes.
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on chip
(such as DRVCC short to ground), the overtemperature
shutdown circuitry will shut down the LTC3899. When the
junction temperature exceeds approximately 175°C, the
overtemperature circuitry disables the DRVCC LDO, causing
the DRVCC supply to collapse and effectively shutting down
the entire LTC3899 chip. Once the junction temperature
drops back to the approximately 155°C, the DRVCC LDO
turns back on. Long-term overstress (TJ > 125°C) should
be avoided as it can degrade the performance or shorten
the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC3899 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked
to the rising edge of an external clock signal applied to
the PLLIN/MODE pin. The turn-on of controller 2’s top
MOSFET is thus 180° out of phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
28
If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
Note that the LTC3899 can only be synchronized to an
external clock whose frequency is within range of the
LTC3899’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Typically, the external clock (on the PLLIN/MODE pin)
input high threshold is 1.6V, while the input low threshold
is 1.1V. The LTC3899 is guaranteed to synchronize to an
external clock that swings up to at least 2.5V and down
to 0.5V or less.
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock and
synchronization. Although it is not required that the freerunning frequency be near the external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
FREQ PIN
0V
PLLIN/MODE PIN
DC Voltage
FREQUENCY
350kHz
INTVCC
DC Voltage
535kHz
Resistor to GND
DC Voltage
50kHz to 900kHz
Any of the Above
External Clock
75kHz to 850kHz
Phase Locked to
External Clock
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Efficiency Considerations
1000
900
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
FREQUENCY (kHz)
800
700
600
500
400
300
200
%Efficiency = 100% – (L1 + L2 + L3 + ...)
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
3899 F11
Figure 10. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3899 is capable of turning on the top MOSFET
(bottom MOSFET for the boost controller). It is determined
by internal timing delays and the gate charge required to
turn on the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
tON(MIN)_BUCK <
VOUT
VIN(f)
tON(MIN)_BOOST <
VOUT − VIN
VOUT (f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3899 is approximately
80ns for the bucks and 120ns for the boost. However, for
the buck channels as the peak sense voltage decreases
the minimum on-time gradually increases up to about
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3899 circuits: 1) IC VBIAS current, 2) DRVCC
regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. The VBIAS current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET driver and control currents. VBIAS current typically
results in a small (<0.1%) loss.
2. DRVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from DRVCC to ground. The resulting dQ/dt is a current out of DRVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
Supplying DRVCC from an output-derived source power
through EXTVCC will scale the VIN current required for
the driver and control circuits by a factor of (Duty Cycle)/
(Efficiency). For example, in a 20V to 5V application,
10mA of DRVCC current results in approximately 2.5mA
of VIN current. This reduces the midcurrent loss from
10% or more (if the driver was powered directly from
VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor and input and output capacitor ESR. In continuous
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LTC3899
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mode the average output current flows through L and
RSENSE, but is chopped between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs
have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the
resistances of L, RSENSE and ESR to obtain I2R losses.
For example, if each RDS(ON) = 30mΩ, RL = 50mΩ,
RSENSE = 10mΩ and RESR = 40mΩ (sum of both input
and output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the top MOSFET(s) (bottom MOSFET for the boost), and become significant
only when operating at high input (output for the boost)
voltages (typically 20V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) • VIN2 • IO(MAX) • CRSS • f
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20μF to 40μF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses including Schottky conduction losses during
dead-time and inductor core losses generally account
for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
30
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD(ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response to
be optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC-coupled and AC-filtered closed-loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming
a predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin. The
ITH external components shown in Figure 12 circuit will
provide an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop response.
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by de3899fa
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creasing CC. If RC is increased by the same factor that CC
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise-time
should be controlled so that the load rise-time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
Buck Design Example
As a design example for one channel, assume VIN = 12V
(nominal), VIN = 22V (maximum), VOUT = 3.3V, IMAX =
5A, VSENSE(MAX) = 75mV and f = 350kHz. The inductance
value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at
the maximum input voltage. Tie the FREQ pin to GND,
generating 350kHz operation. The minimum inductance
for 30% ripple current is:


V
V


∆IL = OUT  1− OUT 
( f ) (L )  VIN(NOM) 
VOUT
VIN(MAX) ( f )
=
RSENSE ≤
65mV
≈ 0.01Ω
5.73A
Choosing 1% resistors: RA = 25k and RB = 78.7k yields
an output voltage of 3.32V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF.
At maximum input voltage with T(estimated) = 50°C:
PMAIN =
3.3V
( 5A )2  1+ ( 0.005) ( 50°C− 25°C)
22V
5A
( 0.035Ω) + ( 22V )2 ( 2.5Ω) ( 215pF ) •
2


1 
1

 6V − 2.3V + 2.3V  ( 350kHz ) = 308mW


A short-circuit to ground will result in a folded back current of:
ISC =
34mV 1  80ns ( 22V ) 
− 
 = 3.21A
0.01Ω 2  4.7µH 
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
PSYNC = (3.21A)2 (1.125) (0.022Ω) = 255mW
which is less than under full-load conditions.
A 4.7μH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 80ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN) =
The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (65mV):
3.3V
= 429ns
22V ( 350kHz )
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VO(RIPPLE) = RESR (∆IL) = 0.02Ω (1.45A) = 29mVP-P
3899fa
For more information www.linear.com/LTC3899
31
LTC3899
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. Figure 11 illustrates the current waveforms present in
the various branches of the 2-phase synchronous buck
regulators operating in the continuous mode. Check the
following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at CIN? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
SW1
of CDRVCC must return to the combined COUT (–) terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Does the LTC3899 VFB pins’ resistive divider connect to
the (+) terminal of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
L1
RSENSE1
VOUT1
COUT1
RL1
VIN
RIN
CIN
SW2
L2
RSENSE2
VOUT2
COUT2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
RL2
3899 F12
Figure 11. Branch Current Waveforms for Bucks
32
3899fa
For more information www.linear.com/LTC3899
LTC3899
APPLICATIONS INFORMATION
4. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
5. Is the DRVCC and decoupling capacitor connected close
to the IC, between the DRVCC and the ground pin? This
capacitor carries the MOSFET drivers’ current peaks.
6. Keep the switching nodes (SW1, SW2, SW3), top gate
(TG1, TG2, TG3), and boost nodes (BOOST1, BOOST2,
BOOST3) away from sensitive small-signal nodes,
especially from the opposites channel’s voltage and
current sensing feedback pins. All of these nodes have
very large and fast moving signals and therefore should
be kept on the output side of the LTC3899 and occupy
minimum PC trace area.
7. Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the DRVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
drops below the low current operation threshold—typically 25% of the maximum designed current level in Burst
Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
both should multiple controllers be turned on at the same
time. A particularly difficult region of operation is when
one buck channel is nearing its current comparator trip
point when the other buck channel is turning on its top
MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
3899fa
For more information www.linear.com/LTC3899
33
LTC3899
TYPICAL APPLICATIONS
VOUT1
RB1
357k
RA1
68.1k
VFB1
LTC3899
CITH1A 100pF
CITH1 1500pF
TG1
RITH1
15k
ITH1
VOUT2
RB2
649k
RA2
68.1k
RITH2
15k
VOUT1
5V
COUT1B 5A
22µF
MBOT2
COUT2A
68µF
VOUT2
8.5V
COUT2B 3A
4.7µF
MTOP3
COUT3A
33µF
COUT3B
2.2µF
×6
CIN1
33µF
×2
CIN2
2.2µF
×3
MBOT1
BG1
CITH2A 68pF
ITH2
TRACK/SS2
RITH3
3.6k
CITH3A 820pF
CDRVCC
4.7µF
DRVCC
EXTVCC
TG2
VFB3
CBIAS
0.1µF
GND
CSS2 0.1µF
VOUT3
C1
1nF
SENSE1–
RUN1
RUN2
RUN3
VBIAS
VFB2
MTOP2
CB2 0.1µF
L2
6.5µH
BOOST2
SW2
ITH3
BG2
SENSE2+
CSS3 0.1µF
SS3
SENSE2–
L3
1.2µH
SENSE3–
SENSE3+
RSNS3
3mΩ
MBOT3
BG3
INTVCC
RSNS2
15mΩ
C2
1nF
TG3
FREQ
CB3 0.1µF
PLLIN/MODE
DRVSET
BOOST3
VPRG3
SW3
CINTVCC
0.1µF
RSNS1
9mΩ
COUT1A
220µF
SW1
TRACK/SS1 SENSE1+
CITH3
10nF
L1
4.9µH
BOOST1
CSS1 0.1µF
CITH2 2200pF
MTOP1
CB1 0.1µF
VOUT3
10V*
VIN
2.2V TO 60V
(START-UP ABOVE 5V)
*VOUT3 IS 10V WHEN VIN < 10V,
FOLLOWS VIN WHEN VIN > 10V
C3
1nF
3899 TA02
Figure 12. High Efficiency Wide Input Range Dual 5V/8.5V Converter
Efficiency and Power Loss
10k
100
VIN = 12V
90 VOUT = 5V
EFFICIENCY (%)
80
EFFICIENCY
1k
70
100
60
50
40
10
POWER LOSS
30
POWER LOSS (mW)
MTOP1, MBOT1: BSZ123N08NS3
MTOP2, MBOT2: BSZ123N08NS3
MTOP3, MBOT3: BSC042NE7NS3
L1: WURTH 744314490
L2: WURTH 744314650
L3: WURTH 744325120
COUT1A: SANYO 6TPB220ML
COUT2A: SANYO 10TPC68M
CIN1, COUT3A: SUNCON 63HVP33M
vs Load
Efficiency
andCurrent
Power Loss vs Load Current
1
20
10
0
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
0.1
3899 TA02b
34
3899fa
For more information www.linear.com/LTC3899
LTC3899
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)
Exposed Pad Variation AA
4.75 REF
38
9.60 – 9.80*
(.378 – .386)
4.75 REF
(.187)
20
6.60 ±0.10
4.50 REF
2.74 REF
SEE NOTE 4
6.40
2.74
REF (.252)
(.108)
BSC
0.315 ±0.05
1.05 ±0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1
0.25
REF
19
1.20
(.047)
MAX
0° – 8°
0.50
(.0196)
BSC
0.17 – 0.27
(.0067 – .0106)
TYP
0.05 – 0.15
(.002 – .006)
FE38 (AA) TSSOP REV C 0910
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3899fa
For more information www.linear.com/LTC3899
35
LTC3899
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ±0.05
5.50 ±0.05
5.15 ±0.05
4.10 ±0.05
3.00 REF
3.15 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
5.5 REF
6.10 ±0.05
7.50 ±0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 ±0.05
5.00 ±0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ±0.10
5.50 REF
7.00 ±0.10
3.15 ±0.10
(UH) QFN REF C 1107
0.200 REF 0.25 ±0.05
R = 0.125
TYP
0.50 BSC
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
36
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3899fa
For more information www.linear.com/LTC3899
LTC3899
REVISION HISTORY
REV
DATE
DESCRIPTION
A
09/15
Clarified INTVCC Pin Functions
PAGE NUMBER
SW1, SW2, SW3 pin callouts corrected
Block Diagram modified
11
11
13, 14
3899fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC3899
37
LTC3899
TYPICAL APPLICATION
VOUT1
RB1
215k
RA1
68.1k
VFB1
LTC3899
CITH1A 100pF
ITH1
RB2
357k
CITH2 2.2nF
RITH2
12.7k
VFB2
ITH2
CITH2A 100pF
CSS2 0.1µF
TRACK/SS2
RB3
232k
RA3
12.1k
CITH3
4.7nF
COUT1A
220µF
VOUT1
3.3V
COUT1B 8A
47µF
×2
RITH3
4.3k
CITH3A 220pF
VFB3
MBOT2
COUT2A
220µF
VOUT2
5V
COUT2B 8A
47µF
×2
ITH3
MTOP3
COUT3A
33µF
VOUT3
24V
COUT3B 5A
2.2µF
×6
CIN1
33µF
×2
CIN2
2.2µF
×3
C1
1nF
SENSE1–
RUN1
RUN2
RUN3
VBIAS
CBIAS
0.1µF
GND
CDRVCC
4.7µF
DRVCC
EXTVCC
TG2
VOUT3
MTOP2
CB2 0.1µF
L2
3.3µH
BOOST2
SW2
BG2
SENSE2+
CSS3 0.1µF
RSNS1
6mΩ
MBOT1
BG1
TRACK/SS1 SENSE1+
RA2
68.1k
L1
2.4µH
SW1
CSS1 0.1µF
VOUT2
MTOP1
CB1 0.1µF
BOOST1
RITH1
10k
CITH1 1500pF
TG1
SENSE2–
RSNS2
6mΩ
C2
1nF
SS3
MTOP1, MTOP2: BSC057N08NS3
MBOT1, MBOT2: BSC036NE7NS3
MTOP3, MBOT3: BSC042NE7NS3
L1: WÜRTH 744325240
L2: WÜRTH 744325330
L3: WÜRTH 7443551370
COUT1A, COUT2A: 6TPB220ML
CIN1, COUT3A: SUNCON 63HVP33M
TG3
FREQ
CB3 0.1µF
PLLIN/MODE
DRVSET
BOOST3
VPRG3
SW3
CINTVCC
0.1µF
L3
3.7µH
MBOT3
BG3
INTVCC
SENSE3–
SENSE3+
RSNS3
6mΩ
C3
1nF
VIN
12V TO 60V
*VOUT3 IS 24V WHEN VIN < 24V,
FOLLOWS VIN WHEN VIN > 24V
3899 TA03
Figure 13. High Efficiency Triple 24V/3.3V/5V Converter with 10V Gate Drive
RELATED PARTS
PART NUMBER
LTC3859AL
COMMENTS
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V,
IQ = 28µA, Buck VOUT Range: 0.8V to 24V, Boost VOUT Up to 60V
LTC3892/LTC3892-1
PLL Fixed Frequency 50kHz to 900kHz, 4.5V ≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ 0.99VIN, IQ = 29µA
LTC3769
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, IQ = 28µA,
PLL Fixed Frequency 50kHz to 900kHz, 4mm × 4mm QFN-24, TSSOP-20E
LTC3784
Low IQ, Multiphase, Dual Channel Single Output
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V,
Synchronous Step-Up DC/DC Controller
PLL Fixed Frequency 50kHz to 900kHz , IQ = 28µA
LTC3890/LTC3890-1 60V, Low IQ, Dual 2-Phase Synchronous Step-Down PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,
LTC3890-2/LTC3890-3 DC/DC Controller with 99% Duty Cycle
0.8V ≤ VOUT ≤ 24V, IQ = 50µA
LTC3891
60V, Low IQ, Synchronous Step-Down DC/DC
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,
Controller with 99% Duty Cycle
0.8V ≤ VOUT ≤ 24V, IQ = 50µA
LTC3857/LTC3857-1 Low IQ, Dual Output 2-Phase Synchronous StepPhase-Lockable Fixed Operating Frequency 50kHz to 900kHz,
LTC3858/LTC3858-1 Down DC/DC Controller with 99% Duty Cycle
4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA/170µA
LTC3864
60V, Low IQ, High Voltage DC/DC Controller with
Fixed Frequency 50kHz to 850kHz, 3.5V ≤ VIN ≤ 60V,
100% Duty Cycle
0.8V ≤ VOUT ≤ VIN, IQ = 40µA, MSOP-12E, 3mm × 4mm DFN-12
LT®8705
80V VIN and VOUT Synchronous 4-Switch
VIN Range: 2.8V (Need EXTVCC > 6.4V) to 80V,
Buck-Boost DC/DC Controller
VOUT Range: 1.3V to 80V; 4 Regulation Loops
38
DESCRIPTION
Triple Output, Buck/Buck/Boost Synchronous
Controller with 28µA Burst Mode IQ
60V, Low IQ, Dual 2-Phase Synchronous Step-Down
DC/DC Controller with 99% Duty Cycle
Low IQ Synchronous Step-Up DC/DC Controller
3899fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3899
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3899
LT 0915 REV A • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2015