VS-VSKT71.., VS-VSKH71.., VS-VSKL71.., VS-VSKN71.. Series www.vishay.com Vishay Semiconductors ADD-A-PAK Generation VII Power Modules Thyristor/Diode and Thyristor/Thyristor, 75 A FEATURES • High voltage • Industrial standard package • Low thermal resistance • UL approved file E78996 • Designed and qualified for industrial level • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 BENEFITS ADD-A-PAK • Excellent thermal performances obtained by the usage of exposed direct bonded copper substrate PRODUCT SUMMARY • Up to 1600 V IT(AV) or IF(AV) 75 A Type Modules - Thyristor, Standard • High surge capability • Easy mounting on heatsink MECHANICAL DESCRIPTION ELECTRICAL DESCRIPTION The ADD-A-PAK Generation VII, new generation of ADD-A-PAK module, combines the excellent thermal performances obtained by the usage of exposed direct bonded copper substrate, with advanced compact simple package solution and simplified internal structure with minimized number of interfaces. These modules are intended for general purpose high voltage applications such as high voltage regulated power supplies, lighting circuits, temperature and motor speed control circuits, UPS and battery charger. MAJOR RATINGS AND CHARACTERISTICS SYMBOL CHARACTERISTICS VALUES IT(AV) or IF(AV) 85 °C IO(RMS) As AC switch 165 ITSM, IFSM 50 Hz 1300 60 Hz 1360 I2t 50 Hz 8.45 60 Hz 7.68 I2t VRRM 84.5 Range UNITS 75 A kA2s kA2s 400 to 1600 V TStg -40 to 125 °C TJ -40 to 125 °C Revision: 21-Mar-14 Document Number: 94631 1 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT71.., VS-VSKH71.., VS-VSKL71.., VS-VSKN71.. Series www.vishay.com Vishay Semiconductors ELECTRICAL SPECIFICATIONS VOLTAGE RATINGS TYPE NUMBER VOLTAGE CODE VRRM, MAXIMUM REPETITIVE PEAK REVERSE VOLTAGE V VRSM, MAXIMUM NON-REPETITIVE PEAK REVERSE VOLTAGE V VDRM, MAXIMUM REPETITIVE PEAK OFF-STATE VOLTAGE, GATE OPEN CIRCUIT V 04 400 500 400 06 600 700 600 VS-VSK.71 08 800 900 800 10 1000 1100 1000 12 1200 1300 1200 14 1400 1500 1400 16 1600 1700 1600 IRRM, IDRM AT 125 °C mA 15 ON-STATE CONDUCTION PARAMETER SYMBOL Maximum average on-state current (thyristors) IT(AV) Maximum average forward current (diodes) IF(AV) Maximum continuous RMS on-state current, as AC switch TEST CONDITIONS 180° conduction, half sine wave, TC = 85 °C IO(RMS) I(RMS) t = 10 ms Maximum peak, one-cycle non-repetitive on-state or forward current ITSM or IFSM t = 8.3 ms t = 10 ms t = 8.3 ms t = 10 ms Maximum I2t for fusing I2t t = 8.3 ms t = 10 ms t = 8.3 ms Maximum I2t for fusing Maximum value or threshold voltage Maximum value of on-state slope resistance Maximum peak on-state or forward voltage Maximum non-repetitive rate of rise of turned on current I2t (1) VT(TO) (2) rt (2) VALUES or No voltage reapplied 100 % VRRM reapplied 75 I(RMS) 165 A 1300 Sinusoidal half wave, initial TJ = TJ maximum 1360 1093 1140 8.45 No voltage reapplied 100 % VRRM reapplied Initial TJ = TJ maximum 7.68 5.97 84.5 Low level (3) 0.96 Low level (3) High level (4) VTM ITM = x IT(AV) VFM IFM = x IF(AV) dI/dt TJ = TJ maximum TJ = TJ maximum TJ = 25 °C kA2s 5.45 t = 0.1 ms to 10 ms, no voltage reapplied TJ = TJ maximum High level (4) UNITS 1.08 3.28 2.86 kA2s V m 1.72 V TJ = 25 °C, from 0.67 VDRM, ITM = x IT(AV), Ig = 500 mA, tr < 0.5 μs, tp > 6 μs 150 A/μs Maximum holding current IH TJ = 25 °C, anode supply = 6 V, resistive load, gate open circuit 250 Maximum latching current IL TJ = 25 °C, anode supply = 6 V, resistive load 400 mA Notes (1) I2t for time t = I2t x t x x (2) Average power = V 2 T(TO) x IT(AV) + rt x (IT(RMS)) (3) 16.7 % x x I AV < I < x IAV (4) I > x I AV Revision: 21-Mar-14 Document Number: 94631 2 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT71.., VS-VSKH71.., VS-VSKL71.., VS-VSKN71.. Series www.vishay.com Vishay Semiconductors TRIGGERING PARAMETER SYMBOL Maximum peak gate power Maximum average gate power Maximum peak gate current Maximum peak negative gate voltage TEST CONDITIONS VALUES PGM 12 PG(AV) 3.0 IGM 3.0 - VGM VGT Anode supply = 6 V resistive load TJ = 25 °C V 2.5 1.7 270 TJ = -40 °C IGT A 4.0 TJ = 125 °C Maximum gate current required to trigger W 10 TJ = -40 °C Maximum gate voltage required to trigger UNITS Anode supply = 6 V resistive load TJ = 25 °C mA 150 TJ = 125 °C 80 Maximum gate voltage that will not trigger VGD TJ = 125 °C, rated VDRM applied 0.25 V Maximum gate current that will not trigger IGD TJ = 125 °C, rated VDRM applied 6 mA VALUES UNITS 15 mA 3000 (1 min) 3600 (1 s) V 1000 V/μs VALUES UNITS -40 to 125 °C BLOCKING PARAMETER SYMBOL TEST CONDITIONS Maximum peak reverse and off-state leakage current at VRRM, VDRM IRRM, IDRM TJ = 125 °C, gate open circuit Maximum RMS insulation voltage VINS 50 Hz Maximum critical rate of rise of off-state voltage dV/dt TJ = 125 °C, linear to 0.67 VDRM THERMAL AND MECHANICAL SPECIFICATIONS PARAMETER SYMBOL Junction operating and storage temperature range TEST CONDITIONS TJ, TStg Maximum internal thermal resistance, junction to case per leg RthJC DC operation 0.29 Typical thermal resistance, case to heatsink per module RthCS Mounting surface flat, smooth and greased 0.1 °C/W A mounting compound is recommended and the torque should be rechecked after a period of 3 hours to allow for the spread of the compound. to heatsink Mounting torque ± 10 % busbar 4 Nm 3 Approximate weight JEDEC® Case style 75 g 2.7 oz. AAP GEN VII (TO-240AA) R CONDUCTION PER JUNCTION DEVICES VSK.71.. SINE HALF WAVE CONDUCTION RECTANGULAR WAVE CONDUCTION 180° 120° 90° 60° 30° 180° 120° 90° 60° 30° 0.052 0.062 0.079 0.116 0.197 0.037 0.064 0.085 0.121 0.200 UNITS °C/W Note • Table shows the increment of thermal resistance RthJC when devices operate at different conduction angles than DC Revision: 21-Mar-14 Document Number: 94631 3 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT71.., VS-VSKH71.., VS-VSKL71.., VS-VSKN71.. Series RthJC (DC) = 0.29°C/W 120 110 100 90 180° 120° 90° 60° 30° 80 70 10 20 30 40 50 60 70 180 180° 120° 90° 60° 30° 160 140 120 100 DC RMS limit 80 60 40 20 Per leg, Tj = 125°C 0 80 0 20 40 60 80 100 120 Average on-state current (A) Average on-state current (A) Fig. 1 - Current Ratings Characteristics Fig. 4 - On-State Power Loss Characteristics 1200 130 RthJC (DC) = 0.29°C/W Peak half sine wave on-state current (A) Maximum allowable case temperature (°C) Maximum average on-state power loss (W) 130 0 120 110 100 DC 180° 120° 90° 60° 30° 90 80 70 0 Maximum average on-state power loss (W) Vishay Semiconductors 20 40 60 80 100 At any rated load condition and with rated Vrrm applied following surge Initial Tj = Tj max @ 60 Hz 0.0083 s @ 50 Hz 0.0100s 1100 1000 900 800 700 600 Per leg 500 120 1 10 100 Average on-state current (A) Number of equal amplitude half cycle current pulses (N) Fig. 2 - Current Ratings Characteristics Fig. 5 - Maximum Non-Repetitive Surge Current 140 1400 180° 120° 90° 60° 30° 120 100 Peak half sine wave on-state current (A) Maximum allowable case temperature (°C) www.vishay.com 80 RMS limit 60 40 20 Per leg, Tj = 125°C 0 0 10 20 30 40 50 60 70 80 Average on-state current (A) Fig. 3 - On-State Power Loss Characteristics 1200 1000 Maximum Non-repetitive Surge Current Versus Pulse Train Duration. Control of conduction may not be maintained. Initial Tj = 125°C No Voltage Reapplied Rated Vrrm reapplied 800 600 Per leg 400 0.01 0.1 1 Pulse train duration (s) Fig. 6 - Maximum Non-Repetitive Surge Current Revision: 21-Mar-14 Document Number: 94631 4 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT71.., VS-VSKH71.., VS-VSKL71.., VS-VSKN71.. Series www.vishay.com Vishay Semiconductors Maximum total on-state power loss (W) 300 RthSA = 0.1 °C/W 0.2 °C/W 0.3 °C/W 0.4 °C/W 0.5 °C/W 0.7 °C/W 1 °C/W 1.5 °C/W 3 °C/W 180° 120° 90° 60° 30° 250 200 150 100 VSK.71 Series Per module Tj = 125°C 50 0 0 20 40 60 80 100 120 140 160 180 0 20 Total RMS output current (A) 40 60 80 100 120 140 Maximum allowable ambient temperature (°C) Fig. 7 - On-State Power Loss Characteristics Maximum total power loss (W) 700 RthSA = 0.1 °C/W 0.2 °C/W 0.3 °C/W 0.5 °C/W 1 °C/W 2 °C/W 180° (sine) 180° (rect) 600 500 400 ∼ 300 200 2 x VSK.71 Series single phase bridge connected Tj = 125°C 100 0 0 0 20 40 60 80 100 120 140 160 180 20 40 60 80 100 120 140 Maximum allowable ambient temperature (°C) Total output current (A) Fig. 8 - On-State Power Loss Characteristics Maximum total power loss (W) 800 RthSA = 0.1 °C/W 0.2 °C/W 0.3 °C/W 0.5 °C/W 1 °C/W 700 600 500 120° (rect) 400 300 200 3 x VSK.71 Series three phase bridge connected Tj = 125°C 100 0 0 40 80 120 160 Total output current (A) 200 0 20 40 60 80 100 120 140 Maximum allowable ambient temperature (°C) Fig. 9 - On-State Power Loss Characteristics Revision: 21-Mar-14 Document Number: 94631 5 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT71.., VS-VSKH71.., VS-VSKL71.., VS-VSKN71.. Series www.vishay.com Vishay Semiconductors Instantaneous on-state current (A) 1000 Per leg 100 10 Tj = 125°C Tj = 25°C 1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Instantaneous on-state voltage (V) Transient thermal impedance Z thJC (°C/W) Fig. 10 - On-State Voltage Drop Characteristics 1 Steady state value RthJC = 0.29 °C/W (DC operation) 0.1 Per leg 0.01 0.001 0.01 0.1 1 10 Square wave pulse duration (s) Fig. 11 - Thermal Impedance ZthJC Characteristics Rec tangular ga te pulse a )Recommend ed load line for ra ted di/ d t: 20 V, 20 ohms tr = 0.5 µs, tp >= 6 µs b )Recommend ed load line for <= 30% rated di/ dt: 15 V, 40 ohms 10 tr = 1 µs, tp >= 6 µs (1) PGM = 200 W, tp = 300 µs (2) PGM = 60 W, tp = 1 ms (3) PGM = 30 W, tp = 2 ms (4) PGM = 12 W, tp = 5 ms (a) (b) 1 TJ = -40 °C TJ = 125 °C TJ = 25 °C Instantaneous gate voltage (V) 100 (4) (3) (2) (1) VGD IGD 0.1 0.001 0.01 IRK.71../ VSK.71 .91.. Series Frequenc y Limited by PG(AV) 0.1 1 10 100 1000 Instantaneous gate current (A) Fig. 12 - Gate Characteristics Revision: 21-Mar-14 Document Number: 94631 6 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT71.., VS-VSKH71.., VS-VSKL71.., VS-VSKN71.. Series www.vishay.com Vishay Semiconductors ORDERING INFORMATION TABLE Device code VS-VS K T 71 1 2 3 4 / 16 5 1 - Vishay Semiconductors product 2 - Module type 3 - Circuit configuration (see Circuit Configuration table) 4 - Current code (75 A) 5 - Voltage code (see Voltage Ratings table) Note • To order the optional hardware go to www.vishay.com/doc?95172 CIRCUIT CONFIGURATION CIRCUIT DESCRIPTION CIRCUIT CONFIGURATION CODE CIRCUIT DRAWING (1) ~ VSKT Two SCRs doubler circuit 1 + 2 T (2) 3 4 5 7 6 (3) G1 K1 K2 G2 (4) (5) (7) (6) (1) ~ VSKH SCR/diode doubler circuit, positive control 1 + 2 H (2) 3 4 5 (3) G1 K1 (4) (5) (1) ~ VSKL 1 SCR/diode doubler circuit, negative control 2 L + (2) 3 7 6 (3) K2 G2 (7) (6) (1) - VSKN SCR/diode common anodes 1 2 N + (2) 3 4 5 + (3) G1 K1 (4) (5) LINKS TO RELATED DOCUMENTS Dimensions www.vishay.com/doc?95368 Revision: 21-Mar-14 Document Number: 94631 7 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Outline Dimensions Vishay Semiconductors ADD-A-PAK Generation VII - Thyristor DIMENSIONS in millimeters (inches) 29 ± 0.5 (1 ± 0.020) 30 ± 0.5 (1.18 ± 0.020) 35 REF. 18 (0.7) REF. 30 ± 1 (1.18 ± 0.039) 15.5 ± 0.5 (0.6 ± 0.020) 24 ± 0.5 (1 ± 0.020) Viti M5 x 0.8 Screws M5 x 0.8 6.7 ± 0.3 (0.26 ± 0.012) Fast-on tab 2.8 x 0.8 (0.110 x 0.03) Document Number: 95368 Revision: 11-Nov-08 20 ± 0.5 (0.79 ± 0.020) 20 ± 0.5 (0.79 ± 0.020) 92 ± 0.75 (3.6 ± 0.030) 5.8 ± 0.25 (0.228 ± 0.010) 15 ± 0.5 (0.59 ± 0.020) For technical questions, contact: [email protected] 4 ± 0.2 (0.157 ± 0.008) 7 6 4 5 3 2 1 6.3 ± 0.2 (0.248 ± 0.008) 22.6 ± 0.2 (0.89 ± 0.008) 80 ± 0.3 (3.15 ± 0.012) www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000