Photodiode arrays with ampli¿er S8866-64/-128 Photodiode array combined with signal processing IC The S8866-64 and S8866-128 are Si photodiode arrays combined with a signal processing IC chip. The signal processing IC chip is formed by CMOS process and incorporates a timing generator, shift register, charge ampli¿er array, clamp circuit and hold circuit, making the external circuit con¿guration simple. For X-ray detection applications, types (S8866-64G-02, S8866128G-02) with phosphor sheet af¿xed on the photosensitive area are also available. Features Applications Large element pitch: 2 types available S8866-64: 1.6 mm pitch × 64 ch S8866-128: 0.8 mm pitch × 128 ch Long and narrow line sensors 5 V power supply operation Simultaneous integration by using a charge ampli¿er array Sequential readout with a shift register (Data rate: 500 kHz max.) Low dark current due to zero-bias photodiode operation Integrated clamp circuit allows low noise and wide dynamic range Integrated timing generator allows operation at two different pulse timings Structure Parameter Element pitch Element diffusion width Element height Number of elements Effective photosensitive area length Board material Symbol*1 P W H - S8866-64 1.6 1.5 1.6 64 102.4 S8866-128 0.8 0.7 0.8 128 102.4 Ceramic Unit mm mm mm mm - *1: Refer to following ¿gure. H Enlarged drawing of photosensitive area Photodiode W P KMPDC0072EA www.hamamatsu.com 1 Photodiode arrays with ampli¿er S8866-64/-128 Absolute maximum ratings Parameter Supply voltage Reference voltage Photodiode voltage Gain selection terminal voltage Master/slave selection voltage Clock pulse voltage Reset pulse voltage External start pulse voltage Operating temperature*2 Storage temperature Symbol Vdd Vref Vpd Vgain Vms V(CLK) V(RESET) V(EXTSP) Topr Tstg Value -0.3 to +6 -0.3 to +6 -0.3 to +6 -0.3 to +6 -0.3 to +6 -0.3 to +6 -0.3 to +6 -0.3 to +6 -5 to +60 -10 to +70 Unit V V V V V V V V °C °C *2: No condensation Recommended terminal voltage Parameter Symbol Vdd Vref Vpd Supply voltage Reference voltage Photodiode voltage Gain selection terminal voltage Master/slave selection voltage Clock pulse voltage Reset pulse voltage External start pulse voltage High gain Low gain High level*3 Low level*4 High level Low level High level Low level High level Low level Vgain Vms V(CLK) V(RESET) V(EXTSP) Min. 4.75 4 Vdd - 0.25 0 Vdd - 0.25 0 3.3 0 3.3 0 Vdd - 0.25 0 Typ. 5 4.5 Vref Vdd Vdd Vdd Vdd Vdd - Max. 5.25 4.6 Vdd + 0.25 0.4 Vdd + 0.25 0.4 Vdd + 0.25 0.4 Vdd + 0.25 0.4 Vdd + 0.25 0.4 Unit V V V V V V V V V V V V V *3: Parallel *4: Serial at 2nd or later stages Electrical characteristics [Ta=25 °C, Vdd=5 V, V(CLK)=V(RESET)=5 V] Parameter Symbol frequency*5 Clock pulse Line rate Output impedance Power consumption Charge amp feedback capacitance f(CLK) LR Zo P High gain Low gain Cf Min. 40 - S8866-64 Typ. Max. 2000 7800 3 100 0.5 1 - Min. 40 - S8866-128 Typ. Max. 2000 3900 3 180 0.5 1 - Unit kHz lines/s kΩ mW pF *5: Video data rate is 1/4 of clock pulse frequency f(CLK). 2 Photodiode arrays with ampli¿er S8866-64/-128 Electrical and optical characteristics [Ta=25 °C, Vdd=5 V, V (CLK)=V (RESET)=5 V, Vgain=5 V (High gain), 0 V (Low gain)] Parameter Symbol Spectral response range Peak sensitivity wavelength High gain Dark output voltage*6 Low gain Saturation output voltage High gain Saturation exposure*7 Low gain High gain Photo sensitivity Low gain Photo response non-uniformity*8 High gain Noise*9 Low gain Output offset voltage*10 λ λp Min. 3 14400 7200 - Vd Vsat Esat S PRNU N Vos S8866-64 Typ. 300 to 1000 720 0.01 0.005 3.5 0.2 0.4 18000 9000 2.0 1.1 Vref Max. Min. 0.2 0.1 0.25 0.5 ±10 3.0 1.7 - 3 3520 1760 - S8866-128 Typ. 300 to 1000 720 0.01 0.005 3.5 0.8 1.6 4400 2200 1.3 0.7 Vref Max. 0.2 0.1 1.0 2.0 ±10 2.0 1.1 - Unit nm nm mV V mlx · s V/lx · s % mVrms V *6: Integration time ts=1 ms *7: Measured with a 2856 K tungsten lamp. *8: When the photodiode array is exposed to uniform light which is 50% of the saturation exposure, the photo response non-uniformity (PRNU) is de¿ned as follows: PRNU = ΔX/X × 100 [%] X: average output of all elements, ΔX: difference between X and the maximum or minimum output, whichever is larger. *9: Measured with a video data rate of 50 kHz and ts=1 ms in dark state. *10: Video output is negative-going output with respect to the output offset voltage. Output waveform of one element Dark state Saturation output voltage Vsat=3.5 V typ. 1 V/div. Output offset voltage Vref=4.5 V typ. 1 V typ. Saturation state GND Trigger 10 V/div. GND CLK GND 200 ns/div. 3 Photodiode arrays with ampli¿er S8866-64/-128 Block diagram RESET 1 CLK 2 EXTSP Vms Vdd GND 4 5 6 7 Timing generator 3 TRIG Shift register 8 EOS 9 Video Vref 10 Hold circuit Vgain 11 Charge amp array Vpd 12 1 2 3 4 5 N-1 N Photodiode array KMPDC0153EA 4 Photodiode arrays with ampli¿er S8866-64/-128 Spectral response (measurement example) Output offset voltage vs. ambient temperature (measurement example) (Ta=25 °C) 0.5 4.505 4.504 4.503 Output offset voltage (V) Photo sensitivity (A/W) 0.4 0.3 0.2 0.1 4.502 4.501 4.500 4.499 4.498 4.497 4.496 4.495 0 200 400 600 800 1000 1200 0 10 20 30 40 50 60 Ambient temperature (°C) Wavelength (nm) KMPDB0275EA KMPDB0288EA Dark output voltage vs. ambient temperature (measurement example) (Ts=1000 ms) Dark output voltage (V) 1 0.1 0.01 0.001 0 10 20 30 40 50 60 Ambient temperature (°C) KMPDB0289EA 5 Photodiode arrays with ampli¿er S8866-64/-128 Timing chart S8866-64 1 2 3 20 clocks 4 5 14 15 16 17 18 19 20 1 2 3 CLK tpw(RESET1) RESET tpw(RESET2) 8 clocks 8 clocks Integration time Video output period Video 1 2 n-1 n Trig EOS tf(CLK) tr(CLK) t2 tpw(CLK1) t1 tf(RESET) tpw(RESET1) tpw(RESET2) tr(RESET) KMPDC0278EA Parameter Clock pulse width Clock pulse rise/fall times Reset pulse width 1 Reset pulse width 2 Reset pulse rise/fall times Clock pulse-reset pulse timing 1 Clock pulse-reset pulse timing 2 Symbol tpw(CLK) tr(CLK), tf(CLK) tpw(RESET1) tpw(RESET2) tr(RESET), tf(RESET) t1 t2 Min. 500 0 21 20 0 -20 -20 Typ. 20 20 0 0 Max. 25000 30 30 20 20 Unit ns ns CLK CLK ns ns ns 1. The internal timing circuit starts operation at the falling edge of CLK immediately after a RESET pulse goes Low. 2. When the falling edge of each CLK is counted as "1 clock", the video signal of the 1st channel appears between "18.5 clocks and 20 clocks". Subsequent video signals appear every 4 clocks. 3. To obtain video signals, extend the High period 3 clocks from the falling edge of CLK immediately after the RESET pulse goes Low, to a 20 clock period. 4. The trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. The rising edge of each trigger pulse is the recommended timing for data acquisition. 5. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the rise of a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the RESET pulse. After the RESET pulse next changes from High to Low, signals integrated within this period are sequentially read out as timeseries signals by the shift register operation. The rise and fall of a RESET pulse must be synchronized with the rise of a CLK pulse, but the rise of a RESET pulse must be set outside the video output period. One cycle of RESET pulses cannot be set shorter than the time equal to "36.5 + 4 × N (number of elements)" clocks. 6. The video signal after an EOS signal output becomes a high impedance state, and the video output will be inde¿nite. 6 Photodiode arrays with ampli¿er S8866-64/-128 S8866-128 1 2 3 4 5 14 15 16 17 18 19 20 1 2 3 CLK tpw(RESET1) RESET tpw(RESET2) 8 clocks 8 clocks Integration time Video output period Video 1 2 n-1 n Trig EOS tf(CLK) tr(CLK) t2 tpw(CLK) t1 tf(RESET) tpw(RESET1) tpw(RESET2) tr(RESET) KMPDC0289EA Parameter Clock pulse width Clock pulse rise/fall times Reset pulse width 1 Reset pulse width 2 Reset pulse rise/fall times Clock pulse-reset pulse timing 1 Clock pulse-reset pulse timing 2 Symbol tpw(CLK) tr(CLK), tf(CLK) tpw(RESET1) tpw(RESET2) tr(RESET), tf(RESET) t1 t2 Min. 500 0 21 20 0 -20 -20 Typ. 20 20 0 0 Max. 25000 30 30 20 20 Unit ns ns CLK CLK ns ns ns 1. The internal timing circuit starts operation at the falling edge of CLK immediately after a RESET pulse goes Low. 2. When the falling edge of each CLK is counted as "1 clock", the video signal of the 1st channel appears between "18.5 clocks and 20 clocks". Subsequent video signals appear every 4 clocks. 3. The trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. The rising edge of each trigger pulse is the recommended timing for data acquisition. 4. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the rise of a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the RESET pulse. After the RESET pulse next changes from High to Low, signals integrated within this period are sequentially read out as time-series signals by the shift register operation. The rise and fall of a RESET pulse must be synchronized with the rise of a CLK pulse, but the rise of a RESET pulse must be set outside the video output period. One cycle of RESET pulses cannot be set shorter than the time equal to "16.5 + 4 × N (number of elements)" clocks. 5. The video signal after an EOS signal output becomes a high impedance state, and the video output will be inde¿nite. 7 Photodiode arrays with ampli¿er S8866-64/-128 Dimensional outline (unit: mm) 110 ± 1.1 12 ± 0.5 25.4 P2.54 × 5 = 12.7 P2.54 × 5 = 12.7 1 A* 102.4 Direction of scan Signal processing IC chip Type no. A S8866-64 3.2 S8866-128 3.0 1.0 ± 0.1 10 1.5 max. 0.5 Photosensitive area 3.5 Photodiode 1 ch Silicon resin 12 0.5 0.25 * Length from the bottom of the board to the center of photosensitive area Board: Ceramic KMPDA0225EB Pin connections Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 Symbol RESET CLK Trig EXTSP Vms Vdd GND EOS Video Vref Vgain Vpd Name Reset pulse Clock pulse Trigger pulse External start pulse Master/slave selection supply voltage Supply voltage Ground End of scan Video output Reference voltage Gain selection terminal voltage Photodiode voltage Note Pulse input Pulse input Positive-going pulse output Pulse input Voltage input Voltage input Negative-going pulse output Negative-going output with respect to Vref Voltage input Voltage input Voltage input Gain selection terminal voltage setting Vdd: High gain (Cf=0.5 pF) GND: Low gain (Cf=1 pF) 8 Photodiode arrays with ampli¿er S8866-64/-128 Setting for each readout method Set to A in the table below in most cases. To serially read out signals from two or more sensors linearly connected, set the 1st sensor to A and the 2nd or later sensors to B. The CLK and RESET pulses should be shared with each sensor and the video output terminal of each sensor connected together. Setting Readout method A All stages of parallel readout, serial readout at 1st sensor B Serial readout at 2nd and later sensors Vms Vdd GND EXTSP Vdd Preceding sensor EOS should be input [Figure 1] Connection example (parallel readout) 12 Vpd 11 Vgain 10 Vref 9 Video 8 EOS 7 GND 6 Vdd 5 Vms 4 EXTSP Trig 3 Trig CLK 2 CLK RESET 1 RESET Vgain +4.5 V EOS 10 μF 0.1 μF +5 V + Video High impedance amplifier KMPDC0288EA Readout circuit Check that pulse signals meet the required pulse conditions before supplying them to the input terminals. Video output should be ampli¿ed by an operational ampli¿er that is connected close to the sensor. 9 Photodiode arrays with ampli¿er S8866-64/-128 Precautions for use (1) The signal processing IC chip is protected against static electricity. However, in order to prevent possible damage to the IC chip, take electrostatic countermeasures such as grounding yourself, as well as workbench and tools. Also protect the IC chip from surge voltages from peripheral equipment. (2) Gold wires for wire bonding are very thin, so they easily break if subjected to mechanical stress. The signal processing IC chip, wire bonding section and photodiode array chip are covered with resin for protection. However, never touch these portions. Excessive force, if applied, may break the wires or cause malfunction. Blow air to remove dust or debris if it gets on the protective resin. Never wash them with solvent. Signals may not be obtained if dust or debris is left or a scratch is made on the protective resin, or the signal processing IC chip or photodiode array chip is nicked. (3) The photodiode array characteristics may deteriorate when operated at high humidity, so put it in a hermetically sealed enclosure or case. When installing the photodiode array on a board, be careful not to cause the board to warp. Information described in this material is current as of May, 2011. Product specifications are subject to change without prior notice due to improvements or other reasons. Before assembly into final products, please contact us for the delivery specification sheet to check the latest information. Type numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(X)" which means preliminary specifications or a suffix "(Z)" which means developmental specifications. The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product use. Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. www.hamamatsu.com HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184 U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1 int. 6, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Cat. No. KMPD1104E02 May 2011 DN 10