s8865-64 etc kmpd1071e

Photodiode arrays with amplifier
S8865-64/-128/-256
S8866-64-02/-128-02
Photodiode array combined with signal
processing IC
The S8865-64/-128/-256 and S8866-64-02/-128-02 are Si photodiode arrays combined with a signal processing IC chip. The
signal processing IC chip is formed by CMOS process and incorporates a timing generator, shift register, charge amplifier array, clamp circuit and hold circuit, making the external circuit configuration simple. A long, narrow image sensor can also be
configured by arranging multiple arrays in a row. For X-ray detection applications, types with phosphor sheet affixed on the
photosensitive area are also available.
As the dedicated driver circuit, the C9118 series (sold separately) is provided. (Not compatible with the S8865-256 and
S8866-64-02.)
Features
Applications
Large element pitch: 5 types available
S8865-64: 0.8 mm pitch × 64 ch
S8865-128: 0.4 mm pitch × 128 ch
S8865-256: 0.2 mm pitch × 256 ch
S8866-64-02: 1.6 mm pitch × 64 ch
S8866-128-02: 0.8 mm pitch × 128 ch
Long and narrow line sensors
Line sensors for X-ray detection
5 V power supply operation
Simultaneous integration by using a charge amplifier array
Sequential readout with a shift register
(Data rate: 500 kHz max.)
Low dark current due to zero-bias photodiode operation
Integrated clamp circuit allows low noise and wide dynamic range
Integrated timing generator allows operation at two
different pulse timings
Types with phosphor sheet affixed on the photosensitive area
are available for X-ray detection
(S8865-64G/-128G/-256G, S8866-64G-02/-128G-02)
Structure
Parameter
Element pitch
Element width
Element height
Number of elements
Effective photosensitive area length
Board material
Symbol*1
P
W
H
-
S8865-64
0.8
0.7
0.8
64
51.2
S8865-128
0.4
0.3
0.6
128
51.2
S8865-256
0.2
0.1
0.3
256
51.2
Glass epoxy
S8866-64-02
1.6
1.5
1.6
64
102.4
S8866-128-02
0.8
0.7
0.8
128
102.4
Unit
mm
mm
mm
mm
-
*1: Refer to following figure.
Enlarged drawing of photosensitive area
KMPDC0072EA
www.hamamatsu.com
1
Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
Absolute maximum ratings
Parameter
Supply voltage
Reference voltage
Photodiode voltage
Gain selection terminal voltage
Master/slave selection voltage
Clock pulse voltage
Reset pulse voltage
External start pulse voltage
Operating temperature*2
Storage temperature*2
Symbol
Vdd
Vref
Vpd
Vgain
Vms
V(CLK)
V(RESET)
V(EXTSP)
Topr
Tstg
Value
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-5 to +60
-10 to +70
Unit
V
V
V
V
V
V
V
V
°C
°C
*2: No condensation
Recommended terminal voltage
Parameter
Supply voltage
Reference voltage
Photodiode voltage
High gain
Low gain
High level*3
Master/slave selection voltage
Low level*4
High level
Clock pulse voltage
Low level
High level
Reset pulse voltage
Low level
High level
External start pulse voltage
Low level
Gain selection terminal voltage
Symbol
Vdd
Vref
Vpd
Vgain
Vms
V(CLK)
V(RESET)
V(EXTSP)
Min.
4.75
4
Vdd - 0.25
0
Vdd - 0.25
0
3.3
0
3.3
0
Vdd - 0.25
0
Typ.
5
4.5
Vref
Vdd
Vdd
Vdd
Vdd
Vdd
-
Max.
5.25
4.6
Vdd + 0.25
0.4
Vdd + 0.25
0.4
Vdd + 0.25
0.4
Vdd + 0.25
0.4
Vdd + 0.25
0.4
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
Max.
2000
-
Unit
kHz
*3: Parallel
*4: Serial at 2nd or later stages
Electrical characteristics [Ta=25 °C, Vdd=5 V, V(CLK)=V(RESET)=5 V]
Parameter
Clock pulse frequency*5
S8865-64
S8865-128, S8866-128-02
Line rate
S8865-256
S8866-64-02
Output impedance
S8865-64, S8866-64-02
Power consumption
S8865-128, S8866-128-02
S8865-256
High gain
Charge amp feedback capacitance
Low gain
Symbol
f(CLK)
LR
Zo
P
Cf
Min.
40
-
Typ.
7339
3784
1922
6838
3
100
180
360
0.5
1
lines/s
kΩ
mW
pF
* 5: Video data rate is 1/4 of clock pulse frequency f(CLK).
2
Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
Electrical and optical characteristics [Ta=25 °C, Vdd=5 V, V(CLK)=V(RESET)=5 V, Vgain=5 V (High gain), 0 V (Low gain)]
S8865-64/-128/-256
Parameter
Spectral response range
Peak sensitivity wavelength
High gain
Dark output voltage*6
Low gain
Saturation output voltage
High gain
Saturation exposure*7
Low gain
High gain
Photo sensitivity
Low gain
Photo response non-uniformity*8
High gain
Noise*9
Low gain
Output offset voltage*10
Symbol
λ
λp
Vd
Vsat
Esat
S
PRNU
N
Vo
S8865-64
Min.
Typ.
Max.
200 to 1000
720
0.01
0.2
0.005
0.1
3.0
3.5
0.8
1.0
1.6
2.0
3520 4400
1760 2200
±10
1.3
2.0
0.7
1.1
Vref
-
S8865-128
Min.
Typ.
Max.
200 to 1000
720
0.01
0.2
0.005
0.1
3.0
3.5
2.4
3.0
4.8
6.0
1200 1500
600
750
±10
1.0
1.5
0.6
0.9
Vref
-
S8865-256
Min.
Typ.
Max.
200 to 1000
720
0.01
0.2
0.005
0.1
3.0
3.5
15
19
30
37.5
200
250
100
125
±10
0.8
1.2
0.5
0.75
Vref
-
Unit
nm
nm
mV
V
mlx · s
V/lx · s
%
mV rms
V
S8866-64-02/-128-02
Parameter
Symbol
Min.
S8866-64-02
Typ.
200 to 1000
720
0.01
0.005
3.5
0.2
0.4
18000
9000
2.0
1.1
Vref
Max.
Min.
S8866-128-02
Typ.
200 to 1000
720
0.01
0.005
3.5
0.8
1.6
4400
2200
1.3
0.7
Vref
Max.
Unit
nm
Spectral response range
λ
nm
Peak sensitivity wavelength
λp
High gain
0.2
0.2
Dark output voltage*6
Vd
mV
Low gain
0.1
0.1
Saturation output voltage
Vsat
3
3
V
High
gain
0.25
1.0
Saturation exposure*7
Esat
mlx · s
Low gain
0.5
2.0
High gain
14400
3520
Photo sensitivity
S
V/lx · s
Low gain
7200
1760
Photo response non-uniformity*8
PRNU
±10
±10
%
High
gain
3.0
2.0
Noise*9
N
mV rms
Low gain
1.7
1.1
Output offset voltage*10
Vo
V
*6: Integration time Ts=1 ms
*7: Measured with a 2856 K tungsten lamp.
*8: When the photodiode array is exposed to uniform light which is 50% of the saturation exposure, the photo response nonuniformity (PRNU) is defined as follows:
PRNU = ΔX/X × 100 [%]
X: average output of all elements, ΔX: difference between X and the maximum or minimum output, whichever is larger.
*9: Measured with a video data rate of 50 kHz and Ts=1 ms in dark state.
*10: Video output is negative-going output with respect to the output offset voltage.
3
Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
Output waveform of one element
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Output offset voltage vs. ambient temperature (measurement example)
Spectral response (measurement example)
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KMPDB0288EA
4
Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
Dark output voltage vs. ambient temperature (measurement example)
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Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
Timing chart
S8865-64/-128/-256, S8866-128-02
1 2 3
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3
CLK
tpw(RESET1)
RESET
tpw(RESET2)
8 clocks
8 clocks
Integration time
Video output period
1
Video
2
3
n-1
n
Trig
EOS
tf(CLK)
tr(CLK)
t2
tpw(CLK)
t1
tpw(RESET1)
tpw(RESET2)
KMPD
tf(RESET)
tr(RESET)
KMPDC0289EC
Parameter
Clock pulse width
Clock pulse rise/fall times
Reset pulse width 1
Reset pulse width 2
Reset pulse rise/fall times
Clock pulse-reset pulse timing 1
Clock pulse-reset pulse timing 2
Symbol
tpw(CLK)
tr(CLK), tf(CLK)
tpw(RESET1)
tpw(RESET2)
tr(RESET), tf(RESET)
t1
t2
Min.
500
0
21
20
0
-20
-20
Typ.
20
20
0
0
Max.
25000
30
30
20
20
Unit
ns
ns
CLK
CLK
ns
ns
ns
1. The internal timing circuit starts operation at the falling edge of CLK immediately after a RESET pulse goes Low.
2. When the falling edge of each CLK is counted as “1 clock”, the video signal of the 1st channel appears between “18.5 clocks and
20.5 clocks”. Subsequent video signals appear every 4 clocks.
3. The trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. The rising edge of each trigger
pulse is the recommended timing for data acquisition.
4. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the rise
of a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the RESET
pulse.
After the RESET pulse next changes from High to Low, signals integrated within this period are sequentially read out as time-series
signals by the shift register operation. The rise and fall of a RESET pulse must be synchronized with the rise of a CLK pulse, but the
rise of a RESET pulse must be set outside the video output period. One cycle of RESET pulses cannot be set shorter than the time
equal to “16.5 + 4 × N (number of elements)” clocks.
5. The video signal after an EOS signal output becomes a high impedance state, and the video output will be indefinite.
6
Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
S8866-64-02
1 2 3
4 5
20 clocks
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3
CLK
tpw(RESET1)
RESET
tpw(RESET2)
8 clocks
8 clocks
Integration time
Video output period
1
Video
2
3
n-1
n
Trig
EOS
tf(CLK)
tr(CLK)
t2
tpw(CLK)
t1
tpw(RESET1)
tpw(RESET2)
KMPDC02
tf(RESET)
tr(RESET)
KMPDC0278EC
Parameter
Clock pulse width
Clock pulse rise/fall times
Reset pulse width 1
Reset pulse width 2
Reset pulse rise/fall times
Clock pulse-reset pulse timing 1
Clock pulse-reset pulse timing 2
Symbol
tpw(CLK)
tr(CLK), tf(CLK)
tpw(RESET1)
tpw(RESET2)
tr(RESET), tf(RESET)
t1
t2
Min.
500
0
21
20
0
-20
-20
Typ.
20
20
0
0
Max.
25000
30
30
20
20
Unit
ns
ns
CLK
CLK
ns
ns
ns
1. The internal timing circuit starts operation at the falling edge of CLK immediately after a RESET pulse goes Low.
2. When the falling edge of each CLK is counted as "1 clock", the video signal of the 1st channel appears between "18.5 clocks and
20.5 clocks". Subsequent video signals appear every 4 clocks.
3. To obtain video signals, extend the High period 3 clocks from the falling edge of CLK immediately after the RESET pulse goes Low,
to a 20 clock period.
4. The trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. The rising edge of each trigger
pulse is the recommended timing for data acquisition.
5. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the rise
of a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the RESET
pulse. After the RESET pulse next changes from High to Low, signals integrated within this period are sequentially read out as timeseries signals by the shift register operation. The rise and fall of a RESET pulse must be synchronized with the rise of a CLK pulse,
but the rise of a RESET pulse must be set outside the video output period. One cycle of RESET pulses cannot be set shorter than
the time equal to "36.5 + 4 × N (number of elements)" clocks.
6. The video signal after an EOS signal output becomes a high impedance state, and the video output will be indefinite.
7
Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
Dimensional outlines (unit: mm)
S8865-64/-128
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Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
S8866-64-02/-128-02
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Pin connections
S8865-64/-128, S8866-64-02/-128-02
Pin no.
1
2
3
4
5
6
7
8
9
10
11
12
Symbol
RESET
CLK
Trig
EXTSP
Vms
Vdd
GND
EOS
Video
Vref
Vgain
Vpd
Name
Reset pulse
Clock pulse
Trigger pulse
External start pulse
Master/slave selection supply voltage
Supply voltage
Ground
End of scan
Video output
Reference voltage
Gain selection terminal voltage
Photodiode voltage
Note
Pulse input
Pulse input
Positive-going pulse output
Pulse input
Voltage input
Voltage input
Negative-going pulse output
Negative-going output with respect to Vref
Voltage input
Voltage input
Voltage input
S8865-256
Pin no.
1
2
3
4
5
6
7
8
9
10
11
12
13
CMOS1
Vpd
RESET
CLK
Trig
EXTSP
Vms
Vdd
GND
EOS
Video
Vref
Vgain
Vpd
Pin No.
14
15
16
17
18
19
20
21
22
23
24
25
26
CMOS2
Vpd
RESET
CLK
Trig
EXTSP
Vms
Vdd
GND
EOS
Video
Vref
Vgain
Vpd
Name
Photodiode voltage
Reset pulse
Clock pulse
Trigger pulse
External start pulse
Master/slave selection supply voltage
Supply voltage
Ground
End of scan
Video output
Reference voltage
Gain selection terminal voltage
Photodiode voltage
Note
Voltage input
Pulse input
Pulse input
Positive-going pulse output
Pulse input
Voltage input
Voltage input
Negative-going pulse output
Negative-going output with respect to Vref
Voltage input
Voltage input
Voltage input
9
Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
Gain selection terminal voltage setting
Vdd: High gain (Cf=0.5 pF) GND: Low gain (Cf=1 pF)
Setting for each readout method
S8865-64/-128, S8866-64-02/-128-02
Set to A in the table below in most cases.
To serially read out signals from two or more sensors linearly connected, set the 1st sensor to A and the 2nd or later sensors to B.
The CLK and RESET pulses should be shared with each sensor and the video output terminal of each sensor connected together.
Setting
Readout method
A
All stages of parallel readout, serial readout at 1st sensor
B
Serial readout at 2nd and later sensors
Vms
Vdd
GND
EXTSP
Vdd
Preceding sensor EOS should be input
[Figure 1] Connection example (parallel readout)
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Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
S8865-256
Signals of channels 1 through 126 are output from CMOS1, while signals of channels 129 through 256 are output from CMOS2. The following two readout methods are available.
(1) Serial readout method
CMOS1 and CMOS2 are connected in serial and the signals of channels 1 through 256 are sequentially read out from one output line.
Set CMOS1 as in “A” in the table below, and set CMOS2 as in “B”. CMOS1 and CMOS2 should be connected to the same CLK and RESET
lines, and their video output terminals to one line.
(2) Parallel readout method
128 channel signals are output in parallel respectively from the output lines of CMOS1 and CMOS2. Set both CMOS1 and CMOS2 as in “A”
in the table below.
[Figure 2] Connection
Serial readout method
Parallel readout method
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Setting
A
B
Vms
Vdd
GND
EXTSP
Vdd
Preceding sensor EOS should be input
Readout circuit
Check that pulse signals meet the required pulse conditions before supplying them to the input terminals.
Video output should be amplified by an operational amplifier that is connected close to the sensor.
11
Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
Precantions
(1) The signal processing IC chip is protected against static electricity. However, in order to prevent possible damage to the IC chip,
take electrostatic countermeasures such as grounding yourself, as well as workbench and tools. Also protect the IC chip from surge
voltages from peripheral equipment.
(2) Gold wires for wire bonding are very thin, so they easily break if subjected to mechanical stress. The signal processing IC chip and
wire bonding section are covered with resin for protection. However, never touch these portions. Excessive force, if applied, may
break the wires or cause malfunction.
Blow air to remove dust or debris if it gets on the protective resin. Never wash them with solvent.
Signals may not be obtained if dust or debris is left or a scratch is made on the protective resin, or the signal processing IC chip or
photodiode array chip is nicked.
(3) The photodiode array characteristics may deteriorate when operated at high humidity, so put it in a hermetically sealed enclosure or case.
When installing the photodiode array on a board, be careful not to cause the board to warp.
Driver circuit C9118 series (sold separately)
The CMOS driver circuit is designed for S8865-64/-128 and S8866-128-02 photodiode arrays with amplifier.
The C9118 series operates a photodiode by just inputting two signals (M-CLK and M-RESET) and a signal +5 V supply.
The C9118 is intended for single use or parallel connections, while the C9118-01 is suitable for cascade connections.
Features
Single power supply (+5 V) operation
Operation with two input signals (M-CLK and M-RESET)
Compact: 46 × 56 × 5.2 t mm
Block diagram
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12
Photodiode arrays with amplifier
S8865-64/-128/-256, S8866-64-02/-128-02
Connection examples
Single or parallel readout example (C9118)
Cascade readout example (C9118-01)
Simultaneous integration/output
(effective for high-speed processing)
Simultaneous integration/serial output
(Simplifies external processing circuit)
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Information described in this material is current as of February, 2014.
Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the
information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always
contact us for the delivery specification sheet to check the latest specifications.
Type numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(X)" which means preliminary specifications or
a suffix "(Z)" which means developmental specifications.
The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that
one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product
use.
Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission.
www.hamamatsu.com
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
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Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1 int. 6, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
China: Hamamatsu Photonics (China) Co., Ltd.: 1201 Tower B, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 100020, China, Telephone: (86) 10-6586-6006, Fax: (86) 10-6586-2866
Cat. No. KMPD1071E08 Feb. 2014 DN
13