For Video Equipment MN6761S External Synchronization Control LSI for Color Video Cameras Overview The MN6761S is an external synchronization control LSI for color video cameras. When used in combination with a synchronizing signal generator (MN67601NS or MN67602PS), it provides external synchronization control for NTSC and PAL video systems. Features Synchronization of both the video camera and the VCR External synchronization inputs: Composite synchronizing signal and burst subcarrier External synchronization techniques • Horizontal synchronization: phase-locked loop • Vertical synchronization: reset technique Pin Assignment SCPSW1 1 28 4fSC SCPSW2 2 27 4fSCOSCO WHD 3 26 4fSCOSCI N/P 4 25 SOPCO SC1 BGP 5 24 GLBSC 6 23 VDD1 VSS2 7 22 VSS1 VDD2 8 21 TEST1 GLSYNC 9 20 HBLK TEST2 10 19 EXT/INT fHP 11 18 LSWCONT HPCO 12 17 LSW XfHOSCI 13 16 VR XfHOSCO 14 15 XfH • Subcarrier synchronization: phase-locked loop Support for both NTSC and PAL systems Built-in feature for automatically switching between external and internal synchronization Built-in horizontal phase adjustment circuit Applications Color video cameras (TOP VIEW) SOP028-P-0375 TEST1 TEST2 SCPSW2 SCPSW1 SC1 21 10 2 1 Selector Shift register CK 90˚ 0˚ Line switch HBLK and BGP pulse generator 3 24 D 16 Monostable multivibrator 11 4 VR Gate Phase comparator Phase comparator Line switch control pulse generator Internal/external synchronization switch 12 N/P WHD 4fSC generator XfH oscillator 13 fH H separation fHP 14 GLSYNC HPCO fV XfH OSCO XfH OSCI V separation XfH 9 22 23 18 20 19 7 8 VSS1 VDD1 LSWCONT HBLK EXT/INT VSS2 VDD2 MN6761S For Video Equipment Block Diagram 15 28 27 26 25 6 5 17 4fSC 4fSC OSCO 4fSC OSCI SCPCO GLBSC BGP LSW For Video Equipment MN6761S Pin Descriptions Pin No. 23 Symbol VDD1 Pin Name Power supply Function Description "H" level (5V) power supply for subcarrier circuits 22 VSS1 Power supply "L" level (GND) power supply for subcarrier circuits 8 VDD2 Power supply "H" level (5V) power supply for synchronizing signal 7 VSS2 Power supply "L" level (GND) power supply for synchronizing signal 9 GLSYNC 6 CLBSC 3 WHD 11 fHP 24 SC1 1 SCPSW1 Subcarrier phase Pin selecting which of the four phase signals generated from 2 SCPSW2 switch inputs the SC1 signal goes to the phase comparator 17 LSW Line switch input For a PAL system, supply the LSW signal from the circuits circuits External synchronizing Input pin for composite synchronizing signal derived from signal input video signal (reference for horizontal and vertical signals) External burst Input pin for burst subcarrier signal derived from video subcarrier input signal (reference for subcarrier signals) Horizontal synchroni- Input pin for WHD signal from synchronizing signal zation input generator Monostable multi- Pin for connecting CR circuit for adjusting delay for analog vibrator input monostable multivibrator (thus adjusting horizontal phase) Subcarrier input Input pin for SC1 signal from synchronizing signal generator synchronizing signal generator. For an NTSC system, keep this pin at "H" level. 4 12 N/P HPCO NTSC/PAL selection "H" level selects NTSC operation; input "L" level, PAL operation. Horizontal phase This pin is at "L" level when the WHD signal, after passing comparator output through the monostable multivibrator, leads the rising edge of the HSYNC signal derived by separating off the horizontal component of the GLSYNC signal and is at "H" level when the signal lags. At all other times, it is in the high-impedance state. 13 14 XfHOSCI XfHOSCO Oscillator input for Clock oscillator pins for the synchronization circuits. the synchronization Connect these pins to an inductor, capacitor, and variable circuits capacitor. (The pins have built-in feedback resistors.) Oscillator output for The circuit oscillates during external synchronization mode. the synchronization The oscillation stops for internal synchronization mode. circuits The oscillator frequency, XfH is 14.31818 MHz (910fH) for Clock output for Clock output pin for synchronizing signal circuits. synchronizing signal This pin provides the clock (XfH) for the external circuits synchronization mode and stays at "L" level for the internal NTSC and 4.406 MHz (282fH) for PAL. 15 XfH synchronization mode. Connect to the EX910fHI pin of the synchronizing signal generator for NTSC operation and to the EX282fHI pin for PAL operation. MN6761S For Video Equipment Pin Descriptions (continued) Pin No. 16 Symbol VR Pin Name Vertical reset output Function Description This pin generates a vertical reset pulse for the V-SERATION interval detected in the GLSYNC signal. Connect it to the VR pin of the synchronizing signal generator. 25 SCPCO Subcarrier phase This pin is at "L" level when the SC1 signal leads the comparator output GLBSC signal and is at "H" level when the signal lags. At all other times, it is in the high-impedance state. 26 4f SCOSCI Oscillator input for Clock oscillator pins for the subcarrier circuits. subcarrier circuits Connect these pins to a crystal oscillator, capacitor, and variable capacitor. (The pins have built-in feedback resistors.) 27 4fSCOSCO Oscillator output for The circuit oscillates during external synchronization mode. subcarrier circuits The oscillation stops for internal synchronization mode. The oscillator frequency, 4fSC , is 14.31818 MHz for NTSC and 14.734 MHz for PAL. 28 4fSC Subcarrier clock output Clock output from subcarrier circuits. In external synchronization mode, this pin provides the (4f SC) clock signal; in internal synchronization mode, it remains at "L" level. Connect this pin to the EX4fSCI pin on the synchronizing signal generator. 18 LSWCONT Line switch polarity During PAL operation, this pin emits an error detection control output pulse if the LSW polarity is wrong, and the chip reverses the LSW polarity. During internal synchronization mode, this pin remains at "L" level. Connect this pin to the LSWCONT pin on the synchronizing signal generator. 19 EXT/INT Automatic internal/ If the chip detects GLSYNC input, it switches to external external switching synchronization mode and drives this pin at "H" level. output Otherwise, it switches to internal synchronization mode and drives this pin at "L" level. Connect this pin to the EXT/INT pin on the synchronizing signal generator. 5 BGP Burst gate pulse output These pulses have a width of 2.5 µs (NTSC) or 2.3 µs (PAL) and trail the rising edge of the HSYNC signal by 5.3 µs (NTSC) or 5.6 µs. They are generated for only 10 H to 256 H (NTSC) or 304 H (PAL) after the VR pulse. 20 HBLK 21 TEST1 10 TEST2 Horizontal blanking These pulses have a width of 8.9 µs (NTSC) or 8.8 µs output (PAL) and follow the rising edge of the HSYNC signal. Test inputs Leave these test inputs open. (The pins include built-in pull-up resistors.) For Video Equipment MN6761S Timing Chart 1. Horizontal synchronization block This block compares the phases of the HSYNC signal derived by separating off the horizontal component of the GLSYNC input and the WHD signal from the synchronizing signal generator after it has passed through the monostable multivibrator. It is thus possible to adjust the horizontal phase by adjusting the CR integral circuit's time constant. GLSYNC HSYNC WHD DELAY WHD Timing chart for horizontal pulse phase comparison 2. Vertical synchronization block This block detects the V-SERATION interval in the GLSYNC input and generates a vertical reset (VR) pulse with 0.5 H of the start of that interval. It then issues no pulses for 256 H (NTSC) or 304 H (PAL) after this VR pulse. GLSYNC VR 2.2µs (NTSC) 1.8µs (PAL) 14.0µs (NTSC) 11.2µs (PAL) Vertical reset pulse timing chart MN6761S For Video Equipment 3. Subcarrier synchronization block This block converts the SC1 output from the synchronizing signal generator into four signals with the same frequency as the burst subcarrier, but different phases. In this phase-locked loop circuit, the phase of GLBSC is compared with the phase selected by 2 bits (SCPSW1 and SCPSW2). During PAL operation, if the LSW polarity is wrong, this block sends an error detection pulse (LSWCONT) to the synchronizing signal generator and reverses the LSW polarity. It also adjusts the relationship between fields 1 through 4. 4. Oscillator blocks The Xf H and 4fSC oscillator blocks operate only during external synchronization mode. Connecting a variable capacitor creates voltage-controlled oscillators that generate the synchronization signal circuit clock (XfH) and subcarrier circuit clock (4f SC) for output to the synchronization signal generator. 5. Automatic internal/external switching block If it detects a minimum of ten edges from the GLSYNC input, this block switches the chip to the external synchronization mode and drives the EXT/INT pin at "H" level. If there are no edges in the GLSYNC input for 10 H, this block switches the chip to the internal synchronization mode and drives this pin at "L" level. HBLK and BGP plus generator GLSYNC HBLK BGP 5.3µs (NTSC) 5.6µs (PAL) 2.5µs (NTSC) 2.3µs (PAL) 8.9µs (NTSC) 8.8µs (PAL) HBLK and BGP pulse timing chart There is an HBLK pulse for each H. BGP pulses are generated for only 10 H to 256 H (NTSC) or 304 H (PAL) after the VR pulse. VBS Burst Sep. Sync Sep. 100kΩ + 100kΩ 100kΩ 100kΩ 22Ω 1kΩ 100kΩ 3kΩ 2.2µH 10kΩ 50kΩ 1kΩ 100kΩ 100pF 220kΩ 10000pF 330pF 100kΩ 3kΩ 1000pF 43kΩ + 2.2µF 2SK198 D4 20pF X2 1kΩ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD2 VSS2 SYNC VP WHD BLK CP1V CP2 WBLK BF SW1 SW2 SW3 SW4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14.31818MHz X1,2 D1 to 4 1SV153 MN67601NS VDD1 VSS1 EX4fSCI 4fSCOSCI 4fSCOSCO SC1 SC2 BSC VPCO EXT/INT CP1 TEST VR EX910fHI 10000pF 2SK128 330pF D3 X1 330pF D2 D1 100kΩ 18pF 10kΩ 10kΩ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10000pF MN6761S SCPSW1 4fSC SCPSW2 4fSCOSCO WHD 4fSCOSCI N/P SCPCO BGP SC1 VDD1 GLBSC VSS2 VSS1 VDD2 TEST1 HBLK GLSYNC TEST2 EXT/INT LSWCONT fHP LSW HPCO XfHOSCI VR XfHOSCO XfH 2.2µH 1kΩ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 5V SC1 SYNC VP WHD BLK CP1V CP2 WBLK BF For Video Equipment MN6761S Application Circuit Example 1. External synchronization for NTSC system 2.2µH 10µF + 10µF + 1kΩ 180pF 10pF 10µF 39000pF 2.2µH 10000pF 10000pF + 47pF 10µF 330pF VBS Burst Sep. Sync Sep. 1kΩ + 100kΩ 100kΩ 100kΩ 12pF 20pF 10µF + 2.2µH 10kΩ 50kΩ 10000pF 330pF 330pF 100kΩ 100kΩ 100kΩ D2 D1 100kΩ 100kΩ Q2 330pF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D1 to 5 1SV153 Q1 to 3 2SK198 17.734MHz X1,2 MN67602PS VDD1 VDD2 VSS1 VSS2 SYNC EX4fSCI VP 4fSCOSCI WHD 4fSCOSCO BLK SC1 SC2 CP1V BSC CP2 WBLK VPCO BF EXT/INT LSWCONT SCBLK HPCO LSW VR 282fHOSCI EX282fHI 282fHOSCO D5 SC2 SC1 10kΩ 1000pF 1kΩ Q3 1kΩ SYNC VP WHD BLK CP1V CP2 WBLK BF 7.5kΩ 10kΩ 2.2µH 18pF 22Ω 1kΩ 330pF D4 X2 10000pF D3 X1 2.2µH MN6761S 28 27 26 25 24 23 22 21 20 19 18 17 16 15 2.2µH 10kΩ Q1 SCPSW1 4fSC SCPSW2 4fSCOSCO WHD 4fSCOSCI N/P SCPCO BGP SC1 VDD1 GLBSC VSS2 VSS1 VDD2 TEST1 HBLK GLSYNC TEST2 EXT/INT LSWCONT fHP LSW HPCO XfHOSCI VR XfHOSCO XfH 10µF + 1kΩ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 5V MN6761S For Video Equipment Application Circuit Example 2. External synchronization for PAL system 1200pF 2.2µF 3kΩ 15pF 330pF 10000pF 1kΩ 1kΩ 180pF 180pF 10pF 3kΩ 100pF 10µF 220kΩ 10000pF 10000pF + 47pF 10µF 1kΩ 1000pF 3kΩ 43kΩ+ 2.2µF 39000pF For Video Equipment MN6761S Package Dimensions (Unit: mm) SOP028-P-0375 17.80±0.20 15 (0.65) 1.27 0.40±0.10 SEATING PLANE +0.10 9.40±0.30 2.40max. 0.15 -0.05 7.20±0.20 14 0.10±0.10 1 1.10±0.20 2.00±0.20 28 0 to 10° 0.30min.