DATA SHEET Part No. AN15865A Package Code No. *QFH080-P-1420H SEMICONDUCTOR COMPANY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. Publication date: March 2004 SDB00102AEB 1 AN15865A Contents Overview ……………………………………………………………………………………………………………. 3 Features …………………………………………………………………………………………………………….. 3 Applications ………………………………………………………………………………………………………… 3 Package ……………………………………………………………………………………………………………. 3 Type …………………………………...……………………………………………………………………………. 3 Application Circuit Example ………………………………………………………………………………………. 4 Block Diagram ………………...……………………………………………………………………………………. 5 Pin Descriptions ……………………………………………………………………………………………………. 7 Absolute Maximum Ratings ………………………………………………………………………………………. 10 Operating Supply Voltage Range ……………..…………………………………………………………………. 10 Electrical Characteristics …………………………………………………………………………………………. 11 I2C Bus Conditions ………………………………………………………………………………………………. 15 Test Circuit Diagram ………………………………………………………………………………………………. 26 Technical Data ……………………………………………………………………………………………………. 27 1. Circuit diagrams of the input/output part and pin function descriptions ……………………………………. 27 2. Notes on video gain………………………………………………………………………………………………. 35 3. Other supplementary matters…………………………………….……………………………………………… 35 Usage Notes ……………………………………….………………………………………………………………. 36 SDB00102AEB 2 AN15865A AN15865A The video switch IC including the synchronous separation function for TV Overview The AN15865A has the video switch portion which consists of a five-channel output in a ten-channel input, the synchronous separation function, the AFC function, and the format detection function. It contributes to the rationalization design of a television system. Features 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Support multi scan / Auto format identification 480i, 576i, 480P, 576P, 720P, 1080i, 1152i, 1152i/letter (both 50 Hz & 60 Hz) Field 1 or 2 monitor out is available Auto distinction in the selected input (Sync on CV/Y or Sync on SY or no input signal) Dummy sync output 480i, 576i, 480P, 576P, 720P, 1080i (both 50 Hz & 60 Hz) Sync separation with AFC w/o external x-tal or clock 2 values, 3 values sync identification RGB → YUV converter (CCIR standard, BTA standard, GBR matrix) Each output can be switched between LPF (6 MHz) & through Each output can be switched among 0 dB, 6 dB or mute Macrovision Comparators for Pin detection ×4 (Connected / Open) Comparators for Aspect ratio ×4 (4:3 video / 4:3 letter box / 16:9 video) High frequency (0 dB at 50 MHz) Support the I2C BUS Various input mode can be selected by using flexible internal switch INPUT OUTPUT IN1 CV1 OUT1 CV1-7/SY4-7/ SC4-7 IN2 CV2 OUT2 CV1-7(SY4-7)/ SC4-7 IN3 CV3 OUT3 CV1-7(SY4-7)/ SC4-7 IN4 CV4/SY4/SC4 Y7/U7/V7 IN5 CV5/SY5/SC5 Y6/U6/V6 H6/V6 IN6 CV6/SY6/SC6 Y5/U5/V5 H5/V5 IN7 CV7/SY7/SC7 Y4/U4/V4 H4/V4 IN8 Y3(G3)/U3(B3)/V3(R3) H3/V3 IN9 Y2(G2)/U2(B2)/V2(R2) H2/V2 IN10 Y1(G1)/U1(B1)/V1(R1) H1/V1 OUT4 G(Y1-6)(CV1-7)/B(U1-6)(SY4-7)/ R(V1-6)(SC4-7) H1/V1 *1 OUT5 G(Y1-6)(CV1-7)/B(U1-6)(SY4-7)/ R(V1-6)(SC4-7) H2/V2 *2 Note) *1: Independent HV only *2: Independent HV or Sync-separated HV Applications y IC for Color TV Package y 80 Pin Plastic High Profile Quad Flat Package (QFP Type) Type y Silicon Monolithic BICMOS IC SDB00102AEB 3 AN15865A Application Circuit Example 41 Vin6 42 V6/SC5 43 Hin6 44 U6/SY5 45 SB5 46 Y6/CV5 Input 5 47 SA5 48 CV1 Input 1 49 GND1 50 CV2 Input 2 51 SA3 52 CV3 53 SB3 54 Y7/CV4 55 SA4 56 U7/SY4 57 SB4 58 V7/SC4 59 SA6 60 Y5/CV6 61 SB6 62 U5/SY6 63 Hin5 64 V5/SC6 Input 6 Input 3 Input 4 Input 6 Vin5 65 40 CV1 Y4/CV7 66 39 VCC2 Hin4 67 38 SY1 U4/SY7 68 Input 7 0.47 µF 35 SLVADR 34 CV2/SY2 71 G3/Y3 72 33 GND 31 GND2 B3/U3 74 5V Output 2 32 SC2 Hin3 73 Input 8 10 kΩ 36 SC1 V4/SC7 70 VCC1 Output 1 37 DCOUT Vin4 69 9V 9V Vin3 75 30 CV3/SY3 R3/V3 76 29 GND VCC4 77 28 SC3 G2/Y2 78 27 VCC3 Hin2 79 26 G1/Y1 B2/U2 80 25 Hout1 Output 3 5V Input 9 3.3 V Input 10 SDB00102AEB Output 5 B1/U1 24 Vout1 23 R1/V1 22 GND3 21 G2/Y2 20 Hout2 19 B2/U2 18 Vout2 17 R2/V2 16 Vsyncsepa 14 0.022 µF Field monitor 15 Sync-in 13 75 kΩ GND4 11 Sync-out 12 0.01 µF 4.7 µF AFC1 10 4.7 kΩ R1/V1 9 Vin1 8 B1/U1 7 Hin1 6 G1/Y1 5 SCL 4 SDA 3 R2/V2 2 Vin2 1 Input 9 Output 4 Note : VCC1, VCC2 = 9 V ± 0.5 V VCC3, VCC4 = 5 V ± 0.3 V SLVADR : 5 V( 8Chex / 8Dhex ) 0 V( 84hex / 85hex ) 4 AN15865A Block Diagram (SYNC separation and AFC system) Vin1 Vin2 V Switch 1 Automatic Polarity control V1 ( independent V ) Vout1 H Switch 1 Automatic Polarity control H1 ( independent H ) Hout1 ( AFC-V or independent V ) Vout2 ( AFC-H H or independent H ) Switch 2 Hout2 Vin6 Hin1 Hin2 Hin6 independent V (selected) Automatic Polarity control V2 V Switch 2 Auto sync distinction independent H (selected) CV1 CV2 CV3 Y7/CV4 SY4 Y6/CV5 SY5 Y5/CV6 SY6 Y4/CV7 SY7 Y3 Y2 Y1 V Counter Automatic Polarity control H2 V Sync Separation H Sync Separation Switch clamp V mask pulse H Counter Sync status Detector ( 2 or 3 ) MACRO VISION LOCK det Phase detector HVCO System mode control System status check Sync-out SDB00102AEB Sync-in V sync sepa AFC filter Field monitor 5 AN15865A Block Diagram (continued) Y7/CV4 U7/SY4 V7/SC4 CV1 CV2 CV3 in4 in1 in2 in3 in5 Y5/CV6 U5/SY6 V5/SC6 Hin5 Vin5 Y6/CV5 U6/SY5 V6/SC5 Hin6 Vin6 in6 in7 Y4/CV7 U4/SY7 V4/SC7 Hin4 Vin4 G3/Y3 B3/U3 R3/V3 Hin3 Vin3 G2/Y2 B2/U2 R2/V2 Hin2 Vin2 G1/Y1 B1/U1 R1/V1 Hin1 Vin1 SA6 SA3 SA4 SA5 SB3 SB4 SB5 SB6 Hout1 Switch Through Vout1 Vout2 Switch Hout2 Sync-Sep AFC Vref 6/0 dB 6/0 dB 6/0 dB 6/0 dB 6/0 dB 6/0 dB 6/0 dB 6/0 dB 6/0 dB CCIR Matrix 2 BTA Matrix 3 GBR CCIR Matrix 2 BTA Matrix 3 GBR + + + Sync-Sep Sync-Sep 6/0 dB 6/0 dB 6/0 dB 6/0 dB 6/0 dB 6/0 dB LPF LPF LPF CV1 SY1 SC1 SC2 CV2/SY2 LPF LPF out1 out2 out3 R1/V1 B1/U1 G1/Y1 SC3 CV3/SY3 LPF LPF LPF LPF LPF G2/Y2 LPF B2/U2 LPF R2/V2 LPF out4 out5 6 SDB00102AEB in8 in9 in10 (Video-Switch) AN15865A Pin Descriptions Pin No. Pin name Type Description 1 Vin2 In Independent V signal input 2 2 R2/V2 In R2/V2 signal input 3 SDA In / Out I2C bus data input 4 SCL In I2C bus clock input 5 G1/Y1 In G1/Y1 signal input 6 Hin1 In Independent H signal input 1 7 B1/U1 In B1/U1 signal input 8 Vin1 In Independent V signal input 1 9 R1/V1 In R1/V1 signal input 10 AFC1 In / Out AFC filter 11 GND4 Ground Ground 12 Sync-out Out Sync signal output for sync separation 13 Sync-in In Sync signal input for sync separation 14 V sync sepa 15 Field monitor Out Field change signal output 16 R2/V2 Out R2/V2 signal output 17 Vout2 Out Independent V signal output 2 18 B2/U2 Out B2/U2 signal output 19 Hout2 Out Independent H signal output 2 20 G2/Y2 Out G2/Y2 signal output 21 GND3 Ground 22 R1/V1 Out R1/V1 signal output 23 Vout1 Out Independent V signal output 1 24 B1/U1 Out B1/U1 signal output 25 Hout1 Out Independent H signal output 1 26 G1/Y1 Out G1/Y1 signal output 27 VCC3 28 SC3 Out 29 GND Ground 30 CV3/SY3 31 GND2 32 SC2 Out 33 GND Ground 34 CV2/SY2 Out 35 SLVADR In In / Out V sync separation filter Ground Power supply 5.0 V power supply Out Ground SC3 signal output Ground CV3/SY3 signal output Ground SC2 signal output Ground CV2/SY2 signal output Sets the I2C bus slave address SDB00102AEB 7 AN15865A Pin Descriptions (continued) Pin No. Pin name Type Description 36 SC1 Out SC1 signal output 37 DCOUT Out Output DC voltage corresponding to S2 38 SY1 Out SY1 signal output 39 VCC2 40 CV1 Out 41 Vin6 In Independent V signal input 6 42 V6/SC5 In V6/SC5 signal input 43 Hin6 In Independent H signal input 6 44 U6/SY5 In U6/SY5 signal input 45 SB5 In Pin status detection for input channel 5 46 Y6/CV5 In Y6/CV5 signal input 47 SA5 In Aspect ratio detection for input channel 5 48 CV1 In CV1 signal input 49 GND1 50 CV2 In CV2 signal input 51 SA3 In Aspect ratio detection for input channel 3 52 CV3 In CV3 signal input 53 SB3 In Pin status detection for input channel 3 54 Y7/CV4 In CV4 signal input 55 SA4 In Aspect ratio detection for input channel 4 56 U7/SY4 In SY4 signal input 57 SB4 In Pin status detection for input channel 4 58 V7/SC4 In SC4 signal input 59 SA6 In Aspect ratio detection for input channel 6 60 Y5/CV6 In Y5/CV6 signal input 61 SB6 In Pin status detection for input channel 6 62 U5/SY6 In U5/SY6 signal input 63 Hin5 In Independent H signal input 5 64 V5/SC6 In V5/SC6 signal input 65 Vin5 In Independent V signal input 5 66 Y4/CV7 In Y4/CV7 signal input 67 Hin4 In Independent H signal input 4 68 U4/SY7 In U4/SY7 signal input 69 Vin4 In Independent V signal input 4 70 V4/SC7 In V4/SC7 signal input Power supply 9.0 V power supply Ground CV1 signal output Ground SDB00102AEB 8 AN15865A Pin Descriptions (continued) Pin No. Pin name Type Description 71 VCC1 Power supply 9.0 V power supply 72 G3/Y3 In G3/Y3 signal input 73 Hin3 In Independent H signal input 3 74 B3/U3 In B3/U3 signal input 75 Vin3 In Independent V signal input 3 76 R3/V3 In R3/V3 signal input 77 VCC4 78 G2/Y2 In G2/Y2 signal input 79 Hin2 In Independent H signal input 2 80 B2/U2 In B2/U2 signal input Power supply 5.0 V power supply SDB00102AEB 9 AN15865A Absolute Maximum Ratings A No. 1 2 Parameter Supply voltage Supply current Symbol Rating VCC1, VCC2 10.0 VCC3, VCC4 5.5 ICC1, ICC2 130 ICC3, ICC4 23 Unit Note V *1 mA 3 Power dissipation PD 773 mW *2 4 Operating ambient temperature Topr −20 to +75 °C *3 5 Storage temperature Tstg −55 to +125 °C *3 Unit Note Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at Ta = 75°C for the independent IC package without a heat sink. Refer to the package power dissipation prepared else and use under the condition not exceeding the allowable value. *3: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. Operating supply voltage range Parameter Operating supply voltage range Symbol Range VCC1, VCC2 8.5 to 9.5 VCC3, VCC4 4.7 to 5.3 V * Note) *: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. SDB00102AEB 10 AN15865A Electrical Characteristics at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Limits Test circuits Conditions Unit Min Typ Max 1 Quiescent Current ICQ12 1 No signal input VCC1, VCC2 109 118 127 mA 2 Quiescent Current ICQ34 1 No signal input VCC3, VCC4 10 15 20 mA – 0.2 0.3 dB GV6 1 f = 500 kHz, VIN = 1 V[p-p] (except composite pass) – 0.7 Video Gain GV0 1 3 5.2 5.7 6.2 dB 4 Video Frequency Response 1 fV1 1 1.0 V[p-p] input at 30 MHz/500 kHz (during 6 dB output)(LPF OFF) –1.5 — 1.0 dB 5 Video Frequency Response 2 fV2 1 1.0 V[p-p] input at 30 MHz/500 kHz (during 0 dB output) (composite in) –1.5 — 1.0 dB 6 Crosstalk CTV 1 1.0 V[p-p] input at 5 MHz Between contiguity channels — — –50 dB 7 Output DC level dVDO 1 Measure the difference from the Output DC level while in mute mode. – 0.4 — 0.4 V 8 LPF characteristic1 fLPF1 1 1.0 V[p-p] input at 6 MHz/500 kHz (LPF ON) –6 –3 0 dB 9 LPF characteristic2 fLPF2 1 1.0 V[p-p] input at 10 MHz/500 kHz (LPF ON) — — –25 dB Note [Hout items] 10 Hout1/2 high level HHI 1 2.8 3.3 — V 11 Hout1/2 low level HLO 1 — — 0.5 V 12 Hout2 pulse width(1) HWID1 1 mode 480i, 576i 1.2 1.6 2.0 µs 13 Hout2 pulse width(2) HWID2 1 mode 480p, 576p 0.6 1.0 1.4 µs 14 Hout2 pulse width(3) HWID3 1 mode 1080i, 720p, 1152i, 1152i /letter 520 660 800 ns 15 H pull in range upper fHPULLUP 1 700 — — Hz 16 H pull in range lower fHPULLLOW 1 — — – 700 Hz 17 Hout2 free-run Freq.1 fHFREE1 1 mode 576i 15.53 15.62 15.72 kHz 18 Hout2 free-run Freq.2 fHFREE2 1 mode 576p, 1152i, 1152i/letter 31.06 31.25 31.43 kHz 19 Hout2 free-run Freq.3 fHFREE3 1 mode 1080i/50 28.00 28.17 28.34 kHz 20 Hout2 free-run Freq.4 fHFREE4 1 mode 720p/50 37.28 37.50 37.72 kHz 21 Hout2 free-run Freq.5 fHFREE5 1 mode 480i 15.65 15.75 15.84 kHz SDB00102AEB 11 AN15865A Electrical Characteristics (continued) at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Test circuits Limits Conditions Unit Min Typ Max 22 Hout2 free-run Freq.6 fHFREE6 1 mode 480p 31.23 31.41 31.60 kHz 23 Hout2 free-run Freq.7 fHFREE7 1 mode 1 080i/60 33.51 33.71 33.90 kHz 24 Hout2 free-run Freq.8 fHFREE8 1 mode 720p/60 44.84 45.11 45.38 kHz Note [Vout items] 25 Vout1/2 high level VHI 1 2.8 3.3 — V 26 Vout1/2 low level VLO 1 — — 0.5 V 27 Vout2 pulse width(1) VWID1 1 AFC/free mode 480i, 480p, 1080i/60 — 6 — H 28 Vout2 pulse width(2) VWID2 1 AFC/free mode 576p, 1080i/50 — 6 — H 29 Vout2 pulse width(3) VWID3 1 AFC/free mode 1152i/letter — 6 — H 30 Vout2 pulse width(4) VWID4 1 AFC/free mode 720p/60 — 5 — H 31 Vout2 pulse width(5) VWID5 1 AFC/free mode 576i, 720p/50 — 5 — H 32 Vout2 pulse width(6) VWID6 1 AFC/free mode 1152i — 6 — H [Address Pins] 33 Address setting voltage (84/85hex) VADR1 1 — — 1.5 V 34 Address setting voltage (8C/8Dhex) VADR2 1 2.5 — — V [DCOUT] 35 S2 compatible DC level L [00] VDCL 1 — — 0.5 V 36 S2 compatible DC level M [01] VDCM 1 1.4 — 2.8 V 37 S2 compatible DC level H [11] VDCH 1 4.0 — — V SDB00102AEB 12 AN15865A Electrical Characteristics (continued) at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Limits Test circuits Unit Conditions Min Typ Max The pin voltage with Pin 3 suction current set to 3 mA during Ack. — — 0.4 V Note [I2C Interface] 38 Suction current during ACK VACK 1 39 SCL, SDA signal input high level VIHI 1 3.0 — 5.5 V 40 SCL, SDA signal input low level VILO 1 0 — 1.5 V 41 Max. frequency allowable to input fimax 1 100 — — Kbit/s START CONDITION SLAVE ADDRESS SUB ADDRESS ACK ACK DATA BYTE ACK STOP CONDITION SDA tBUF tLO tSU.DAT tHD.DAT tSU.STO SCL tSU.STA tHD.STA tR tF tHI tLO Note) The above characteristics are reference values on IC designing and not guaranteed by shipping inspection. SDB00102AEB 13 AN15865A Electrical Characteristics (Reference values for design) at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Test circuits Reference values Conditions Min Typ Max Unit Note V[p-p] *1 VDYV 1 2.4 — — VM 1 — 3.5 — Output pedestal level VPED 1 1.0 V[p-p] input 0 dB mode — 3.5 — V *1 Output sync level VSYNC 1 1.0 V[p-p] input 0 dB mode — 3.2 — V *1 BH 1 Conversion by 6 MHz — –1.4 — kHz/ mV *1 42 Input Dynamic Range 43 Mute DC level 44 45 V *1 [Hout items] 46 H VCO osc. Chara. [Vout items] 47 Vout2 free-run Freq.1 fVFREE1 1 mode (V : 50 Hz) — 50 — Hz *1 48 Vout2 free-run Freq.2 fVFREE2 1 mode (V : 60 Hz) — 60 — Hz *1 [SA SB Pins] 49 Scart ident SA L VSAL 1 — — 1.0 V *1 50 Scart ident SA M VSAM 1 1.7 — 3.0 V *1 51 Scart ident SA H VSAH 1 4.0 — — V *1 52 Pin detect SB L VSBL 1 — — 1.5 V *1 53 Pin detect SB H VSBH 1 2.5 — — V *1 [Others] 54 Hin L HSL 1 — — 1.5 V *1 55 Hin H HSH 1 2.5 — — V *1 56 Vin L VSL 1 — — 1.5 V *1 57 Vin H VSH 1 2.5 — — V *1 Note) *1 : The characteristics listed above are logical values derived from the design, and as such, all of these cannot be guaranteed. If, in the unlikely case that problems do occur related to these parameters, Panasonic will negotiate in good faith with the customer on these matters. SDB00102AEB 14 AN15865A I2C Bus Conditions y The AN15865A in I2C bus control performs switch mode selection, matrix selection, gain selection, LPF selection, synchronous mode selection and freerun mode selection through a control register and detects the system status, aspect and pin information through a status register. The upper seven address bits are allocated to the slave address while the LSB is allocated to the R/W bit. The R/W bit corresponds to the control register with with the bit set to 0 and corresponds to the status register with the bit set to 1. Sub Address D7 D6 D5 D4 D3 D2 D1 D0 84/8C 85/8D 1 0 0 0 1/0 1 0 R/W Note) The change of D3 data is performed by control of a SLVADR terminal Control Register y The AN15865A selects slave address 84 or 8C(hex) according to the status of the SLVADR pin. Address 84(hex) will be selected with the SLVADR pin grounded the the GND side. Address 8C(hex) will be selected with the pin grounded to the 5-V line. Slave Address (84 or 8C) S AS Sub Address (X) AS DATA (X) DATA (X + 1) AS AS DATA (X + 2) continue Note) AS = ACK from Slave R/W = 0 Sub Address D7 D6 D5 D4 D3 D2 D1 00 OUT1signal select OUT2 signal select 01 OUT3 signal select OUT4 signal select D0 02 OUT5 sync distinction 00 : auto distinction 01 : sync on CV/Y use 10 : sync on SY use 11 : free-run free-run priority 0 : fixing 1 : auto distinction use OUT5 sync 0 : AFC 1 : independent 03 OUT4 matrix 00 : through 01 : CCIR standard 10 : BTA standard 11 : GBR matrix OUT5 matrix 00 : through 01 : CCIR standard 10 : BTA standard 11 : GBR matrix Dummy sync mode Control (When 02/D7, D6 = '11') 000 : 480i / 60 001 : 480p / 60 010 : 1 080i / 60 011 : 720p / 60 100 : 576i / 50 101 : 576p / 50 110 : 1 080i / 50 111 : 720p / 50 HVout2 polarity 0 : positive 1 : negative 04 CV1 GAIN 0 : 0 dB 1 : 6 dB SY1/SC1 GAIN 0 : 0 dB 1 : 6 dB CV2 GAIN 0 : 0 dB 1 : 6 dB SY2/SC2 GAIN 0 : 0 dB 1 : 6 dB CV3 GAIN 0 : 0 dB 1 : 6 dB SY3/SC3 GAIN 0 : 0 dB 1 : 6 dB OUT4 GAIN 0 : 0 dB 1 : 6 dB OUT5 GAIN 0 : 0 dB 1 : 6 dB 05 OUT1 LPF 0 : through 1 : LPF ON OUT2 LPF 0 : through 1 : LPF ON OUT3 LPF 0 : through 1 : LPF ON OUT4 LPF 0 : through 1 : LPF ON OUT5 LPF 0 : through 1 : LPF ON OUT1 DCOUT 00 : 0 V 01 : 1.9 V 10 : indefinite 11 : 4.5 V Field monitor sel 0 : F1 / F2 out 1 : clock moni out 06 input4 U/SY sel 0 : SY select 1 : U select input5 U/SY sel 0 : SY select 1 : U select input6 U/SY sel 0 : SY select 1 : U select input7 U/SY sel 0 : SY select 1 : U select input8 BR/UV sel 0 : BR select 1 : UV select input9 BR/UV sel 0 : BR select 1 : UV select input10 BR/UV sel 0 : BR select 1 : UV select Australia free-run 0 : except Australia 1 : Australia mode 07 test77 test76 test75 test74 test73 test72 test71 test70 08 test87 test86 test85 test84 test83 test82 test81 test80 OUT5 signal select Note) Please send data "00" to sub-address "07" and "08". SDB00102AEB 15 AN15865A I2C Bus Conditions (continued) OUT1 signal select 00/D7 00/D6 00/D5 00/D4 CV1 OUT1 SY1 OUT1 SC1 OUT1 0 0 0 0 CV1 IN1 DC DC 0 0 0 1 CV2 IN2 DC DC 0 0 1 0 CV3 IN3 DC DC 0 0 1 1 CV4 IN4 SY4 IN4 SC4 IN4 0 1 0 0 SY4 + SC4 IN4 IN4 SY4 IN4 SC4 IN4 0 1 0 1 CV5 IN5 SY5 IN5 SC5 IN5 0 1 1 0 SY5 + SC5 IN5 IN5 SY5 IN5 SC5 IN5 0 1 1 1 CV6 IN6 SY6 IN6 SC6 IN6 1 0 0 0 SY6 + SC6 IN6 IN6 SY6 IN6 SC6 IN6 1 0 0 1 CV7 IN7 SY7 IN7 SC7 IN7 1 0 1 0 SY7 + SC7 IN7 IN7 SY7 IN7 SC7 IN7 1 0 1 1 DC DC DC 1 1 0 0 DC DC DC 1 1 0 1 DC DC DC 1 1 1 0 DC DC DC 1 1 1 1 DC DC DC *1 SDB00102AEB 16 AN15865A I2C Bus Conditions (continued) OUT2 signal select 00/D3 00/D2 00/D1 00/D0 CV2/SY2 OUT2 SC2 OUT2 0 0 0 0 CV1 IN1 DC 0 0 0 1 CV2 IN2 DC 0 0 1 0 CV3 IN3 DC 0 0 1 1 CV4 IN4 SC4 IN4 0 1 0 0 SY4 IN4 SC4 IN4 0 1 0 1 SY4 + SC4 IN4 IN4 SC4 IN4 0 1 1 0 CV5 IN5 SC5 IN5 0 1 1 1 SY5 IN5 SC5 IN5 1 0 0 0 SY5 + SC5 IN5 IN5 SC5 IN5 1 0 0 1 CV6 IN6 SC6 IN6 1 0 1 0 SY6 IN6 SC6 IN6 1 0 1 1 SY6 + SC6 IN6 IN6 SC6 IN6 1 1 0 0 CV7 IN7 SC7 IN7 1 1 0 1 SY7 IN7 SC7 IN7 1 1 1 0 SY7 + SC7 IN7 IN7 SC7 IN7 1 1 1 1 DC SDB00102AEB DC *1 17 AN15865A I2C Bus Conditions (continued) OUT3 signal select 01/D7 01/D6 01/D5 01/D4 CV3/SY3 OUT3 SC3 OUT 0 0 0 0 CV1 IN1 DC 0 0 0 1 CV2 IN2 DC 0 0 1 0 CV3 IN3 DC 0 0 1 1 CV4 IN4 SC4 IN4 0 1 0 0 SY4 IN4 SC4 IN4 0 1 0 1 SY4 + SC4 IN4 IN4 SC4 IN4 0 1 1 0 CV5 IN5 SC5 IN5 0 1 1 1 SY5 IN5 SC5 IN5 1 0 0 0 SY5 + SC5 IN5 IN5 SC5 IN5 1 0 0 1 CV6 IN6 SC6 IN6 1 0 1 0 SY6 IN6 SC6 IN6 1 0 1 1 SY6 + SC6 IN6 IN6 SC6 IN6 1 1 0 0 CV7 IN7 SC7 IN7 1 1 0 1 SY7 IN7 SC7 IN7 1 1 1 0 SY7 + SC7 IN7 IN7 SC7 IN7 1 1 1 1 DC SDB00102AEB DC *1 18 AN15865A I2C Bus Conditions (continued) OUT4 signal select 01/D3 01/D2 01/D1 01/D0 G1/Y1 OUT4 B1/U1 OUT4 R1/V1 OUT4 HOUT1 OUT4 VOUT1 OUT4 0 0 0 0 CV1 IN1 DC DC indefinite indefinite 0 0 0 1 CV2 IN2 DC DC indefinite indefinite 0 0 1 0 CV3 IN3 DC DC indefinite indefinite 0 0 1 1 Y7/CV4 IN4 U7/SY4 IN4 V7/SC4 IN4 indefinite indefinite 0 1 0 0 Y6/CV5 IN5 U6/SY5 IN5 V6/SC5 IN5 Hin6 IN5 Vin6 IN5 0 1 0 1 Y5/CV6 IN6 U5/SY6 IN6 V5/SC6 IN6 Hin5 IN6 Vin5 IN6 0 1 1 0 Y4/CV7 IN7 U4/SY7 IN7 V4/SC7 IN7 Hin4 IN7 Vin4 IN7 0 1 1 1 G3/Y3 IN8 B3/U3 IN8 R3/V3 IN8 Hin3 IN8 Vin3 IN8 1 0 0 0 G2/Y2 IN9 B2/U2 IN9 R2/V2 IN9 Hin2 IN9 Vin2 IN9 1 0 0 1 G1/Y1 IN10 B1/U1 IN10 R1/V1 IN10 Hin1 IN10 Vin1 IN10 1 0 1 0 DC DC DC indefinite indefinite 1 0 1 1 DC DC DC indefinite indefinite 1 1 0 0 DC DC DC indefinite indefinite 1 1 0 1 DC DC DC indefinite indefinite 1 1 1 0 DC DC DC indefinite indefinite 1 1 1 1 DC DC DC *1 indefinite indefinite SDB00102AEB 19 AN15865A I2C Bus Conditions (continued) OUT5 signal select 02/D3 02/D2 02/D1 012D0 G2/Y2 OUT5 B2/U2 OUT5 R2/V2 OUT5 HOUT2 OUT5 VOUT2 OUT5 0 0 0 0 CV1 IN1 DC DC *2 *2 0 0 0 1 CV2 IN2 DC DC *2 *2 0 0 1 0 CV3 IN3 DC DC *2 *2 0 0 1 1 Y7/CV4 IN4 U7/SY4 IN4 V7/SC4 IN4 *2 *2 0 1 0 0 Y6/CV5 IN5 U6/SY5 IN5 V6/SC5 IN5 *2 *2 0 1 0 1 Y5/CV6 IN6 U5/SY6 IN6 V5/SC6 IN6 *2 *2 0 1 1 0 Y4/CV7 IN7 U4/SY7 IN7 V4/SC7 IN7 *2 *2 0 1 1 1 G3/Y3 IN8 B3/U3 IN8 R3/V3 IN8 *2 *2 1 0 0 0 G2/Y2 IN9 B2/U2 IN9 R2/V2 IN9 *2 *2 1 0 0 1 G1/Y1 IN10 B1/U1 IN10 R1/V1 IN10 *2 *2 1 0 1 0 DC DC DC *2 *2 1 0 1 1 DC DC DC *2 *2 1 1 0 0 DC DC DC *2 *2 1 1 0 1 DC DC DC *2 *2 1 1 1 0 DC DC DC *2 *2 1 1 1 1 DC DC DC *1 *2 *2 Note) *1 : 3.5 Vdc are outputted at the time of mute mode *2 : It is based on a setup of sync distinction SDB00102AEB 20 AN15865A I2C Bus Conditions (continued) y The AN15865A selects slave address 85 or 8D(hex) according to the status of the SLVADR pin. Address 85(hex) will be selected with the SLVADR pin grounded the the GND side. Address 8D(hex) will be selected with the pin grounded to the 5-V line. Status register S Slave Address (85 or 8D) DATA (X) AM AM DATA (X + 1) DATA (X + 2) AM continue Note) AM = Ack from Master R/W = 1 D7 D6 D5 D4 D3 D2 DATA0 Aspect ratio SA3 00 : 4:3 video signal 01 : 4:3 letterbox 10 : 16:9 video signal 11 : No use Aspect ratio SA4 00 : 4:3 video signal 01 : 4:3 letterbox 10 : 16:9 video signal 11 : No use Aspect ratio SA5 00 : 4:3 video signal 01 : 4:3 letterbox 10 : 16:9 video signal 11 : No use DATA1 Pin detect SB3 0 : Open 1 : connect Pin detect SB4 0 : Open 1 : connect Pin detect SB5 0 : Open 1 : connect Pin detect SB6 0 : Open 1 : connect AFC-LOCK OUT5 0 : unlock System status 1 : lock Sync status 0 : 2 value 1 : 3 value MACRO VISION detection (OUT5) 0 : normal signal 1 : macro vision signal auto distinc. Result CVSYdet 0 : SY 1 : CV auto distinc. Result sync fix 0 : continue 1 : fix DATA2 Australia interlace 0 : except Australia 1 : Australia Australia format 0 : 1 152i 1 : 1 152i(letter) D1 D0 Aspect ratio SA6 00 : 4:3 video signal 01 : 4:3 letterbox 10 : 16:9 video signal 11 : No use 000 : 480i / 60 001 : 480p / 60 010 : 1 080i / 60 011 : 720p / 60 100 : 576i / 50 101 : 576p / 50 110 : 1 080i / 50 111 : 720p / 50 Signal detect 0 : no signal 1 : signal input 0 Note) The default data at the time of power-on is 0. SDB00102AEB 21 AN15865A I2C Bus Conditions (continued) Description of Registers 1. Control Register Out1 signal select Out2 signal select Out3 signal select Out4 signal select Out5 Sync distinction Free-run priority Out5 Sync Out5 signal select : Selects the Input IN1 to IN7 for OUT1(CV1, SY1, SC1) (Including Mute mode) : Selects the Input IN1 to IN7 for OUT2(CV2, SY2, SC2) (Including Mute mode) : Selects the Input IN1 to IN7 for OUT3(CV3, SY3, SC3) (Including Mute mode) : Selects the Input IN1 to IN10 for OUT4(G1/Y1, B1/U1, R1/V1, Hout1, Vout1) : Switches the sync identification AFC circuit operating mode 0 = Automatic identification (with priority ranking) (If input signal to both CV and SY, SY signal will be selected) 1 = Uses CV or Y input 2 = Uses SY input 3 = Free-run : The priority of a free-run is changed 0 = Fixed mode 1 = Auto distinction will be started if a signal is inputted into a Sync block While input signal is removed, return to free-run mode. (Free-run priority only enabled when Out5 sync distinction = free-run) : Selects H, V signal of Hout2, Vout2 whether independent H and V or AFC H and V 0 = AFC H and V 1 = independent H and V : Selects the Input IN1 to IN10 for OUT5(G2/Y2, B2/U2, R2/V2, Hout2, Vout2) Out4 matrix : Selects the type of matrix conversion of Out4 0 = Through 1 = CCIR protocol 2 = BTA protocol 3 = Convert GBR to YUV Out5 matrix : Selects the type of matrix conversion of Out5 0 = Through 1 = CCIR protocol 2 = BTA protocol 3 = Convert GBR to YUV Dummy sync mode control : Selects the type of output sync format of Out5 0 = 480i / 60 1 = 480p / 60 2 = 1080i / 60 3 = 720p / 60 4 = 576i / 50 5 = 576p / 50 6 = 1 080i / 50 7 = 720p / 50 HVout2 polarity : Select the polarity of HOUT2 and VOUT2 at AFC mode 0 = positive, Sync level is high 1 = Negative, Sync level is low SDB00102AEB 22 AN15865A I2C Bus Conditions (continued) CV1 GAIN SY1/SC1 GAIN CV2 GAIN SY2/SC2 GAIN CV3 GAIN SY3/SC3 GAIN OUT4 GAIN OUT5 GAIN OUT1 LPF OUT2 LPF OUT3 LPF OUT4 LPF OUT5 LPF OUT1 DCOUT Field monitor select INPUT4 U/SY select : Select the gain of OUT1(CV1) 0 = 0 dB 1 = 6 dB : Select the gain of OUT1(SY1, SC1) 0 = 0 dB 1 = 6 dB : Select the gain of OUT2(CV2) 0 = 0 dB 1 = 6 dB : Select the gain of OUT2(SY2, SC2) 0 = 0 dB 1 = 6 dB : Select the gain of OUT3(CV3) 0 = 0 dB 1 = 6 dB : Select the gain of OUT3(SY3, SC3) 0 = 0 dB 1 = 6 dB : Select the gain of OUT4(G1/Y1, B1/U1, R1/V1) 0 = 0 dB 1 = 6 dB : Select the gain of OUT5(G2/Y2, B2/U2, R2/V2) 0 = 0 dB 1 = 6 dB : This switch selects LPF on/off of OUT1 0 = Through 1 = LPF ON : This switch selects LPF on/off of OUT2 0 = Through 1 = LPF ON : This switch selects LPF on/off of OUT3 0 = Through 1 = LPF ON : This switch selects LPF on/off of OUT4 0 = Through 1 = LPF ON : This switch selects LPF on/off of OUT5 0 = Through 1 = LPF ON : Selects the DC level to OUT1(SC1) . This DC level corresponds to S2 standard. 0=0V 1 = 1.9 V 2 = indefinite 3 = 4.5 V : Selects the field distinction signal in interlace mode, or the oscillation clock of built-in VCO 0 = Field1/Field2 out (Field1 : Low Field2 : High) 1 = clock monitor out : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select SDB00102AEB 23 AN15865A I2C Bus Conditions (continued) INPUT5 U/SY select INPUT6 U/SY select INPUT7 U/SY select INPUT8 BR/UV select INPUT9 BR/UV select INPUT10 BR/UV select Australia free-run 2. Status Register Scart Ident SA3 Scart Ident SA4 Scart Ident SA5 Scart Ident SA6 Pin detect SB3 Pin detect SB4 : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select : The mode changeover switch of an incoming signal 0 : BR input select 1 : UV input select : The mode changeover switch of an incoming signal 0 : BR input select 1 : UV input select : The mode changeover switch of an incoming signal 0 : BR input select 1 : UV input select : Set up, when you oscillate the free-run of the Australia signal 0 = except Australia 1 = Australia mode : Return the control voltage of SA3(Pin 51) 0 = less than 1 V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite : Return the control voltage of SA4(Pin 55) 0 = less than 1V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite : Return the control voltage of SA5(Pin 47) 0 = less than 1V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite : Return the control voltage of SA6(Pin 59) 0 = less than 1V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite : Return the control voltage of SB3(Pin 53) 0 = 5 V(Open) 1 = 0 V(Connected) : Return the control voltage of SB4(Pin 57) 0 = 5 V(Open) 1 = 0 V(Connected) SDB00102AEB 24 AN15865A I2C Bus Conditions (continued) Pin detect SB5 : Return the control voltage of SB5(Pin 45) 0 = 5 V(Open) 1 = 0 V(Connected) Pin detect SB6 : Return the control voltage of SB6(Pin 61) 0 = 5 V(Open) 1 = 0 V(Connected) AFC-LOCK : Indicate the AFC lock status in the sync separation 0 = unlocked 1 = locked OUT5 System status : Return the input signal format after sync separated 0 = 480i / 60 4 = 576i / 50 1 = 480p / 60 5 = 576p / 50 2 = 1080i / 60 6 = 1080i / 50 3 = 720p / 60 7 = 720p / 50 Sync status : Return of identifying whether the input is ternary sync 0 = Binary sync 1 = Tri-level sync MACRO VISION : Indicate the whether to be a macro vision signal 0 = normal signal 1 = macro vision signal Auto Distinction Result of CV/SY detection : The detection result is indicated on which Sync shall have ridden between "CV" or "SY" 0 = SY 1 = CV Auto Distinction Result of Sync fixing situation : It indicates whether the detection result of Auto distinction fixed 0 = Under the check 1 = fixed Australia interlace : It indicates whether the input signal is Australia format 0 = except Australia 1 = Australia Australia format : It indicates the type of Australia format 0 = 1152i 1 = 1152i(litter) Signal detect : It indicates whether there is input signal 0 = no signal 1 = Signal input SDB00102AEB 25 AN15865A 41 Vin6 42 V6/SC5 0.47 µF 43 Hin6 44 U6/SY5 0.47 µF 45 SB5 46 Y6/CV5 0.47 µF 47 SA5 Input 5 0.47 µF 48 CV1 50 CV2 0.47 µF Input 1 49 GND1 Input 2 51 SA3 52 CV3 0.47 µF 53 SB3 54 Y7/CV4 0.47 µF 55 SA4 0.47 µF 57 SB4 58 V7/SC4 0.47 µF 59 SA6 60 Y5/CV6 0.47 µF 61 SB6 62 U5/SY6 0.47 µF 63 Hin5 64 V5/SC6 0.47 µF Input 3 Input 4 Input 6 56 U7/SY4 Test Circuit Diagram Vin5 65 Y4/CV7 66 Input 7 Signal Generator 0.47 µF 9V 37 DCOUT V4/SC7 70 35 SLVADR Input 8 80 10 µF 25 Hout1 Output 2 10 µF Output 3 10 kΩ 10 kΩ 10 kΩ 10 kΩ Output 4 10 µF 10 µF 5V 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ Output 5 10 kΩ 22 nF 4.7 kΩ 4.7 µF 10 nF 0.47 µF 0.47 µF 0.47 µF Vin2 1 3.3 V 0.47 µF R1/V1 22 10 µF Vout1 23 10 µF B1/U1 24 10 µF B2/U2 R2/V2 16 10 µF Vout2 17 10 µF B2/U2 18 10 µF Hout2 19 10 µF G2/Y2 20 10 µF GND3 21 26 G1/Y1 Vsyncsepa 14 79 75 kΩ Field monitor 15 Hin2 Sync-in 13 27 VCC3 Sync-out 12 78 GND4 11 G2/Y2 AFC1 10 28 SC3 10 µF R1/V1 9 77 Vin1 8 VCC4 B1/U1 7 29 GND Hin1 6 76 G1/Y1 5 R3/V3 SCL 4 30 CV3/SY3 0.47 µF HV Signal Generator 10 kΩ 75 SDA 3 Input 9 0.47 µF 10 µF 31 GND2 Vin3 R2/V2 2 5V 10 kΩ 32 SC2 Hin3 73 0.47 µF 0.47 µF 10 kΩ 10 µF 33 GND B3/U3 74 0.47 µF 10 kΩ 34 CV2/SY2 71 G3/Y3 72 0.47 µF Output 1 36 SC1 10 µF Vin4 69 VCC1 9V 38 SY1 10 µF Hin4 67 U4/SY7 68 0.47 µF 10 kΩ 39 VCC2 10 kΩ 0.47 µF 40 CV1 10 µF Input 10 BUS Control SDB00102AEB 26 AN15865A Technical Data 1. Circuit diagrams of the input/output part and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Inner circuit VIN HIN Pin 1, 8, 41, 65, 69, 75 Pin 6, 43, 63, 67, 73, 79 1 6 8 41 43 63 65 67 69 73 75 79 2 5 7 9 44 46 48 50 52 54 56 60 62 66 68 72 74 76 78 80 Description 5V 75k 60k 34k 2V Independent H, V signal input pins. 12k 200k 1k G/Y B/U R/Y U/SY Y/CV 85k 40k Pin 5, 72, 78 Pin 7, 74, 80 Pin 2, 9, 76 Pin 44, 56, 62, 68 Pin 46, 48, 50, 52, 54, 60, 66 9V 25µ 25µ 90k G/Y, B/U, R/V, U/SY, Y/CV signal input pins. 3.7 V 4V 50µ 25µ 12k SDB00102AEB 27 AN15865A Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Inner circuit Description 5V 50k 50µ SDA Pin 3 1.5k 1.9 V I2C bus data input pin. 3 12k 90k 30k ACK 5V 50k 50µ SCL Pin 4 1.5k 1.9 V 4 12k 90k I2C bus clock input pin. 30k 5V 25µ AFC1 Pin 10 10 AFC filter pin. 9V 900µ 12k SDB00102AEB 28 AN15865A Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. 11 Inner circuit Description GND4 Pin 11 5V system ground pin. 9V 100µ Sync-out Pin 12 12 Sync signal output pin for sync separation. 12k 100µ 5V 60µ 40µ 3µ 13 1.3µ 1.5V Sync signal input pin for sync separation. 80µ Sync-in Pin 13 12k SDB00102AEB 29 AN15865A Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Inner circuit Description V sync sepa Pin 14 5V 12µ 10µ 17k 14 V sync separation filter pin. 80k 40µ 75k 0.022µ 12k Field monitor Pin 15 9V 3.3 V 15 Field change signal output pin. 12k SDB00102AEB 30 AN15865A Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. 16 18 20 22 24 26 28 30 32 34 36 38 40 Inner circuit G/Y B/U R/V CV/SY SC Pin 20, 26 Pin 18, 24 Pin 16, 22 Pin 30, 34, 38, 40 Pin 28, 32, 36 9V 100µ 12k Vout Hout 17 19 Description G/Y, B/U, R/V, CV/SY, SC signal output pins. 100µ Pin 17, 23 Pin 19, 25 9V AFC or independent H, V signal output pins. 3.3 V 12k 23 25 21 Independent H, V signal output pins GND3 Pin 21 5 V system ground pin. SDB00102AEB 31 AN15865A Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Inner circuit Description VCC3 Pin 27 5V CIRCUIT 5 V system power supply pin. x Apply 5 V. 27 12k 29 GND 31 GND2 Pin 31 33 GND Pin 29 9 V system ground pin. Pin 33 5V SLVADR 60k 75k Pin 35 34k 2V 35 200k 85k 12k 40k Pin to output DC voltage corresponding to S2, which overlaps the SC1 signal on Output 1. The DC voltage varies with the setting in the control register. 35k DCOUT Pin 37 37 12k 50µ 25µ SDB00102AEB 05/D2 05/D1 DC value 0 0 0V 0 1 1.9 V 1 0 indefinite 1 1 4.5 V 32 AN15865A Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Inner circuit Description VCC2 Pin 39 9V CIRCUIT 9 V system power supply pin. x Apply 9 V. 39 12k 9V 25µ 90k 42 58 64 70 4V V/SC V/SC signal input pins. 50µ Pin 42, 58, 64, 70 25µ 12k SB Pin 45, 53, 57, 61 5V 45 53 57 61 75k 200k 60k 34k 2V Pin status detection pins. Pin opened : No signal. Pin shorted : With signal. Status data is transferred to the microcomputer in serial. 12k 85k 40k SDB00102AEB 33 AN15865A Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Inner circuit Description 5V 24k SA 85k 34k 47 51 55 59 3.5 V 39k 1.6 V 12k 200k 85k 49 29k Pin 47, 51, 55, 59 85k Aspect ratio detection pins. Pin voltage Aspect ratio 5.0 V to 4.0 V 16 : 9 3.0 V to 1.7 V Letter-box 1.0 V to 0 V 4:3 32k GND1 Pin 49 5 V system ground pin. VCC1 Pin 71 9V CIRCUIT 9 V system power supply pin. x Apply 9 V. 71 12k VCC4 Pin 77 5V CIRCUIT 5 V system power supply pin. x Apply 5 V. 77 12k SDB00102AEB 34 AN15865A Technical Data (continued) 2. Notes on video gain Input Output 6 dB use 0 dB use 0 dB / 6 dB 1 V[p-p] 1 V[p-p] 2 V[p-p] I2C control 0 dB 2 V[p-p] 2 V[p-p] I2C control For 1 V[p-p] input signal, both 0 dB and 6 dB gain can be enabled. However, for 2 V[p-p] input signal, only 0 dB gain is allowed for normal operation. 0 dB / 6 dB SY I2C control SY + SC SC 0 dB / 6 dB The gain of SY + SC can be controlled by Control Register SY/SC GAIN. SY/SC GAIN = 0 SY + SC = –6 dB SY/SC GAIN = 1 SY + SC = 0 dB please note that the gain of SY + SC is not controlled by Control Resister CV GAIN. 3. Other supplementary matters y The remedy of APL change please attach resistance of 1 MΩ - 3 MΩ to each pin of CV and SY between opposite GND by carrying out that it is hard to receive APL change. y How to output a synchronous separation output to Hout2 to Vout2 Please choose "1" by test76(07/D6) and out5 sync(02/D4) in a control register, respectively. SDB00102AEB 35 AN15865A Usage Notes 1. For use, voltages above 5.5 V should not be applied to the following pins. (Pin No. 15, 17, 19, 23, 25) 2. Pay enough attention to that following items when using the IC, otherwise the IC may break or give off smoke. y Do not insert the IC in the reverse direction. 3. Keep in mind the it may cause a latch-up by the following pins in the examination of the method of pulse current. Pin number Merit level (mA) 46 –100 47 –90 52 –80 53 –70 62 –80 Be careful not to impress the pulse current more than the above. The current level is describing the merit value of the pulse current which a latch-up does not generate. However, in all pins, a latch-up is not caused by the examination of the CV method. (200pF 200V) 4. Purchase of Panasonic I2C Components conveys a license under the Philips I2C patent right to use these components in an I2C systems, provided that the system conforms to the I2C standard specifications as defined by Philips. SDB00102AEB 36 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: • Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. • Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. 2002 JUL