TOSHIBA TC90A80F

TC90A80N/F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC90A80N,TC90A80F
3-Line Digital Comb Filter for VCR, YNR/CNR, and Skew Correctors (NTSC)
The TC90A80N/F is a 3-line digital Y/C (luminance/
chrominance) separation IC for VCR.
In addition to YNR and CNR used for noise reduction in the
playback signal, the IC incorporates skew correctors for special
playback. The IC is then suitable for processing S-VHS recorded
playback signals.
TC90A80N
Features
•
TV format: NTSC (3.58)
•
Dynamic comb filter
•
YNR circuit
•
CNR circuit
•
Luminance signal non-linear vertical edge corrector (with
coring function)
•
Luminance signal horizontal frequency characteristic
corrector (with coring function)
•
Luminance signal line noise canceller
•
Record/playback input switch circuit (switches between Y/C
and Y inputs)
•
Y and C input pins, independently one another (Y: sync tip
clamp; C: center bias)
•
Re-mixer circuit after Y/C sharpness processing
•
Skew detector and correctors (NTSC ×5 Mode: in units of 0.2
H)
•
PLL detector for switching frequencies (fsc, 2 fsc, 4 fsc and 8 fsc clock inputs)
•
8-bit 4 fsc AD converter (2 channels)
•
10-bit 8 fsc DA converter (2 channels)
•
1-H delay line (2 channels)
•
I2C bus control
•
I2C bus decode output pin (High/Low)
•
5-V single power operation
TC90A80F
1
Weight
SDIP28-P-400-1.78 : 1.7 g (typ.)
SOP28-P-450-1.27 : 0.8 g (typ.)
2002-12-04
TC90A80N/F
Mode1
HD + PV
OUT
SDA
SCL
fsc-IN
+5 V
(PLL)
Y-OUT
C-OUT
Block Diagram
18
17
16
15
0.1 µF
27
26
VSS2
25
DAC
(8 fsc)
Interpolation
Mix
ON
Delay Adj
(±210 @70 ns)
CNR
YCS
PLL
detector
VCO
21
VSS5
1/2
8 fsc
+
Y-EQ
Y-N.C
LPF
0.01 µF
19
I2C bus
4 fsc
Skew
1/8 1/4 1/2 0
Ped. CLIP
20
VDD5
Delay
Killer
N.L V-enhancer
YNR
Memory
YCS Memory
[B]
[A]
Dynamic comb
Filter
YNR
Skew
corrector
ADC
ADC
Skew
detector
VSS3
10
11
VDD3
12
VDD4
13
PG
14
0.01 µF
0.01 µF
0.47 µF
2
C.SYNC
IN
+5 V
(digital)
47 µF
KILLER
/PV IN
Y/C-IN
100 µF
6
0.47 µF
0.1 µF
Sync Clamp
TEST
7
8
9
Y-IN
4
VSS1
5
0.01 µF
2
VDD1
3
0.01 µF
Bias
+5 V
(ADC)
0.01 µF
22
C-N.C
BPF
Memory
[B]
0.01 µF
+
23
VDD2
Skew
corrector
CNR
1
24
Mix
OFF
680 pF
0.1 µF
DAC
C-IN
28
100 µF
330 Ω
0.01 µF
0.01 µF
0.1 µF
2002-12-04
TC90A80N/F
Pin Functions
Pin
No.
Pin Name
1
BIAS
DC Level
(V)
Function
Interface Circuit
1.3
1
3.16
2
ADC bias pin
Sets upper limit of range D for ADC.
VRT
Connect a 0.01-µF capacitor between this pin and pin 5
(VSS1).
20 Ω
The output voltage is held at internal level.
3
VDD1
ADC power supply pin (analog)
Apply the same voltage as that of pin 23 (VDD2).
5.0
Internally connected to pin 23 (VDD2).
Chrominance signal input pin
(I2C Bus function: NR)
CIN
5
VSS1
Because the signal is internally center-biased, it should
be applied after cutting the DC component using a
capacitor of around 0.01 µF.
ADC GND pin (analog)
Set the same voltage as that of pin 26 (VSS2).
2.5
4
20 Ω 15 kΩ
15 kΩ
4
0.0
Internally connected to pin 26 (VDD2).
ADC bias pin
Sets lower limit of range D for ADC.
6
VRB
Connect a 0.01-µF capacitor between this pin and pin 5
(VSS1).
1.83
6
20 Ω
The output voltage is held at internal level.
Sync Tip
Luminance signal input pin
(I2C Bus function: NR)
7
YIN
15 kΩ
2
660 Ω 1.14 kΩ
Connect a 0.01-µF capacitor between this pin and pin 5
(VSS1).
1.14 kΩ 660 Ω
ADC bias pin
Because sync tip clamp is internally used, the signal
should be applied after cutting the DC component
using a capacitor of around 0.47 µF.
NR Mode
: 1.86
7
YCS Mode
: 1.83
20 Ω
20 Ω
Pin for reset control and test control when shipping.
8
TEST
Reset control: Applying pulse of 10 µs or longer while
the pin is at High with power on resets all the I2C bus
settings to 0. For normal use, set the pin to Low.
3
0.0
8
150 Ω
2002-12-04
TC90A80N/F
Pin
No.
Pin Name
DC Level
(V)
Function
Sync Tip
Composite video signal input pin
(I2C Bus function: YCS)
9
10
YCIN
VSS3
Interface Circuit
Because sync tip clamp is internally used, the signal
should be applied after cutting the DC component
using a capacitor of around 0.47 µF.
Logic and DRAM GND pin (digital)
YCS Mode
: 1.86
9
NR Mode
: 1.83
20 Ω
0.0
Separate digital VSS from analog VSS.
20 Ω
―
Killer control and pseudo vertical pulse (PV) input pin
(M or H polarity can be selected using I2C Bus.)
11
KIPVIN
In Killer mode, Y/C separation, vertical enhancer, CNR,
and YNR are halted.
PV input: Vertical mask signal for detecting skew.
Apply PV which is synchronous with input video signal.
3-level
input
11
700 Ω 3.2 V
1.4 V
For normal use, or not in use, set the pin to Low.
12
VDD3
13
VDD4
Logic power supply pin (digital)
Separate digital VDD from analog VDD.
DRAM power supply (digital)
Separate digital VDD from analog VDD.
5.0
―
5.0
―
Composite sync pulse input pin for detecting skew
14
15
16
CSYNCIN
SCL
SDA
Apply sync separation pulse (positive polarity pulse) of
the input video signal.
When not in use, set to Low.
2
I C bus clock input pin
14
―
―
2
I C bus data input/output pin
700 Ω
―
15
16
700 Ω
700 Ω
ACK
Sync output pin
17
HDPVOUT
In Skew Correction Mode: Output can be selected as
either HD pulse which is synchronous with output video
signal or signal mixed with input PV.
―
17
In modes other than Skew Correction, drives out C
Composite sync pulse. Use for later-stage circuit such
as 3DNR.
4
2002-12-04
TC90A80N/F
Pin
No.
Pin Name
18
MODE1
DC Level
(V)
Function
Interface Circuit
MODE1 output pin
―
18
Apply sine wave locked to the frequency of the input
video burst signal. One of the four frequencies (fsc,
2fsc, 4fsc, and 8fsc) can be selected using I2C bus.
2.45
19
High or Low output voltage signal can be selected
using I2C bus. Use for controlling peripheral circuits.
Clock input pin
19
FSC
170 Ω
300 kΩ
20
VDD5
PLL power supply pin (analog)
5.0
―
21
VSS5
PLL GND pin (analog)
0.0
―
90 Ω
VCO control pin
22
FIL
23
VDD2
24
VB2
Connect lag-lead filter between this pin and pin 21
(VSS5).
DAC power supply pin (analog)
Apply the same voltage as that of pin 3 (VDD1).
3.0
22
100 Ω
5.0
Internally connected to pin 3 (VDD1).
DAC bias 2 pin
3.4
24
Sync Tip
: 2.46
25
400 Ω
Connect a 0.01-µF capacitor between this pin and pin
26 (VSS2).
Luminance signal output pin
25
YOUT
26
VSS2
When Y/C Re-Mix Mode is selected using I2C bus, this
pin drives out a composite video signal.
DAC GND pin (analog)
Set the same voltage as that of pin 5 (VSS1).
5
0.0
Internally connected to pin 5 (VSS1).
2002-12-04
TC90A80N/F
Pin Name
27
COUT
28
VB1
DC Level
(V)
Function
Interface Circuit
400 Ω
Pin
No.
Chrominance signal output pin
When Y/C Re-Mix Mode is selected using I2C bus, this
pin drives out no signal.
3.7
27
DAC bias pin 1
Connect a 0.01-µF capacitor between this pin and pin
26 (VSS2).
1.6
28
Note 1: Caution regarding external circuits (component allocation) for improving S/N and stabilizing operation:
Power supply pins are paired with GND pins. Read the section on Pin Functions and connect a ceramic
capacitor and an electrolytic capacitor directly between power supply and GND pins.
Toshiba recommend using a capacitor of 0.1 µF or more between analog power supply and GND pins. (For
digital pins, use a 0.01-µF capacitor.)
6
2002-12-04
TC90A80N/F
IC Control Specifications
•
Functions and characteristics of this IC are set using the I2C bus.
•
The data transfer format conforms to the Philips I2C bus format.
•
When reset signal is applied, the following DATA bits are all cleared to 0.
•
Data transfer format
S
Slave address (8 bits)
A
DATA1
A
DATA2
A
DATA3
A
DATA4
A
P
Slave address: B4H S: Start condition, A: Acknowledgement, P: Stop condition
•
Outline of I2C bus format
I2C bus transfers data between ICs using two lines: data (SDA) and clock (SCL).
The I2C bus starts according to the start condition and ends according to the stop condition.
The start condition is satisfied if SDA changes from High to Low when SCL is High.
The stop condition is satisfied if SDA changes from Low to High when SCL is High.
The length of data to be transferred is 8 bits. Data are transferred via the SDA line. An acknowledge (ACK) bit
is required after a data byte. The bus line must be pulled up to the power supply level using a resistor. When
SCL is High, data must not be changed.
•
I2C bus control signal timing
Don’t change the data while clock is in High level.
tBUF
tr
tf
Date
tf
Clock
Start Condition
tr
tSU; DAT
tHD; DAT
tHD; STA
tHIGH
tSU; STO
Stop Condition
tLOW
Characteristics
Symbol
Min
Max
Unit
fSCL
0
100
kHz
tHD; STA
4.0
―
µs
SCL clock Low period
tLOW
4.7
―
µs
SCL clock High period
tHIGH
4.0
―
µs
Data hold time
tHD; DAT
0
3.45
µs
Data setup time
tSU; DAT
250
―
ns
SDA/SCL signal rise time
tr
―
1000
ns
SDA/SCL signal fall time
tf
―
300
ns
Stop condition setup time
tSU; STO
4.0
―
µs
tBUF
4.7
―
µs
SCL clock frequency
Hold time to satisfy start condition
Bus free time between stop and start conditions
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by
Philips.
7
2002-12-04
TC90A80N/F
I2C Bus Control Data List
I2C Bus Control List
DATA1
Slave address: 1011010x
D7
D6
Function
Skew
0: YCS
0: OFF
1: NR
1: ON
D5
00: OFF
10: 0.625
01: 0.5
11: 0.75
000: ±0 ns
011: −210
001: −70
100: ±0 ns
010: −140
101: +70
000: 1
011: 7
001: 3
100: 9
010: 5
101: 11
D1
D-Range
D0
Input Clock
110: +140
0: 2 Vp-p
00: fsc
10: 4 fsc
111: +210
1: 1 Vp-p
01: 2 fsc
11: 8 fsc
CNR Corr.
Y-EQ/N.C Lim
Mode1
Y-EQ/N.C fo
110: 13
0: ON
0: Low
0: High
111: 15
1: OFF
1: High
1: Low
YNR Corr.
Pulse M/H
Sync Out
Y/C Mix
00: OFF
10: 0.25
00: OFF
10: H4 (L8)
0: ON
0: PV
0: HD
0: OFF
01: 0.125
11: 0.5
01: H2 (L4)
11: H8 (L14)
1: OFF
1: Killer
1: HD + PV
1: ON
V-Emph Gain (YCS)
DATA4
D2
CNR Lim.
Y-EQ Gain
DATA3
D3
C-Delay
CNR Gain
DATA2
D4
000: OFF
011: +0.50
001: +0.25
100: +0.75
010: +0.25
101: +1.00
110: +1.25
111: +1.50
V-Emph N.L (YCS)
000: 4
011: 16
001: 8
100: 20
010: 12
101: 24
YNR Gain (NR)
000: OFF
011: 0.375
001: 0.125
100: 0.5
010: 0.25
101: 0.625
110: 28
00: OFF
10: 2
111: 32
01: 1
11: 3
YNR Lim (NR)
110: 0.75
111: 0.875
000: 1
011: 7
001: 3
100: 9
010: 5
101: 11
8
V-Emph Core (YCS)
YNR Mode (NR)
110: 13
00: YNR-W
111: 15
01: YNR-N
10:
YCOMB-W
11:
YCOMB-N
2002-12-04
TC90A80N/F
Description of I2C Bus Control
(1)
Function
: Controls input signal and IC functions. (YCS: Y/C-IN → 3 line Y/C separation, NR: Y
and C input independently → YNR, CNR)
(2) Skew
: Controls skew correction. (OFF: normal mode, ON: Corrects skew every 0.2 H.)
(3) C-Delay
: Controls Y/C time. (Switches chroma signal delay time. −: Advances chroma signal.
+: Delays chroma signal.)
(4) D-Range
: Controls input/output gain. (2 Vp-p: 1 V input 2 V output, Gain = 6dB, 1 Vp-p: 1 V
input 1 V output, Gain = 0dB)
(5) Input Clock
: Controls clock PLL. (Select input clock.)
(6) CNR Gain
: Controls CNR cyclic coefficient/subtraction gain. (OFF: Stops CNR. 0.75: Maximum
effect)
(7) CNR Lim.
: Controls the CNR limiter. (Limiter level when converting 100 IRE input.: 4 ≈ −31dB
to 18 ≈ −18dB)
(8) CNR Corr.
: Controls CNR correlation/non-correlation
ON: Controls CNR correlation/non-correlation. → Low vertical color misalignment
OFF: Maximum → effect with vertical color misalignment
(9) Mode1
: Controls parallel output. (Low: Drives out voltage approx. VSS. High: Drives out
voltage approx. VDD.)
(10) Y-EQ fo
: Corrects Y frequency characteristic and controls Y-NC bottom frequency. (high: 4/3
fsc, low: fsc)
(11) Y-EQ Gain
: Controls Y frequency characteristic correction addition gain. (OFF: Stops frequency
characteristic correction. 0.5: Corrects by +3dB at 3 MHz.)
(12) Y-EQ/N.C Lim
: Controls Y frequency characteristic correction coring level and Y-NC limiter. (OFF:
N.C OFF, H*: Limiter level when Y-EQ fo = high, L*: Limiter level when Y-EQ fo =
low, When converting 100 IRE input, limiter levels are as follows.2: −37dB, 4: −31dB,
8: −25dB, 14: −20dB)
(13) YNR Corr.
: Controls YNR correlation/non-correlation
ON: Controls YNR correlation/non-correlation → Low Y vertical color misalignment
OFF: Maximum effect → with Y vertical color misalignment
(14) Pulse Middle/High : Controls High pulse input polarity. (PV: PV with M/H and Killer with Middle/Low,
Killer: Killer with M/H and PV with M/L)
PV: Used for vertical-masking PLL for detecting skew and driving out HD + PV
when compensating skew.
Killer: Used for controlling separation Off, V-Emph Off in YCS Mode, and YNR/CNR
Off in NR Mode.
(15) Sync Out
: Controls pulse output in Skew Correction Mode. (HD: Drives out HD which is
synchronous with output signal. HD + PV: Mixes PV in HD which is synchronous
with to output signal.) HD lock phase is not held (varies from 500 ns to 600 ns).
In modes other than Skew Correction, drives out input C.SYN after delaying approx.
560 ns.
(16) Y/C Mix
: Controls Y/C mix output. (OFF: Drives out separated Y and C. ON: Drives out mixed
Y and C from the Y output pin. The C output pin is mute.)
(17) V-Emph Gain (YCS) : Controls vertical enhancer gain. (OFF: Enhancer Off. +1.5: Maximum effect)
(18) V-Emph N.L (YCS) : Controls vertical enhancer non-linear point. (4: Low effect, 32: Maximum effect)
(19) V-Emph Core (YCS) : Controls vertical enhancer coring. (OFF: Coring Off. 3: Emphasizes non correlation
of approx. 15 mV or more.)
(20) YNR Gain (NR)
: Controls YNR cyclic coefficient/subtraction gain. (OFF: Stops YNR. 0.875: Maximum
effect)
(21) YNR Lim (NR)
: Controls the YNR limiter. (Limiter level when converting 100 IRE input.: 1 ≈
−43dB~15 ≈ −19dB)
(22) YNR Mode (NR)
: Controls YNR and Y-COMB bandwidths. (*-W: Wideband, *-N: Narrowband)
(Note that the controls of DATA4 D7 to DATA4 D0 vary according to the setting of DATA1 D7 (function).)
9
2002-12-04
TC90A80N/F
Functions
Bus Setting
Function
YCS
(composite video
signal input)
Function
Skew
Y/C
Sep
CDelay
Drang
CK
Select
CNR
YNR
OFF
3 Line
Comb
Sep
O
O
O
△
C-N.C
×
BPF
Sep
O
△
C-N.C
×
ON
NR
(Y and C input
independently)
OFF
ON
×
×
O
O
O
O
O
O
O
O
O
△
C-N.C
O
×
YVSkew
EQ/NC Emph
O
O
O
O
O
O
×
×
×
O
×
O
Killer
PM/H
Sync
output
O
O
C.Sync
O
O
O
O
O
O
HD·PV
C.Sync
HD·PV
Y/C
MIX
YOUT
COUT
OFF
Y
C
ON
Y/C
Mute
OFF
Y
C
ON
Y/C
Mute
OFF
Y
C
ON
Y/C
Mute
OFF
Y
C
ON
Y/C
Mute
O: Specified, ×: Not specified
Description of Functions
(1) 3-line Y/C separation circuit (VTR Record Mode)
Provides clear Y and C separation using a dynamic comb filter, which logically extracts the chrominance
signal, based on the result of detecting vertical 3-line non correlation using two 1-H delay lines.
Also incorporates a vertical edge enhancer with coring function, which produces a clearer record signal
with suppressed noise.
(2) YNR and CNR circuits (VTR Playback Mode)
Independently incorporates cyclic noise reduction using 1-H delay lines for Y and C, effectively reducing
vertical non-correlation noise in the playback signal.
(3) Skew corrector (Special Playback Mode for VHS VTR ×5 speed videotape)
From composite sync pulse signal (sync separation output) detects horizontal skew in units of 0.2 H (×2 =
0.4 H before and after Cue/Rev noise bar) generated at special playback of VHS VTR ×5 speed videotape.
Using the detection result, automatically corrects horizontal skew included in the input playback video
signal by switching the delay time for line memory.
This function can be used for both composite video signals and independently-applied Y and C signals.
1) Pseudo vertical (PV) signal and composite signal necessary for detecting skew
Based on the reference signal of the horizontal frequency generated from the input composite sync
signal, detects the position of input sync signal in units of 0.2 H. Because skew is detected due to the
noise included in the input composite signal, apply the composite sync signal from which noise is
reduced to some extent at sync separation (no filter in the IC).
Note that erroneous skew detection around the period where vertical sync signal is included can be
prevented by halting skew detection and by setting PLL to the fh as reference during the PV pulse
period. So, apply pseudo vertical signal.
2) Supplementary function: pin 17 (HDPVOUT)
In Skew Correction Mode, pin 17 drives out the HD pulse (width: approx. 4 µs) which synchronizes with
the video signal after skew correction; in modes other than Skew Correction, pin 17 drives out the input
composite sync signal. Pin 17 can also be used for output with the input PV mixed using the I2C bus (in
Skew Correction Mode only). Use pin 17 for later-stage circuit such as 3DNR. Note, however, that since
the HD lock position and jitter performance are not designed for high precision, do not use pin 17
directly for circuits requiring high precision.
3) Recommended use conditions (eg, search speed)
Since the skew amount is not the same for Cue/Rev with ×5 speed tape, depending on the search speed,
after skew correction, horizontal synchronization may become inconsistent at junctions between fields.
As a result, the time for each field differs and vertical synchronization degrades.
To avoid this phenomenon, it is necessary to select a search speed where four types of skew comprise a
cycle during a 1-V pulse period (excluding PV pulse period). Consider a search speed with no or not
much degradation of vertical synchronization, paying attention to the position of the noise bar.
(Example): In ×11 Cue Mode, skew for the 1-V pulse period consists of Skew 0 H → noise → skew 0.4 H
→ noise → skew 0.8 H → noise → skew 0.2 H → noise → skew 0.6 H → noise → skew 0 H.
Where, consistency of horizontal synchronization is maintained. Degradation of vertical
synchronization can also be made less conspicuous visually by increasing the search speed.
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2002-12-04
TC90A80N/F
Maximum Rating (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Supply voltage
VDD
VSS + 6.0
V
Input voltage
VIN
VSS í 0.3 to VDD + 0.3
V
Potential difference between power
supply pins
(Note 2)
VDG
0.4
V
Power dissipation
(Note 3)
TC90A80N
TC90A80F
Storage temperature
900
mW
PD
600
Tstg
-55 to +125
°C
Note 2: Connect pin 3 to pin 23. The potential difference among all power supply pins, 3 (23), 12, 13, and 20, must
not exceed 0.4 V.
The potential difference among VSS pins 5, 10, 21, and 26 must not exceed 0.01 V.
Note 3: Ta = 75°C for TC90A80F mounted on a PCB (70 mm × 70 mm × 1.6 mm)
Recommended Operating Conditions
Characteristics
Symbol
Min
Typ.
Max
Unit
Supply voltage
VDD
4.75
5.00
5.25
V
Potential difference between pins 3
and 23
(Note 4)
VDG1
ʊ
0
0.04
V
Potential difference among power
supply pins 3,12, 13, and 20
VDG2
ʊ
0
0.15
V
Potential difference among VSS pins
5, 10, 21, and 26
VSG
ʊ
0
0.01
V
Input voltage
VIN
0
ʊ
VDD
V
Operating temperature
Topr
í10
ʊ
75
°C
Note 4: Since power supply pins 3 and 23 are connected in the IC, supply power to them at the same voltage.
If there is a large potential difference between the pins, a large current flows through the IC causing
degradation or damage due to heat stress.
Maximum ratings: A set of specified parameter values which must not be exceeded during operation, even for an
instant. If any of these limit values is exceeded during operation, it causes permanent damage to
the TC90A80N/F. Therefore, care must be exercised that the TC90A80N/F operates within the
specified ranges.
Recommended operating conditions: Minimum, typical and maximum values for key operating parameters such as
supply voltage, DC voltage and operating temperature. Ensuring that the
parameter values remain within these specified ranges during operation will
help to ensure that the integrity of the TC90A80N/F is not compromised. When
designing video equipment, be aware that the TC90A80N/F can function within
the recommended operating ranges.
11
2002-12-04
TC90A80N/F
Electrical Characteristics
DC Characteristics
2
(Ta = 25°C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C BUS: according to test
conditions)
Characteristics
Pin
No.
Pin
Name
Symbol
Min
Typ.
Max
Unit
I2C bus setup
2
I C bus setup
Power supply
Test Conditions (Remarks)
DATA1 DATA2 DATA3
00
00
00
DATA4
00
3, 12,
13,
20, 23
VDD
IDD
60
85
105
mA
1
BIAS
V1
0.9
1.3
1.7
V
2
VRT
V2
3.02
3.16
3.30
V
• Input signal : Not apply to pins 4, 7, and 9.
4
CIN
V4
2.4
2.5
2.6
V
• Test content : Measure the DC voltage of those pins.
6
VRB
V6
1.69
1.83
1.97
V
7
YIN
V7
1.69
1.83
1.97
V
9
YCIN
V9
1.72
1.86
2.00
V
19
FSC
V19
2.00
2.45
2.90
V
22
FIL
V22
1.8
3.0
4.2
V
24
VB2
V24
3.0
3.4
3.8
V
25
YOUT
V25
2.37
2.5
2.63
V
27
COUT
V27
3.52
3.7
3.88
V
28
VB1
V28
1.2
1.6
2.0
V
Pin voltage
• Input signal : Apply NTSC color bar at 1-Vp-p to pin 9.
• Test content : Measure the total current of power
supply pins 3, 12, 13, 20, and 23.
I2C bus setup
I2C bus setup
VIML
VSS
ʊ
1.0
V
00
40
00
00
00
02
00
00
• Input signal : Apply NTSC color bar at 1-Vp-p to pin 9.
• Test content : Apply DC voltage to pin 11 and measure
the DC voltage change at the following
points.
VIML : Normal operation
3-level input
voltage
11: KIPVIN
VIMM
1.8
ʊ
2.8
V
VIMM : Stops Y/C separation (drives out composite
video signal to pin 25).
VIMH : Receives PV
(drives out High (VOH) to pin 17).
VIMH
3.6
ʊ
VDD
V
Operations of VIMM and VIMH are inverted by DATA3 D2
= 1 of the I2C bus settings.
To support high-speed pulse input, the circuit must have
no hysteresis
I2C bus setup
VIH
4
ʊ
VDD
V
VIL
VSS
ʊ
1
V
8 : TEST
2-level input
voltage
14 : CSYNCIN
15 : SCL
16 : SDA
00
02
00
00
• Test content : Apply DC voltage to pins 8, 14, 15, and
16. Change the DC voltage and check
the point where High/Low level is applied
to those pins by monitoring the DC
change on pins 17 and 18. Measure the
input bottom voltage of the pins 8, 14, 15
and 16.
VIH : Apply reset signal, composite sync signal, I2C bus
High level.
VIL : Apply reset signal, composite sync signal, I2C bus
Low level.
12
2002-12-04
TC90A80N/F
VOH
4.6
ʊ
VDD
V
I2C bus setup
2
I C bus setup
00
00
00
00
00
02
00
00
• Test content : Measure the output voltage on pins 17
and 18 when DC is applied with a 4.7-kȍ
resistor.
17: HDPVOUT
18: MODE1
VOL
VSS
ʊ
0.4
V
Output voltage
VOH : Connects a 4.7-kȍ resistor between pin 17/18
and GND.
VOL : Connects a 4.7-kȍ resistor between pin 17/18
and VDD.
I2C bus setup
16
SDA
VACK
VSS
ʊ
0.4
V
00
00
00
00
• Test content : Measure the ACK output voltage when
DC is applied with a 4.7-kȍ resistor.
Connect a 4.7-kȍ resistor between pin 16 and VDD.
13
2002-12-04
TC90A80N/F
AC Characteristics
Luminance signal input/output characteristics
2
(Ta = 25°C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C bus: according to test conditions)
Characteristics
Symbol
Min
Typ.
Max
Unit
I2C bus setup
Test Conditions (Remarks)
DATA1 DATA2 DATA3
2
Recommended input level
VYIN
ʊ
1.0
1.3
V
I C bus setup
GY
5.5
6.0
6.5
dB
00
00
00
• Input signal : Apply white 100% signal to pins 7 and 9.
I2C bus setup
Low-frequency gain
00
DATA4
00
00
00
00
• Input signal : Apply white 100% signal at 1-Vp-p to pin
9.
• Test content : Compare pin 25 output level with pin 9
input level.
I2C bus setup
Comb characteristic
Ycom
40
45
ʊ
dB
í2
í1
0
dB
Differential error
L
í1
0
+1
LSB
(reference value)
Integral error
B
í3
0
+3
LSB
(reference value)
I2C bus setup
Zy
250
400
ȍ
700
00
00
00
00
00
00
• Input signal : Apply 1-Vp-p, 2.5-V DC offset sine
wave to pin 9.
• Test content : Monitor pin 25 in Killer Mode. Change
input frequency. Measure gain
difference between 0.5 MHz and 3
MHz.
FY
Output impedance
00
• Input signal : Apply 1-Vp-p, 2.5-V DC offset sine
wave to pin 9.
• Test content : Monitor pin 25. Change input frequency.
Measure gain difference between
3.51678 MHz and 3.579545 MHz.
I2C bus setup
Frequency characteristic
00
00
00
00
00
• Input signal : Input 1-Vp-p, 15-kHz square wave to
pin 9.
• Test content : Calculate output impedance, AC
applied with/without 300-ȍ resistor
connected between pin 25 and GND.
I2C bus setup
Fundamental clock leakage
L1fy
ʊ
0.3
1.0
L4fy
ʊ
4
ʊ
L8fy
ʊ
20
ʊ
00
00
00
00
00
00
mVrms • Input signal : No input to pin 9.
• Test content : Measure 4 fsc (14.31818 MHz)
component of pin 25.
I2C bus setup
Clock leakage 2
00
mVrms • Input signal : No input to pin 9.
• Test content : Measure fsc (3.579545 MHz)
component of pin 25.
I2C bus setup
Clock leakage 1
00
00
00
00
00
mVrms • Input signal : No input to pin 9.
• Test content : Measure 8 fsc (28.63636 MHz)
component of pin 25.
14
2002-12-04
TC90A80N/F
Chrominance signal input/output characteristics
2
(Ta = 25°C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C bus: according to test conditions)
Characteristics
Symbol
Min
Typ.
Max
Unit
Test Conditions (Remarks)
I2C bus setup DATA1 DATA2 DATA3 DATA4
I2C bus setup
Recommended input level
VCIN
ʊ
1.0
1.3
V
2
I C bus setup
GC
4.5
5.2
5.8
dB
00
00
00
• Input signal : Apply chroma 100% signal to pin 4.
(To pin 4, chrominance signal only;
to pin 9, composite video signal)
I2C bus setup
Chrominance signal gain
80
00
00
00
00
80
00
00
00
• Input signal : Apply chroma 100%, 0.714-Vp-p
signal to pins 4 and 9. (To pin 4,
chrominance signal only; to pin 9,
composite video signal)
• Test content : Compare pin 27 output level with
input level.
I2C bus setup
Comb characteristic
Ccom
35
40
ʊ
dB
00
00
00
00
• Input signal : Apply 0.714-Vp-p, 2.5-V DC offset
sine wave to pin 9.
• Test content : Monitor pin 27. Change input
frequency. Measure gain difference
between 3.57168 MHz and
3.579545 MHz.
I2C bus setup
80
00
00
00
• Input signal : Apply 0.714-Vp-p sine wave to pin 4.
BWC
í0.5
í0.2
0
dB
Differential gain
DG
0
2
5
%
Differential phase
DP
0
2
5
°
BPF frequency characteristic
• Test content : Monitor pin 27. Change input
frequency. Measure gain difference
between 3.579545 MHz and
3.079545 MHz.
I2C bus setup
Zc
250
400
700
ȍ
L1fc
ʊ
0.3
1.0
L4fc
ʊ
4
ʊ
L8fc
ʊ
20
ʊ
15
80
00
00
00
00
00
00
00
mVrms • Input signal : No input to pin 9.
• Test content : Measure fsc (3.579545 MHz)
component of pin 27.
00
00
00
00
mVrms • Input signal : No input to pin 9.
• Test content : Measure 4fsc (14.31818 MHz)
component of pin 27.
I2C bus setup
Clock leakage 2
00
• Input signal : Apply 1-Vp-p chroma 100% signal to
pin 4.
• Test content : Calculate output impedance, AC
applied with/without 300-ȍ resistor
connected between pin 27 and
GND.
I2C bus setup
Clock leakage 1
00
• Test content : Monitor pin 27 using vector scope
(p-p value).
I2C bus setup
Fundamental wave clock
leakage
00
• Input signal : Apply 1-Vp-p, 5-step staircase (0 =
40 IRE) to pin 9.
I2C bus setup
Output impedance
00
00
00
00
00
mVrms • Input signal : No input to pin 9.
• Test content : Measure 8fsc (28.63636 MHz)
component of pin 27.
2002-12-04
TC90A80N/F
YNR Characteristics
2
(Ta = 25°C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C bus: according to test conditions)
Characteristics
Symbol
Min
Typ.
Max
Unit
Test Conditions (Remarks)
I2C bus setup DATA1 DATA2 DATA3 DATA4
I2C bus setup
Y comb characteristic 1
YNRW1
ʊ
í23
í20
80
00
08
FC
• Input signal : Apply 71.3 mVp-p, 2.5-V DC offset
sine wave to pin 7.
dB
• Test content : Monitor pin 25.
Change input frequency. Measure
gain difference between 629.36 kHz
and 621.493 kHz.
I2C bus setup
80
00
08
FD
• Input signal : Apply 71.4 mVp-p, 2.5-V DC offset
sine wave to pin 7.
Y comb characteristic 2
YNRN1
ʊ
í20
í17
dB
• Test content : Monitor pin 25.
Change input frequency. Measure
gain difference between 629.36 kHz
and 621.493 kHz.
I2C bus setup
80
00
08
FE
• Input signal : Apply 71.4 mVp-p, 2.5-V DC offset
sine wave to pin 7.
Y comb characteristic 3
YCOBW1
ʊ
í9
í7
dB
• Test content : Monitor pin 25.
Change input frequency. Measure
gain difference between 629.36 kHz
and 621.493 kHz.
I2C bus setup
80
00
08
FF
• Input signal : Input 71.4 mVp-p, 2.5-V DC offset
sine wave to pin 7.
Y comb characteristic 4
YCOBN1
ʊ
í12
í10
dB
• Test content : Monitor pin 25.
Change input frequency. Measure
gain difference between 629.36 kHz
and 621.493 kHz.
CNR Characteristic
2
(Ta = 25°C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C bus: according to test conditions)
Characteristics
Symbol
Min
Typ.
Max
Unit
Test Conditions (Remarks)
I2C bus setup DATA1 DATA2 DATA3 DATA4
I2C bus setup
C comb characteristic
CNR
ʊ
í14
í12
16
80
FC
00
00
• Input signal : Apply 71.4 mVp-p, 2.5-V DC offset
sine wave to pin 4.
dB
• Test content : Monitor pin 27.
Change input frequency. Measure
gain difference between 3.579545
MHz and 3.571678 MHz.
2002-12-04
TC90A80N/F
PLL characteristic
2
(Ta = 25°C, VDD = 5.00 V, clock input: according to test conditions, I C bus: according to test
conditions)
Characteristics
Symbol
Min
Typ.
Max
Unit
Test Conditions (Remarks)
2
I C bus setup
2
I C bus setup
Pull-in frequency range
ǻfckN
±100
ʊ
ʊ
kHz
DATA1 DATA2 DATA3 DATA4
00
00
00
00
• Clock input : Change input frequency at 0.5 Vp-p.
• Test content : Change input frequency with fsc
(3.579545 MHz) as reference and
measure pull-in range for PLL.
I2C bus setup
00
00
00
00
• Clock input : Change input amplitude at fsc
(3.579545 MHz).
• Test content : Increase input clock amplitude from
0 Vp-p and measure input amplitude
for PLL.
I2C bus setup
Operating input amplitude 1
Vck
0.3
0.5
2.0
Vp-p
01
00
00
00
• Clock input : Change input amplitude at 2 fsc
(7.15909 MHz).
• Test content : Increase input clock amplitude from
0 Vp-p and measure input amplitude
for PLL.
I2C bus setup
02
00
00
00
• Clock input : Change input amplitude at 4 fsc
(14.31818 MHz).
• Test content : Increase input clock amplitude from
0 Vp-p and measure input amplitude
for PLL.
I2C bus setup
03
00
00
00
• Input signal : Apply 10-kHz, 1-Vp-p triangular
wave to pin 9.
Operating input amplitude 2
Vck8
0.5
1.0
2.0
Vp-p
• Clock input : Change input amplitude at 8 fsc
(28.63636 MHz).
• Test content : Increase input clock amplitude from
0 Vp-p and measure input amplitude
where pin 25 output stabilizes.
17
2002-12-04
TC90A80N/F
HD Reference Characteristics
2
(Ta = 25°C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C bus: according to test conditions)
Characteristics
Symbol
Min
Typ.
Max
Unit
Test Conditions (Remarks)
2
I C bus setup
2
I C bus setup
HD output pulse width
HDW
ʊ
4.4
ʊ
µs
DATA1 DATA2 DATA3 DATA4
40
00
00
00
• Input setting : pin 11 = 0 V, pin 14 = 0 V
• Test content : Measure HD pulse width of pin 17.
I2C bus setup
HD free-running frequency
HDF
ʊ
15.734
ʊ
kHz
40
00
00
00
• Input setting : pin 11 = 5 V, pin 14 = 0 V
• Test content : Measure HD frequency of pin 17.
I2C bus setup
HD pull-in frequency range
HDPU
ʊ
±280
ʊ
Hz
40
00
00
00
• Input setting : Set pin 11 to 0 V, and apply pulse
signal whose High period is 4 µs
and amplitude is 5 V (increase from
0 V to 5 V) to pin 14. Change input
frequency.
• Test content : Change input frequency with fh
(15.734 kHz) as reference and
measure pull-in range where HD
frequency of pin 17 locks to the input
frequency.
I2C bus setup
Minimum input sync pulse width
HD
ʊ
300
ʊ
ns
40
00
00
00
• Input setting : Set pin 11 to 0 V, and apply fh
(15.734 kHz) pulse signal whose
amplitude is 5 V (increase from 0 V
to 5 V) to pin 14. Change High
period of input pulse.
• Test content : Increase input pulse width from
50 ns and measure input pulse width
where HD frequency of pin 17 locks
to fh.
18
2002-12-04
TC90A80N/F
VDD2 23
SW4
FIL 22
8 TEST
VSS5 21
9 YCIN
VDD5 20
10 VSS3
FSC 19
C.SYNC IN
1
13 VDD4
+5 V (digital)
SDA 16
SW7
R32
4.7 kȍ
SDA
SCL 15
14 CSYNCIN
R65
300 ȍ
C64 0.1 µF
R64
1.8 kȍ
TP27
Mode1
HD + PV OUT
HD + PV
OUT
SDA
SCL
R34
4.7 kȍ
TP19
1
SW8 3
1
SW9 3
2
Q32
RN1203
SCL
Measuring
equipment
GND
Clock
input
Mode1
R33
4.7 kȍ
Q31
RN1203
TP14
2
TP18
HD
PVOUT 17
C14
47 µF
2
fsc-IN
TP17
12 VDD3
1
SW6
SW12
Clock
GND
C15 0.01 µF
TP16
MODE1 18
2
+5 V (PLL)
TP15
C11
TP09
0.01 µF
11 KIPVIN
C13
0.01 µF TP11
Killer
PV IN
2 Y/C-IN
C12
47 µF
SW5
Video
-GND
C10
0.47 µF
1
R62
820 ȍ
+5 V R05
(DAC) 330 ȍ
2
Video IN
2
Measuring
equipment
C65
47 µF
6 VRB
SW12
Q62
L61 27 µH
R63 1 kȍ
VB2 24
1
C61 12 pF
5 VSS1
7 YIN
TP07
1
YOUT 25
R61 820 ȍ
4 CIN
2
Reset IN
2
SW10
Y-OUT
C06 0.01 µF
3
2.5 V DC
1
C61 22 pF
R31 SW3
1
20 kȍ
Q61
C22 0.01 µF
C21 Open
Y-GND
1
C18
C17 680 pF
100 µF C19 0.1 µF
Y-IN
2
2
C16
0.1 µF
SW2
SW11
1
VSS2 26
C20
0.1 µF TP25
1
COUT 27
3 VDD1
C08
0.47 µF
Y-IN
2 VRT
C02
0.01 µF
C-OUT
TP22
C-IN
2
VB1 28
1 BIAS
C01
0.01 µF
C03
TP04 0.1 µF
SW1
C-GND
+5 V (ADC)
1
C05
0.1 µF
C-IN
C04 100 µF
TC90A80N/F
C63
10 µF
C32
0.1 µF
GND
C23 0.01 µF
+5 V
C31
220 µF
<Power>
Test Circuit
2
R35
4.7 kȍ
SW Control Table
Measuring characteristic (symbol)
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9 SW10 SW11 SW12
Supply current
1
1
3
2
1
2
2
3
3
2
1
1
Pin voltage
2
2
3
2
2
2
2
3
3
2
1
1
3-level input voltage
1
1
3
2
1
1
2
3
3
2
1
1
2-level input voltage
1
1
3
1
1
2
1
3
3
2
1
1
Output voltage
1
1
3
2
1
2
1
1, 2
1, 2
2
1
1
Low-frequency gain
1
1
3
2
1
2
2
3
3
2
1
1
Comb characteristic (Ycom)
1
1
2
2
1
2
2
3
3
2
1
1
1
Frequency characteristic
1
1
2
2
1
1
2
3
3
2
1
Output impedance (Zy)
1
1
3
2
1
2
2
3
3
2
1, 2
2
Fundamental wave clock leakage (L1fy)
2
2
3
2
2
2
2
3
3
2
1
1
Chrominance signal gain
1
1
3
2
1
2
2
3
3
1
1
1
Comb characteristic (Ccom)
1
1
2
2
1
2
2
3
3
1
1
1
BPF frequency characteristic
1
1
3
2
1
2
2
3
3
1
1
1
Output impedance (Zc)
1
1
3
2
1
2
2
3
3
1
1, 2
2
Fundamental wave clock leakage (L1fc)
2
2
3
2
2
2
2
3
3
1
1
1
Y comb frequency characteristic 1, 2, 3, 4
1
1
1
2
1
2
2
3
3
2
1
1
CNR characteristic
1
1
3
2
1
2
2
3
3
1
1
1
PLL characteristic (3 items)
1
1
3
2
1
2
2
3
3
2
1
1
HD reference characteristic (4 items)
1
1
3
2
1
1
1
3
3
2
1
1
I2C bus control characteristic
1
1
3
2
1
2
2
3
3
2
1
1
19
2002-12-04
TC90A80N/F
TC90A80N/F Application Circuit
(evaluation board)
L01 22 µH
NC
SDA (pin 06)
to PC
(PRT) SCL (pin 05)
GND (pin 25)
TP14
4
3
2
1
Q36
RN1203
NPN Tr: 2SC2458Y or equivalent
PNP Tr: 2SA1048Y or equivalent
14 CSYNCIN
SCL 15
C85 47 µF
R92 C86
75 ȍ 470 µF
R90
100 ȍ
R87
820 ȍ
R86 1.2 kȍ
C84 0.1 µF
R91 1/4W
220 ȍ
R89 560 ȍ
R88 12 kȍ
R84 6.8 kȍ
R85 560 ȍ
C82 12 pF
C81 22 pF
C21
Open
C19
0.1 µF
VR5
1 kB
(550)
Q85
C-GND
C17
100 µF
C18
680 pF
R83 1.2 kȍ
C22
0.01 µF
fsc1
HD + PV
OUT
SW6
SDA
fsc2
VR4 2 kB
Mode1
R54 12 kȍ
C-OUT
L05 47 µH
C46 47 µF
TP25
C20
0.1 µF
TP22
C16
0.1 µF
TP19
Q84
R72
C66
75 ȍ 0.1 µF
R67
820 ȍ
R66 1.2 kȍ
C65 47 µF
L82
22 µH
Y C
C15 0.01 µF
SCL
Q83
Q4
Q5
S-OUT (to TV)
Y-GND
C50
15 pF
C47
0.01 µF
R53 1.5 kȍ
SDA 16
Q65
L33
27 µH
C48 10 pF
13 VDD4
C64 0.1 µF
R71 1/4W
220 ȍ
R69 560 ȍ
R68 12 kȍ
R64 6.8 kȍ
R65 560 ȍ
R63 1.2 kȍ
C62 12 pF
C61 22 pF
R61 820 ȍ
C23
0.01 µF
TP27
R70
100 ȍ
R52 5.6 kȍ
HDPVOUT 17
C.SYNC IN
R02
220 ȍ
VR6
1 kB
(550)
R51 1 kȍ
12 VDD3
TP81
C83
47 µF Q82
C45 0.01 µF
MODE1 18
Q81
R82 L81
820 ȍ 27 µH
fsc-IN
TP18
FSC 19
+5 V (PLL)
TP17
10 VSS3
Y-OUT
R55
510 ȍ
fsc1
PLL
GND
fsc2
fsc2
D-GND
Mode1
R49
10 kȍ
C.SYNC IN
Nor.
VDD5 20
R48
10 kȍ
Killer/PV IN
R04
3.3 kȍ
9 YCIN
11 KIPVIN
Q64
R56 C49 33 pF
75 ȍ
+5 V (digital)
VSS5 21
TP16
L03
100 µH
PV
Killer
R01
220 ȍ
C03
TP04 0.1 µF
L02
100 µH
FIL 22
+5 V R05
(DAC) 330 ȍ
TP15
R03
3.9 kȍ
Y/C-IN
C13
0.01 µF
SW5
C11
TP11 0.01 µF TP09
L04
bead
Y/C-Input Level
Video-GND
C10
0.47 µF
C09
Non
SW3
Nor.
LPF
R45
820 ȍ
VR3
1 kB
(520)
8 TEST
Nor.
TP33
Q35
C44 47 µF
C43 0.1 µF
Q34
YOUT 25
VDD2 23
7 YIN
Q63
+9 V
Y-OUT
4 CIN
6 VRB
C06 0.01 µF
SW4
C63
0.1 µF Q62
VSS2 26
VB2 24
TP07
C07
Non
C08
0.47 µF
3 VDD1
C-OUT
5 VSS1
TEST
R44 1.2 kȍ
R42 6.8 kȍ
R43 560 ȍ
R41 1.2 kȍ
C42
47 µF Q33
C41 15 pF
C40 22 pF
R39 75 ȍ
R40 L32
820 ȍ 18 µH
R47 560 ȍ
R46 12 kȍ
Video IN
COUT 27
Y-IN
+9 V
C39
12 pF
2 VRT
C02 0.01 µF
TP61
R81 820 ȍ
S-IN
Video IN
VB1 28
C04
100 µF
+5 V (ADC)
C05 0.1 µF
TP31
Nor.
S-IN
C-IN
SW2
1 BIAS
C01 0.01 µF
C12
47 µF
Y-GND
Q32
C14
47 µF
Y-Input Level
+9 V
L31
47 µH
Y-IN
Q61
R62 L61
820 ȍ 27 µH
SW1
TP32
R36 2.2 kȍ
VR2
2 kB
C38
220 µF
R35
1.5 kȍ
C-Input Level
C-GND
+9 V
TC90A80N/F
R38
1.5 kȍ
C-IN
Q31
R34 2.2 kȍ
VR1
2 kB
C37
0.1 µF
R37 2.2 kȍ
R32
75 ȍ
R33 2.2 kȍ
+9 V
(form VTR)
R50 1 kȍ
R31
75 ȍ
C36 0.01 µF
Y C
S-IN
L62 22 µH
C35 47 µF
C33
C34
220 µF 0.1 µF
Nor.
+9 V
C32
0.1 µF
GND
C52
0.1 µF
GND
C31
220 µF
<Power>
+5 V
C51
220 µF
Application Circuit Example
HD + PV
OUT
Q37
RN1203
20
2002-12-04
TC90A80N/F
Package Dimensions
Weight: 1.7 g (typ.)
21
2002-12-04
TC90A80N/F
Package Dimensions
Weight: 0.8 g (typ.)
22
2002-12-04
TC90A80N/F
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
23
2002-12-04