Si2356DS Datasheet

Si2356DS
Vishay Siliconix
N-Channel 40 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
40
RDS(on) () Max.
ID
(A)a
0.051 at VGS = 10 V
4.3
0.054 at VGS = 4.5 V
4.1
0.070 at VGS = 2.5 V
3.6
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• Material categorization:
For definitions of compliance please see
www.vishay.com/doc?99912
Qg (Typ.)
3.8 nC
APPLICATIONS
TO-236
(SOT-23)
G
•
•
•
•
1
3
S
DC/DC Converter
Load Switch
LED Backlighting
Power Management
D
D
G
2
Top View
S
Si2356DS (E9)*
N-Channel MOSFET
* Marking Code
Ordering Information:
Si2356DS-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Drain-Source Voltage
Symbol
VDS
Limit
40
Gate-Source Voltage
VGS
± 12
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)
TC = 70 °C
3.4
ID
TA = 25 °C
3.2 a,b
2.6 a,b
IDM
Pulsed Drain Current (t = 100 µs)
TC = 25 °C
20
IS
TA = 25 °C
0.8 a,b
1.7
TC = 70 °C
1.1
PD
TA = 25 °C
W
0.96 a,b
0.62 a,b
TA = 70 °C
Operating Junction and Storage Temperature Range
A
1.4
TC = 25 °C
Maximum Power Dissipation
V
4.3
TA = 70 °C
Continuous Source-Drain Diode Current
Unit
TJ, Tstg
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient a,c
t5s
Symbol
RthJA
Typical
100
Maximum
130
Maximum Junction-to-Foot (Drain)
Steady State
RthJF
60
75
Unit
°C/W
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 5 s.
c. Maximum under steady state conditions is 175 °C/W.
Document Number: 62893
S13-1814-Rev. A, 12-Aug-13
For technical questions, contact: [email protected]
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2356DS
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 250 µA
40
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS/TJ
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
VGS(th)/TJ
Gate-Source Threshold Voltage
ID = 250 µA
VGS(th)
VDS = VGS , ID = 250 µA
Gate-Source Leakage
IGSS
VDS = 0 V, VGS = ± 12 V
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
Forward Transconductancea
V
43
mV/°C
- 3.8
0.6
1.5
V
± 100
nA
VDS = 40 V, VGS = 0 V
1
VDS = 40 V, VGS = 0 V, TJ = 55 °C
10
VDS 5 V, VGS = 10 V
10
µA
A
VGS 10 V, ID = 3.2 A
0.042
0.051
RDS(on)
VGS 4.5 V, ID = 3.1 A
0.045
0.054
VGS 2.5 V, ID = 2 A
0.056
0.070
gfs
VDS = 15 V, ID = 3.2 A
13

S
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
370
VDS = 20 V, VGS = 0 V, f = 1 MHz
tr
td(off)
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
VDS = 20 V, VGS = 10 V, ID = 3.2 A
0.72
VDS = 20 V, VGS = 4.5 V, ID = 3.2 A
nC
0.81
f = 1 MHz
VDD = 20 V, RL = 7.7 
ID  2.6 A, VGEN = 10 V, Rg = 1 
0.2
0.7
1.4
6
12
12
20
13
20
6
12
10
20
VDD = 20 V, RL = 7.7 
ID  2.6 A, VGEN = 4.5 V, Rg = 1 
tf
Fall Time
13
5.7
tf
td(off)
Turn-Off Delay Time
8.1
3.8
td(on)
tr
Rise Time
pF
17
td(on)
Turn-On Delay Time
Rise Time
50
52
78
18
27
53
80

ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulse Diode Forward Current (t = 100 µs)
ISM
Body Diode Voltage
VSD
TC = 25 °C
1.4
20
IS = 2.6 A, VGS 0 V
0.8
1.2
A
V
Body Diode Reverse Recovery Time
trr
12
20
ns
Body Diode Reverse Recovery Charge
Qrr
5
10
nC
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
IF = 2.6 A, dI/dt = 100 A/µs, TJ = 25 °C
8.5
3.5
ns
Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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For technical questions, contact: [email protected]
Document Number: 62893
S13-1814-Rev. A, 12-Aug-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2356DS
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
5
20
VGS = 10 V thru 3 V
VGS = 2.5 V
4
TC = 25 °C
ID - Drain Current (A)
ID - Drain Current (A)
15
10
VGS = 2 V
3
2
TC = 125 °C
5
1
TC = - 55 °C
0
0
0
0.5
1
1.5
2
0
1
Output Characteristics
Transfer Characteristics
0.07
510
408
0.06
VGS = 2.5 V
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
2
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
0.05
VGS = 4.5 V
0.04
VGS = 10 V
Ciss
306
204
102
Coss
Crss
0
0.03
0
5
10
15
20
0
10
ID - Drain Current (A)
20
On-Resistance vs. Drain Current and Gate Voltage
40
Capacitance
1.9
10
VGS = 10 V, 3.2A
ID = 3.2 A
VDS = 20 V
RDS(on) - On-Resistance (Normalized)
VGS - Gate-to-Source Voltage (V)
30
VDS - Drain-to-Source Voltage (V)
8
VDS = 10 V
6
4
VDS = 32 V
2
0
1.55
VGS = 4.5 V, 3.1A
VGS = 2.5 V, 2A
1.2
0.85
0.5
0
2.2
4.4
6.6
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 62893
S13-1814-Rev. A, 12-Aug-13
8.8
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
For technical questions, contact: [email protected]
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2356DS
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
0.120
10
RDS(on) - On-Resistance (Ω)
IS - Source Current (A)
ID = 3.2A
TJ = 150 °C
TJ = 25 °C
1
0.100
0.080
TJ = 125 °C
0.060
TJ = 25 °C
0.040
0.020
0.000
0.1
0.0
0.3
0.6
0.9
0
1.2
2
4
6
8
10
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
30
1.4
ID = 250 μA
1.22
Power (W)
VGS(th) (V)
20
1.04
0.86
10
0.68
0.5
- 50
- 25
0
25
50
75
100
125
150
0
0.001
0.01
0.1
1
10
100
Time (s)
TJ - Temperature (°C)
Threshold Voltage
Single Pulse Power (Junction-to-Ambient)
100
ID - Drain Current (A)
10
Limited by RDS(on)*
100 μs
1
1 ms
10 ms
0.1
100 ms
10s, 1 s
DC,
0.01
TA = 25 °C
Single Pulse
0.001
0.1
BVDSS Limited
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
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For technical questions, contact: [email protected]
Document Number: 62893
S13-1814-Rev. A, 12-Aug-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2356DS
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
4.8
ID - Drain Current (A)
3.6
2.4
1.2
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
Current Derating*
2
0.9
0.72
Power (W)
Power (W)
1.5
1
0.54
0.36
0.5
0.18
0
0
0
25
50
75
100
125
150
0
25
50
75
100
125
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power Junction-to-Foot
Power Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 62893
S13-1814-Rev. A, 12-Aug-13
For technical questions, contact: [email protected]
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2356DS
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
PDM
0.05
t1
0.02
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 175 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse
0.01
10 -4
4. Surface Mounted
10 -3
10 -2
10 -1
1
100
10
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62893.
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For technical questions, contact: [email protected]
Document Number: 62893
S13-1814-Rev. A, 12-Aug-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SOT-23 (TO-236): 3-LEAD
b
3
E1
1
E
2
e
S
e1
D
0.10 mm
C
0.004"
A2
A
C
q
Gauge Plane
Seating Plane
Seating Plane
C
A1
Dim
0.25 mm
L
L1
MILLIMETERS
Min
INCHES
Max
Min
Max
0.044
A
0.89
1.12
0.035
A1
0.01
0.10
0.0004
0.004
A2
0.88
1.02
0.0346
0.040
b
0.35
0.50
0.014
0.020
c
0.085
0.18
0.003
0.007
D
2.80
3.04
0.110
0.120
E
2.10
2.64
0.083
0.104
E1
1.20
1.40
0.047
e
0.95 BSC
e1
L
1.90 BSC
0.40
L1
q
0.0748 Ref
0.60
0.016
0.64 Ref
S
0.024
0.025 Ref
0.50 Ref
3°
0.055
0.0374 Ref
0.020 Ref
8°
3°
8°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
Document Number: 71196
09-Jul-01
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AN807
Vishay Siliconix
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
ambient air. This pattern uses all the available area underneath the
body for this purpose.
0.114
2.9
0.081
2.05
0.150
3.8
0.059
1.5
0.0394
1.0
0.037
0.95
FIGURE 1. Footprint With Copper Spreading
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
Document Number: 70739
26-Nov-03
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
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Application Note 826
Vishay Siliconix
0.049
(1.245)
0.029
0.022
(0.559)
(0.724)
0.037
(0.950)
(2.692)
0.106
RECOMMENDED MINIMUM PADS FOR SOT-23
0.053
(1.341)
0.097
(2.459)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index Return to Index
APPLICATION NOTE
Document Number: 72609
Revision: 21-Jan-08
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Revision: 02-Oct-12
1
Document Number: 91000