ST7538
POWER LINE FSK TRANSCEIVER
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HALF DUPLEX FREQUENCY SHIFT KEYING
(FSK) TRANSCEIVER
INTEGRATED POWER LINE DRIVER WITH
PROGRAMMABLE VOLTAGE AND CURRENT
CONTROL
PROGRAMMABLE INTERFACE:
– SYNCHRONOUS
– ASYNCHRONOUS
SINGLE SUPPLY VOLTAGE (FROM 7.5 UP TO 12.5V)
VERY LOW POWER CONSUMPTION (Iq=5 mA)
INTEGRATED 5V VOLTAGE REGULATOR
(UP TO 100mA) WITH SHORT CIRCUIT
PROTECTION
8 PROGRAMMABLE TRANSMISSION
FREQUENCIES
TQFP44 Slug Down
ORDERING NUMBER: ST7538P
■
WATCHDOG TIMER
DESCRIPTION
The ST7538 is a Half Duplex synchronous/asynchronous FSK Modem designed for power line
communication network applications. It operates
from a single supply voltage and integrates a line
driver and a 5V linear regulator. The device operation is controlled by means of an internal register,
programmable through the synchronous serial interface. Additional functions as watchdog, clock
output, output voltage and current control, preamble detection, time-out, band in use are included.
Realized in Multipower BCDV technology that allows to integrate DMOS, Bipolar and CMOS structures in the same chip.
PROGRAMMABLE BAUD RATE UP TO 4800BPS
RECEIVING SENSITIVITY 1 mVRMS
SUITABLE TO APPLICATION IN ACCORDANCE
WITH EN 50065 CENELEC SPECIFICATIONS
CARRIER OR PREAMBLE DETECTION
BAND IN USE DETECTION
PROGRAMMABLE REGISTER WITH
SECURITY CHECKSUM
MAINS ZERO CROSSING DETECTION AND
SYNCHRONIZATION
BLOCK DIAGRAM
DVdd
AVdd
DVss
AVss
TEST1 TEST2 TEST3
BU
TEST
BU
CARRIER
DETECTION
CD/PD
RxFo
AGC
RxD
CLR/T
DIGITAL
FILTER
PLL
FSK
DEMOD
IF
FILTER
FILTER
AMPL
RAI
SERIAL
INTERFACE
FILTER
CONTROL
REGISTER
REG/DATA
CURRENT
CONTROL
CL
VOLTAGE
CONTROL
Vsense
RxTx
FSK
MODULATOR
TxD
DAC
TX
FILTER
ALC
REGOK
ATO
PLI
TIME BASE
OSC
ZC
OP-AMP
ATOP1
ATOP2
+
PAVcc
VREG
-
Vdc
PG
XOut
September 2003
XIn
WD
TOUT
RSTO
MCLK
ZCin
ZCout
C_OUT
CMINUS
CPLUS
D03IN1407
1/30
ST7538
N.C.
REG_DATA
PG
GND
C_OUT
N.C.
C_PLUS
C_MINUS
REG_OK
TEST1
N.C.
PIN CONNECTION (Top view)
44
43
42
41
40
39
38
37
36
35
34
TEST2
TXD
5
29
VSENSE
GND
6
28
AVDD
TOUT
7
27
XIN
CLR/T
8
26
XOUT
BU
9
25
SGND
DVDD
10
24
ATO
MCLK
11
23
CL
12
13
14
15
16
17
18
19
20
21
22
PAVCC
30
ATOP2
4
PAVSS
RXFO
RxTx
ATOP1
31
DVSS
3
N.C.
RAI
RXD
ZCIN
32
ZCOUT
VDC
2
WD
33
DVSS
RSTO
1
TEST3
CD_PD
D01IN1312
PIN DESCRIPTION
N°
Name
1
CD_PD
2
3
Type
Description
Digital/Output
Carrier or Preamble Detect Output.
"1" No Carrier or Preamble Detected
"0" Carrier or Preamble Detected
DVss
Supply
Digital Ground
RxD
Digital/Output
RX Data Output.
4
RxTx
Digital/Input
with internal pull-up
Rx or Tx mode selection input.
"1" - RX Session
"0" - TX Session
5
TxD
Digital/Input
with internal pull-down
TX Data Input.
6
GND
Supply
Substrate Ground (same function as PIN 41)
7
TOUT
Digital/Output
TX Time Out Event Detection
"1" - Time Out Event Occurred
"0" - No Time-out Event Occurred
8
CLR/T
Digital/Output
Synchronous Mains Access Clock or
Control Register Access Clock
9
BU
Digital/Output
Band in use Output.
"1" Signal within the Programmed Band
"0" No Signal within the Programmed Band
10
DVdd
Supply
Digital Supply Voltage
11
MCLK
Digital/Output
Master Clock Output
12
RSTO
Digital/Output
Power On or Watchdog Reset Output
13
TEST 3
Digital/Input
with internal pull-down
Test Input. Must be connected to DVss during Normal Operation
2/30
ST7538
PIN DESCRIPTION (continued)
N°
Name
14
WD
15
16
17
Type
Description
Digital/Input
with internal pull-up
Watchdog input. The Internal Watchdog Counter is cleared on the
falling edges.
ZCOUT
Digital/Output
Zero Crossing Detection Output
ZCIN1
Analog/Input
Zero Crossing AC Input.
NC
Floating
Must be connected to DVss.
18
DVss
Supply
Digital Ground
19
ATOP1
Power/Output
Power Line Driver Output
20
PAVss
Supply
Power Analog Ground
21
ATOP2
Power/Output
Power Line Driver Output
22
PAVCC
Supply
Power Supply Voltage
23
CL2
Analog/Input
Current Limiting Feedback.
A resistor between CL and AVss sets the PLI Current Limiting Value
24
ATO
Analog/Output
Small Signal Analog Transmit Output
25
SGND
Supply
Analog Signal Ground
26
XOUT
Analog I/O
Crystal Output- External Clock Input
27
XIN
Analog Input
Crystal Oscillator Input
28
AVdd
Supply
Analog Power supply.
Vsense
Analog/Input
Output Voltage Sensing input for the voltage control loop
30
TEST2
Analog/Input
Test Input must be connected SGND
31
RxFO
Analog/Output
Receiving Filter Output
32
RAI
Analog/Input
Receiving Analog Input
33
VDC
Power
5V Voltage Regulator Output
34
NC
floating
Must Be connected to DVss.
35
TEST1
Digital/Input
with internal pull-down
Test input. Must Be connected to DVss.
36
REGOK
Digital/Output
Security checksum logic output
"1" - Stored data Corrupted
"0" - Stored data OK
29
3
37
C_MINUS4 Analog/Input
38
C_PLUS5
39
NC
40
C_OUT
41
GND
42
PG
43
44
<1>
<2>
<3>
<4>
<5>
Analog/Input
Op-amp Not Inverting Input.
floating
Must Be connected to DVss
Analog/Output
Op-amp Output
Supply
Substrate Ground (same function as PIN 6)
Digital/Output
Power Good logic Output
"1" - VDC is above 4.5V
"0" - VDC is below 4.25V
REG_DATA Digital/Input
with internal pull-down
NC
Op-amp Inverting Input.
floating
Mains or Control Register Access Selector
"1" - Control Register Access
"0" - Mains Access
Must be connected to DVss.
If not used this pin must be connected to VDC
Cannot be left floating
Cannot be left floating
If not used this pin must be connected to VDC
If not used this pin must be tied low (SGND or PAVss or DVss)
3/30
ST7538
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
-0.3 to +14
V
PAVCC
Power Supply Voltage
AVdd
Analog Supply Voltage
-0.3 to +5.5
V
DVdd
Digital Supply Voltage
-0.3 to +5.5
V
AVss/DVss
-0.3 to +0.3
V
Digital input Voltage
DVss - 0.3 to DVdd +0.3
V
VO
Digital output Voltage
DVss - 0.3 to DVdd +0.3
V
IO
Digital Output Current
VI
Vsense
Voltage between AVss and DVss
Voltage Range at Vsense Input
-2 to +2
mA
AVss - 0.3 to AVdd+0.3
V
-AVdd - 0.3 to AVdd +0.3
V
RAI
Voltage Range at RAI Input
ATO
Output Current at ATO Output
-2 to +2
mA
ATO
Voltage range at ATO Output
AVss - 0.3 to AVdd +0.3
V
AVss - 0.3 to +PAVcc +0.3
V
ATOP
Powered ATO Output Current
400
mARms
Tamb
Operating ambient Temperature
-40 to +85
°C
Tstg
Storage Temperature
-50 to 150
°C
±1500
V
±1000
V
±2000
V
ATOP1,2
ATOP1 Pin
ATOP2 Pin
Other pins
Voltage range at Powered ATO Output
Maximum Withstanding Voltage Range
Test Condition: CDF-AEC-Q100-002- “Human Body Model”
Acceptance Criteria: “Normal Performance”
THERMAL DATA
TQFP44
with slug
Unit
Maximum Thermal Resistance Junction-Ambient Steady State(*)
35
°C/W
Maximum Thermal Resistance Junction-Ambient Steady State(**)
50
°C/W
Symbol
Parameter
Rth-j-amb1
Rth-j-amb2
(*) Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB
(**) It's the same condition of the point above, without any heatsinking surface on the board.
4/30
ST7538
ELECTRICAL CHARACTERISTCS
(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, unless otherwise specified)
Symbol
AVCC,
DVCC
Parameter
Test Condition
Supply Voltages
Min.
Typ.
Max.
Unit
4.75
5
5.25
V
PAVCC - DVCC PAVCC and DVCC Relation
during Power-Up Sequence
DVCC < 4.75V
0.1
1.2
V
PAVCC - AVCC PAVCC and DVCC Relation
during Power-Up Sequence
AVCC < 4.75V
0.1
1.2
V
7.5
12.5
V
10
V/ms
7
mA
PAVcc
Power Supply Voltage
Max allowed slope during
Power-Up
AICC + DICC
I PAVCC
Input Supply Current
Powered Analog Supply
Current
Transmission & Receiving mode
5
TX mode (no load)
30
50
mArms
RX mode
500
1000
µA
370
mArms
Maximum total current
Digital I/O
VIH
High Logic Level Input Voltage
2
VIL
Low Logic Level input Voltage
VOH
High Logic Level Output Voltage IOH= -2mA
VOL
Low Logic Level Output Voltage IOL= 2mA
V
0.8
3.5
V
V
0.4
V
Oscillator
VIHX
XIN High Level Input Voltage
External Clock
VILX
XIN Low Level Input Voltage
External Clock
DC
XTAL Clock Duty Cycle
External Clock
Xtal
Crystal Oscillator frequency
3
V
2
40
60
V
%
16
MHz
62.5
ns
Tclock
Oscillator Period (1/Xtal)
XtalESR
External Oscillator Esr
Resistance
40
Ohm
External Oscillator Stabilization
Capacitance
16
pF
XtalCL
Transmitter
IATOP
VATO
Output Transmitting Current in
programmable current limiting
Vsense connected though a
100pF cap to GND; Rcl=1.85kΩ;
RLOAD =1Ω (as in fig. 13)
Max Carrier Output AC Voltage RCL = 1.85kΩ Vsense=0V
250
310
370
mArms
1.75
2.3
3.5
VPP
VATODC
Output DC Voltage on ATO
2.1
2.5
V
HD2ATO
Second Harmonic Distortion on
ATO
VATO = 2VPP; Fc=86KHz
1.7
-55
-42
dB
HD3ATO
Third Harmonic Distortion on
ATO
VATO = 2VPP; Fc=86KHz
-52
-49
dB
VATOP(AC)
Max Carrier Output AC Voltage
for each ATOP1 and ATOP2
pins
RCL = 1.85kΩ
Vsense=0V
VAT OP ( A C)
PAVcc ≥ ------------------------------------ + 7.5V
2
3.5
4.6
6
Vpp
VATOP(DC)
Output DC Voltage on ATOP1
and ATOP2 pins
3.5
4.2
5
V
5/30
ST7538
ELECTRICAL CHARACTERISTCS (continued)
(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, unless otherwise specified)
Symbol
Parameter
HD2ATOP
Second Harmonic Distortion on
each ATOP1 and ATOP2 pins
HD3ATOP
VATOP
GST
DRNG
Third Harmonic Distortion on
each ATOP1 and ATOP2 pins
Accuracy with Voltage Control
Loop Active
Test Condition
Typ.
Max.
Unit
VATOP = 4VPP
No Load
-55
-42
dB
VATOP = 4VPP
RLOAD =50Ω (Differential)
Carrier Frequency: 132.5KHz
-65
-53
dB
VATOP = 4VPP
No Load.
-56
-49
dB
VATOP = 4VPP
RLOAD =50Ω (Differential)
Carrier Frequency: 132.5KHz
-65
-52
dB
+1
GST
1.4
dB
210
mVPK
RCL = 0Ω
ALC Gain Step Control loop
gain step
Min.
-1
0.6
1
170
190
ALC Dynamic Range
30
dB
Voltage control loop reference
threshold on Vsense pin
Figure 13
Hysteresis on Voltage loop
reference threshold
Figure 13
Current control loop reference
threshold on Csense pin
Figure 13
1.80
1.90
2.00
V
CCLHYST
Hysteresis on Voltage loop
reference threshold
Figure 13
210
250
290
mV
VSENSE
VSENSE Input Impedance
Figure 16 - 600 Baud Xtal=16MHz
0.01
1.6
ms
Figure 16- 1200 Baud
Xtal=16MHz
0.01
800
µs
Figure 16- 2400 Baud
Xtal=16MHz
0.01
400
µs
Figure 16- 4800 Baud
Xtal=16MHz
0.01
200
µs
VCLTH
VCLHYST
CCLTH
TRxTx
TALC
TST
Carrier Activation Time
+-19
mV
36
KΩ
Carrier Stabilization Time
From STEP 16 to zero or From
step 16 to step 31,
Figure 16.
Xtal =16MHz
3.2
ms
Tstep
Figure 16
Xtal =16MHz
200
µs
2
mVrms
Receiver
VIN
Input Sensitivity (Normal Mode)
1
Input Sensitivity (High Sens.)
VIN
Maximum Input Signal
RIN
Input Impedance
VCD
VBU
6/30
µVrms
500
2
Vrms
100
140
kΩ
Carrier Detection Sensitivity
(Normal Mode)
1
2
mVrms
Carrier Detection Sensitivity
(High Sensitivity Mode)
500
Band in Use Detection Level
77
80
µVrms
85
dB/
µVrms
ST7538
ELECTRICAL CHARACTERISTCS (continued)
(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
-25<Tj<125 C
0<Io<100mA
4.9
5.05
5.2
V
-25<Tj<125 C
0<Io<150mA
4.7
5.2
V
Voltage Regulator
VDC
Linear Regulator Output
Voltage
Line Regulation
7.5V<PAVcc<12.5V
Idc=10mA
10
50
mV
Load Regulation
5mA<Idc<100mA
Vin=7.5V
20
75
mV
I(VDC)
Linear Regulator Current
Limitation
150
180
210
V
UVLO
Input Under Voltage Lock Out
Threshold
3.7
3.9
4.1
V
UVLOHYS
PG
PGHYS
UVLO Hysteresis
340
Power Good Output Voltage
Threshold on VDC pin
4.3
PG Hysteresis
4.5
mV
4.7
250
V
mV
Other Functions
TRSTO
Reset Time
See Figure 18; Xtal=16MHz
50
TWD
Watch-dog Pulse Width
See Figure 18
3.5
TWM
Watch-dog Pulse Period
See Figure 18
TWD +
3.5
TWO
Watch-dog Time Out
See Figure 18
TOUT
TX TIME OUT
Control Register Bit 7 and Bit 8
See Figure 17
TOFF
TOFFD
TCD
Time Out OFF Time
See Figure 17
RxTx 0->1 vs. TOUT Delay
See Figure 17
Carrier Detection Time
selectable by register
Control Register
bit 9 and bit10
Figure 10
ms
ms
1490
1.5
1
3
ms
s
s
125
ms
20
µs
ms
ms
ms
500
1
3
5
CD_PD Propagation Delay
Figure 10
Master Clock Output
Selectable by register
Control Register
bit 15 and bit 16
see table 6
fclock
fclock/2
fclock/4
Baud rate
Control Register
bit 3 and bit 4
see table 6
600
1200
2400
4800
Baud
Baud rate Bit Time (=1/BAUD)
Control Register
bit 3 and bit 4
see table 6
1667
833
417
208
µs
TB
500
µs
TDCD
MCLK
BAUD
300
µs
MHz
Zero Crossing Detection
ZCDEL
Zero Crossing Detection delay
(delay between the ZCIN and
ZCOUT signals)
Figure 19
1
µs
7/30
ST7538
ELECTRICAL CHARACTERISTCS (continued)
(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
ZC(LOW)
Zero Crossing Detection Low
Threshold
-45
-5
mV
ZC(HIGH)
Zero Crossing Detection High
Threshold
5
+45
mV
-20
+20
mV
45
mA
ZC(OFFSET) Zero Crossing Offset
Operational Amplifier
COUT(Sync)
Max Sync Current
COUT(Source) Max Source Current
15
28
-30
-20
CIN(Offset)
Input Terminals OFFSET
-38
GBWP
Gain Bandwidth Product
6
7
-10
mA
+38
mV
9
MHz
Serial Interface
Ts
Setup Time
see figure 3, 5, 6, 7 & 8
5
ns
TH
Hold Time
see figure 3, 5, 6, 7 & 8
2
ns
TCR
CLR/T vs. REG_DATA or RxTx
see figure 3, 5, 6, 7 & 8
TB/4
TCC
CLR/T vs. CLR/T
see figure 3, 5, 6, 7 & 8
TB
2*TB
TDS
Setup Time
see figure 3, 5, 6, 7 & 8
TB/4
TB/2
TDH
Hold Time
see figure 3, 5, 6, 7 & 8
TB/4
TB/2
TH
TB/2
TCRP
8/30
see figure 4
ST7538
FUNCTIONAL DESCRIPTION
Carrier Frequencies
ST7538 is a multi frequency device: eight programmable Carrier Frequencies are available (see table 1).
Only one Carrier could be used a time. The communication channel could be varied during the normal
working Mode to realize a multifrequency communication.
Selecting the desired frequency in the Control Register the Transmission and Reception filters are accordingly tuned.
Table 1.
FCarrier
F0
F1
F2
F3
F4
F5
F6
F (KHz)
60
66
72
76
82.05
86
110
132.5
F7(1)
Baud Rates
ST7538 is a multi Baud rate device: four Baud Rate are available (See table 2).
Table 2.
Baud Rate [Baud]
600
∆F (2)(Hz)
600
1200
600
1200
2400(1)
1200(1)
2400
2400
4800
4800
Note: 1.
2.
3.
4.
Deviation (3)
1(4)
0.5
1
0.5
1
0.5
1
Default value
Frequency deviation.
Deviation = ∆F / (Baud Rate)
Deviation 0.5 Not Allowed
9/30
ST7538
Mark and Space Frequencies
Mark and Space Communication Frequencies are defined by the following formula:
F ("0") = FCarrier + [∆F]/2
F ("1") = FCarrier - [∆F]/2
∆F is the Frequency Deviation.
With Deviation = “0.5” the difference in terms of frequency between the mark and space tones is half the
Baudrate value (∆F=0.5*BAudrate). When the Deviation = “1” the difference is the Baudrate itself (∆F=
Baudrate). The minimal Frequency Deviation is 600Hz.
Table 3.
Carrier
Frequency
(KHz)
Baud
Rate
Deviation
60
600
-1
1200
2400
66
72
“0”
59733
60221
59733
60221
1
59408
60547
0.5
59408
60547
1
58757
61198
4800
0.5
58757
61198
1
57617
62337
600
-1
65755
66243
1200
0.5
65755
66243
1
65430
66569
2400
0.5
65430
66569
1
64779
67220
4800
0.5
64779
67220
1
63639
68359
71777
72266
600
1200
2400
10/30
“1”
0.5
Carrier
Frequency
(KHz)
Baud
Rate
Deviation
82.05
600
-1
1200
2400
86
-1
76
Exact Frequency [Hz]
(Clock=16MHz)
110
0.5
71777
72266
1
71452
72591
0.5
71452
72591
1
70801
73242
4800
0.5
70801
73242
1
69661
74382
600
-1
75684
76335
1200
0.5
75684
76335
1
75358
76660
2400
0.5
75358
76660
1
74870
77148
4800
0.5
74870
77148
1
73568
78451
“1”
“0”
81706
82357
0.5
81706
82357
1
81380
82682
0.5
81380
82682
1
80892
83171
4800
0.5
80892
83171
1
79590
84473
600
-1
85775
86263
1200
0.5
85775
86263
1
85449
86589
2400
0.5
85449
86589
1
84798
87240
4800
0.5
84798
87240
1
83659
88379
109701
110352
600
-1
1200
2400
132.5
Exact Frequency [Hz]
(Clock=16MHz)
0.5
109701
110352
1
109375
110677
0.5
109375
110677
1
108724
111165
4800
0.5
108724
111165
1
107585
112467
600
-1
132161
132813
1200
0.5
132161
132813
1
131836
133138
2400
0.5
131836
133138
1
131348
133626
4800
0.5
131348
133626
1
130046
134928
ST7538
Host Processor Interface
ST7538 exchanges data with the host processor thorough a serial interface.
The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged using RxD, TxD
and CLR/T lines.
Four are the ST7538 working modes:
Data Reception
■
■
Data Transmission
■
Control Register Read
■
Control Register Write
REG_DATA and RxTx lines are level sensitive inputs.
Table 4.
REG_DATA
RxTx
Data Transmission
0
0
Data Reception
0
1
Control Register Read
1
1
Control Register Write
1
0
■
Mains Access
ST7538 features two type of communication interfaces:
- Asynchronous
- Synchronous
The selection can be done through the internal Control Register.
Figure 1.
Asynchronous
Data Interface
Host Controller
Synchronous
Data Interface
RxD
RxD
TxD
TxD
RxTx
RxTx
CLR/T
CLR/T
REG_DATA
REG_DATA
ST7538
Host Controller
ST7538
D03IN1415
– Asynchronous Mode.
ST7538 allows to interface the Host Controller using a 3 line interface (RXD,TXD & RxTx).
Data are exchange without any auxiliary Clock reference in an Asynchronous mode without adding any
protocol bits. The host controller has to recover the clock reference in receiving Mode and control the Bit
time in transmission mode. RxD line is forced to a low logic level when no carrier is detected.
11/30
ST7538
– Synchronous mode.
St7538 allows to interface the host Controller using a four lines synchronous interface (RXD,TXD, CLR/T
& RxTx). ST7538 is always the master of the communication and provides the clock reference on CLR/T
line.
When ST7538 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are
stable on CLR/T rising Edge.
When ST7538 is in transmitting mode the clock reference is internally generated and data are read on TxD
line on CLR/T rising Edge.
If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7538 enters in an Idle State and CLR/T
line is forced Low. After Tcc time the modem starts providing received data on RxD line.
If RxTx line is set to “0” & REG_DATA=”0” (Data Transmission), ST7538 d in an Idle State and transmission
circuitry is switched on. (figure 3). After Tcc time the modem starts transmitting data present on TXD line
(figure 3) .
Figure 2.
Receiving Bit Synchronization
Transmitting Bit Synchronization
CLR/T
CLR/T
RxD
TxD
TS
TH
D03IN1416
Figure 3. Data Reception -> Data Transmission -> Data reception
TCC
TCC
CLR_T
TB
TDS
TDH
RXD
REG_DATA
TCR
TCR
RxTx
TS
TXD
TH
BIT23
BIT22
D03IN1402
PACKET MODE (Only for Reception)
In Packet mode data transmission from ST7538 to Host Controller is done at a higher speed than the
Mains one. This function could reduce the efficiency of data exchange process because the Host Controller is involved in data reception for a shorter period of time.
To achieve this function is enabled an internal auxiliary buffer which stores the incoming bits. The buffer
is transferred to the host controller when full at the packet rate. The packet rate is programmable and is
related to the Mclk clock frequency. The length of the packet can be also programmed through the control
register (see table 9) to be 16, 14, 9 or 8 bits.
The packet mode to start working needs two levels of enable. One at the control register level the other at
the pin level. TxD is the pin that if forced High enables the Packet Mode Function. According to when TxD
is forced high, the next incoming bit is stored inside the internal buffer or delivered on RxD pin. If TxD pin
is forced low during a RX session the transceiver starts working in bit mode and the content of the packet
buffer is deleted.
12/30
ST7538
Figure 4. Packet Mode Timing
CLR_T
TDS
TDH
RXD
IDLE
IDLE
IDLE
TCRP
TXD
D03IN1406
CLR_T
RXD
Control Register Access
The communication with ST7538 Control Register is always synchronous. The access is achieved using
the same lines of the Mains interface (RxD, TxD and CLR/T) plus REG_DATA Line.
With REG_DATA = 1 and RxTx=0, the data present on TxD are loaded into the Control Register MSB first.
The ST7538 sampled the TxD line on CLR/T rising edges. The control Register content is updated at the
end of the register access section (REG_DATA falling edge). If more than 24 bits are transferred to
ST7538 only the latest 24 bits are stored inside the Control Register.
With REG_DATA = 1 and RxTx=1, the content of the Control Register is sent on RxD port. The Data on
RxD are stable on CLR/T rising edges MSB First.
13/30
ST7538
Figure 5. Data Reception
➨
Control Register read ➨ Data Reception Timing Diagram
TCC
TCC
CLR_T
TDS
TDH
TDS
RXD
TDH
TB
BIT23
BIT22
TCR
REG_DATA
TCR
RxTx
D03IN1404
Figure 6. Data Reception
➨
Control Register write
➨
Data Reception Timing Diagram
TCC
TCC
CLR_T
TDS
TDH
TB
RXD
TCR
TCR
REG_DATA
TCR
TCR
RxTx
TS
TXD
TH
BIT23
BIT22
D03IN1403
Figure 7. Data Transmission ➨ Control Register read ➨ Data Reception Timing Diagram
TCC
TCC
CLR_T
TB
TDS
RXD
BIT23
TDH
TDH
BIT22
TCR
REG_DATA
TDS
TCR
TCR
RxTx
TS
TH
TXD
D03IN1405
Figure 8. Data Transmission ➨ Control Register Write ➨ Data Reception Timing Diagram
TCC
TCC
CLR_T
TB
TS
TXD
TH
BIT23
TS
TH
BIT22
TCR
REG_DATA
TCR
TCR
RxTx
TDS
TDH
RXD
D03IN1401
14/30
ST7538
Receiving Mode
The receive section is active when RxTx Pin =”1” and REG_DATA=0.
The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered by a Band pass
Filter (+-10KHz). The Pre-Filter can be removed setting one bit in the Control Register. The Input Stage
features a wide dynamic range to receive Signal with a Very Low Signal to Noise Ratio. The Amplitude of
the applied waveform is automatically adapted by an Automatic Gain Control block (AGC) and then filtered
by a Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (+-6K). The resulting signal is down-converted by a mixer using a sinewave generated by the FSK Modulator. Finally an
Intermediate Frequency Band Pass-Filter (IF Filter) improves the Signal to Noise ration before sending the
signal to the FSK demodulator. The FSK demodulator then send the signal to the RX Logic for final digital
filtering. Digital filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal
Jitter. RxD Line is forced at logic level “0” when neither mark or space frequencies are detected on RAI Pin.
Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have a correct demodulation.
While ST7538 is in Receiving Mode (RxTx pin =”1”), the transmit circuitry, Power Line Interface included,
are turned off. This allows the device to achieve a very low current consumption (5 mA typ). In Receiving
mode ATOP2 pin is internally connected to PAVSS.
■ High Sensitivity Mode
It is possible to increase ST7538 Receiving Sensitivity setting to “1” the High Sensitivity Bit of Control
Register. This Function allows to increase the communication reliability when the ST7538 sensitivity is
the limiting factor.
■
Synchronization Recovery System (PLL)
ST7538 embeds a Clock Recovery System to feature a Synchronous data exchange with the Host
Controller.
The clock recovery system is realized by means of a second order PLL. Data on the data line (RxD) are
stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD line transitions ± LOCK-IN
Range).
The PLL Lock-in and Lock-out Range is ±π/2. When the PLL is in the unlock condition, CLR/T and RxD
lines are forced to a low logic level.
When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The maximum number
of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive
only to RxD rising Edges to reduce the CLR/T Jitter.
ST7538 PLL is forced in the un-lock condition, when more than 32 equal symbols are received.
Figure 9.
CLR/T
RxD
D03IN1417
LOCK-IN RANGE
15/30
ST7538
■
Carrier/Preamble Detection
The Carrier/Preamble Block is a digital Frequency detector Circuit.
It can be used to manage the MAINS access and to detect an incoming signal.
Two are the possible setting:
- Carrier Detection
- Preamble Detection
CARRIER DETECTION: The Carrier/Preamble detection Block notifies to the host controller the
presence of a Carrier when it detects on the RAI Input a signal with an harmonic component close to
the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception
sensitivity (1mVrms Typ. in Normal Sensitivity Mode).
The CD_PD line is forced to a logic level low when a Carrier is detected.
PREAMBLE DETECTION: The Carrier/Preamble detection Block notifies to the host controller the
presence of a Carrier modulated at the Programmed Baud Rate for at least 4 Consecutive Symbols
(“1010” or “0101” are the symbols sequences detected).
CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range.
To reinforce the effectiveness of the information given by CD_PD Block, a digital filtering is applied on
Carrier or Preamble notification signal (See Control Register Paragraph). The Detection Time Bits in the
Control Register define the filter performance. Increasing the Detection Time reduced the false
notifications caused by noise on main line. The Digital filter adds a delay to CD_PD notification equal to
the programmed Detection Time. When the carrier frequency disappears, CD_PD line is held low for a
period equal to the detection time and then forced high.
Figure 10. CD_PD Timing during RX
TDCD
TCD
CD_PD
RAI
D03IN1418
Figure 11. Receiving Path Block Diagram
RXFO
31
Bit 3,4
Bit 0-2
Bit 3,4
3
Bit 3,4 &14-21
8
PLL
Low Pass
DIGITAL
FILTER
Bit 9 & 10
1
CD_PD
Low Pass
9
BU
32
AGC
RxD
CLR/T
Bit 23
MIXER
FSK
DEMODULAOR
Bit 12 & 13
CARRIER/
PREAMBLE
DETECTION
Band Pass
Band Pass
IF FILTER
CHANNEL
FILTER
LOCAL
OSC
Band Pass
PRE-FILTER
GAIN
CONTROL
Bit 0 -2
Carrier Detection
BAND
IN
USE
D03IN1419
16/30
RAI
ST7538
Transmission Mode
The transmit mode is set when RxTx Pin =”0” and REG_DATA Pin =”0”. In transmitting mode the FSK Modulator and the Power Line Interface are turned ON. The transmit Data (TXD) enter synchronously or asynchronously to the FSK modulator.
– Host Controller Synchronous Communication Mode: on CLR/T rising edge, TXD Line Value is read and
sent to the FSK Modulator. ST7538 Manage the Transmission timing according to the BaudRate Selected
– Host Controller Asynchronous Communication Mode: TXD data enter directly to the FSK Modulator.The
Host Controller Manages the Transmission timing
In both conditions no Protocol Bits are added by ST7538.
The FSK frequencies are synthesized in the FSK modulator from a 16 MHz crystal oscillator by direct digital synthesis technique. The frequencies Table in different Configuration is reported in Table 3. The frequencies precision is same as external crystal one’s.
In the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the
harmonic distortion. The transition between a symbol and the following is done at the end of the on-going
half FSK sinewave cycle.
Figure 12.
Bit 7 & 8
TIMER
VOLTAGE
LOOP
29
THERMAL
SENSOR
CURRENT
LOOP
23
Vsense
7
TOUT
Bit 14
Bit 0-5
Bit 0-2
5
TxD
CL
ALC
DAC
PLI
19
ATOP1
Band Pass
D-TYPE
FLIP
FLOP
FSK
MODULATOR
TRANSMISSION
FILTER
PLI
8
CLR/T
ZERO CROSSING
15
ZCOUT
PLI
21
24
ATOP2
ATO
CLR/T GENERATOR
16
ZCIN
D03IN1420
17/30
ST7538
■
Automatic Level Control (ALC)
The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear discrete steps)
controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB to 30 dB and
the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ).
Two are the control loops acting to define the ALC gain:
- A Voltage Control loop
- A Current Control Loop
The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense. The gain
adjustment is related to the result of a peak detection between the Voltage waveform on Vsense and
two internal Voltage references.
- If Vsense < VCLTH - VCLHYST
- If VCLTH - VCLHYST < Vsense < VCLTH + VCLHYST
- If Vsense > VCLTH + VLC HYST
The next gain level is increased by 1 step
No Gain Change
The next gain level is decreased by 1 step
The Current control loop acts to limit the maximum Peak Output current inside ATOP1 and ATOP2.
The current control loop acts through the voltage control loop decreasing the Output Peak-to-Peak
Amplitude to reduce the Current inside the Power Line Interface.
The current sensing is done by mirroring the current in the High side MOS of the Power Amplifier (not
dissipating current Sensing). The Output Current Limit (up to 400mApeak), is set by means of an
external resistor (RCL) connected between CL and PAVss. The resistor converts the current sensed into
a voltage signal. The Peak current sensing block works as the Output Voltage sensing Block:
- If V(CL) < CCL TH - CCLHYST
- If CCLTH - CCLHYST < V(CL) < CCLTH + CCLHYST
- If V(CL) > CCL TH + CLCHYST
Voltage Control Loop Acting
No Gain Change
The next gain level is decreased by 1 step
Figure 13 shows the typical connection of Current anVoltage control loops.
Figure 13. Voltage and Current Feedback external interconnection Example
ATOP/ATO
ALC
VRPK
Vout
R1
VOLTAGE
LOOP
Vsense
5.6nF
VCLHYST
R2
VCLTH
CURRENT
LOOP
RCL
100pF
AVss
D03IN1421
Voltage Control Loop Formula
R1 + R2
VR PK ≅ -------------------- ⋅ ( V CLT H ± VCL HY ST )
R2
18/30
1.865V (Typ)
CL
CCLHYST
CCLTH
ST7538
Table 5. Vout vs. R1 & R2 resistors value
Vout (Vrms)
Vout (dBµV)
(R1+R2)/R2
R2 (KΩ)
R1 (KΩ)
0.150
103.5
1.1
7.5
1.0
0.250
108.0
1.9
5.1
3.9
0.350
110.9
2.7
3.6
5.6
0.500
114.0
3.7
3.3
8.2
0.625
115.9
4.7
3.3
11.0
0.750
117.5
5.8
2.7
12.0
0.875
118.8
6.6
2.0
11.0
1.000
120.0
7.6
1.6
10.0
1.250
121.9
9.5
1.6
13.0
1.500
123.5
10.8
1.6
15.0
Notes: The rate of R2 takes in account the input resistance on the SENSE pin (36 KΩ).
5.6nF capacitor effect has been neglected.
Figure 14. Typical Output Current vs. Rcl
Irms
(mA)
D01IN1311
325
300
275
250
225
200
175
150
125
100
■
2
2.5
3
3.5
4
4.5
5
Rcl(KΩ)
Integrated Power Line Interface (PLI)
The Power Line Interface (PLI) is a double CMOS AB Class Power Amplifier with the two outputs
(ATOP1 and ATOP2) in opposition of phase.
Two are the possible configuration:
- Single Ended Output (ATOP1).
- Bridge Connection
The Bridge connection guarantee a Differential Output Voltage to the load with twice the swing of each
individual Output. This topology virtually eliminates the even harmonics generation.
The PLI requires, to ensure a proper operation, a regulated and well filtered Supply Voltage. PAVcc
Voltage must fulfil the following formula to work without clipping phenomena:
( AC )- + 7.5V
PAVcc ≥ VATOP
----------------------------------2
To allow the driving of an external Power Line Interface, the output of the ALC is available even on ATO
pin. ATO output has a current capability much lower than ATOP1 and ATOP2.
19/30
ST7538
Figure 15. PLI Bridge Topology
VRPK
ATOP2
INVERTER
2*VRPK
LOAD
ATOP1
ALC
Vout
R1
VRPK
Vsense
VOLTAGE
LOOP
5.6nF
R2
CL
CURRENT
LOOP
RCL
100pF
PAVss
D03IN1422
Figure 16. PLI Startup Timing Diagram
RX/TX
TALC
TRXTX
TST
4V
ATOP2
0V
STEP NUMBER 16
17
18
31
D03IN1408
20/30
ST7538
Control Register
The ST7538 is a multi-channel and multifunction transceiver. An internal 24 Bits Control Register allows
to manage all the programmable parameters (table 5).
The programmable functions are:
■ Channel Frequency
■
Baud Rate
■
Deviation
■
Watchdog
■
Transmission Timeout
■
Frequency Detection Time
■
Zero Crossing Synchronization
■
Detection Method
■
Mains Interfacing Mode
■
Output Clock
■
Packet Mode Baudrate
■
Packet Length
■
Packet Enable
■
Input Pre-Filter
■
Sensitivity Mode
21/30
ST7538
Table 6. Control Register Functions
Function
0 to 2
Value
Frequencies
60 KHz
66 KHz
72 KHz
76 KHz
82.05 KHz
86 KHz
110 KHz
132.5 KHz
3 to 4
Baud Rate
600
1,200
2,400
4,800
5
Selection
Bit2
Bit1
Bit0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 4
Bit 3
0
0
1
1
0
1
0
1
Deviation
0
1
Watchdog
9 to 10
11
22/30
Transmission
Time Out
Frequency
detection time
Zero Crossing
Synchronization
132.5 kHz
2400
0.5
Bit 6
Disabled
Enabled (1.5 s)
7 to 8
Default
Bit 5
0.5
1
6
Note
Disabled
1s
3s
Not Used
500 µs
1 ms
3 ms
5 ms
0
1
Enabled
Bit 8
Bit 7
0
0
1
1
0
1
0
1
Bit 10
Bit 9
0
0
1
1
0
1
0
1
1 sec
1 ms
Bit 11
Disabled
Enabled
0
1
Disabled
ST7538
Table 6. Control Register Functions (continued)
Function
12 to 13
Detection
Method
Value
Selection
Note
Default
Preamble
detection
without
conditioning
Bit 13
Bit 12
Carrier detection
without conditioning
0
0
Carrier Detection
Notification on CD_PD Line
CLR/T and RxD signal
always Present
Carrier detection
with conditioning
0
1
CLR/T and RxD lines are
forced to “0” when Carrier
is not detected
Preamble detection
without conditioning
1
0
Preamble Detection
Notification on CD_PD Line
CLR/T and RxD signal
always Present
Preamble detection
with conditioning
1
1
Preamble Detection
Notification on CD_PD Line
CLR/T and RxD lines are
forced to “0” when
Preamble has not been
detected or PLL is in
Unlock condition
Bit 14
14
15 to 16
17 to 18
19 to 20
Mains
Interfacing
Mode
Output Clock
Packet Mode
Baud Rate
Packet Length
Synchronous
Asynchronous
16 MHz
8 MHz
4 MHz
Not Used
Mclk/32
Mclk/64
Mclk/128
Mclk/256
8 Bit
9 Bit
14 Bit
16 Bit
0
1
Asynchronous
Bit 16
Bit 15
0
0
1
1
0
1
0
1
Bit 18
Bit 17
0
0
1
1
0
1
0
1
Bit 20
Bit 19
0
0
1
1
0
1
0
1
4 MHz
MLCK/64
14 bits
Bit 21
21
Packet Mode
Enable
Disabled
Enabled
0
1
Disabled
Bit 22
22
Sensitivity
Mode
Normal Sensitivity
High Sensitivity
0
1
Normal
Bit 23
23
Input Filter
Disabled
Enabled
0
1
Disabled
23/30
ST7538
AUXILIARY ANALOG AND DIGITAL FUNCTIONS
Band In Use
The Band in Use Block has a Carrier Detection like function but with a different Input Sensibility (77dBµV
Typ.)
and with a different BandPass filter Selectivity (40dB/Dec).
BU line is forced High when a signal in band is detected.
To prevent BU line false transition, BU signal is conditioned to Carrier Detection Internal Signal.
Time Out
Time Out Function is a protection against a too long data transmission. When Time Out function is enabled
after 1 or 3 second of continuos transmission the transceiver is forced in receiving mode. This function
allows ST7538 to automatically manage the CENELEC Medium Access specification. When a time-out
event occur, TOUT is forced high, and is held high for at least 125 ms. To Unlock the Time Out condition
RxTx should be forced High. During the time out period only register access or reception mode are enabled.
During Reset sequence if RxTx line =”0” & REG_DATA line =”1”, TIMEOUT protection is suddendly enabled and ST7538 must be configured in data reception after the reset event before starting a new data
transmission.
Time Out time is programmable using Control Register bits 7 and 8 (table 6).
Figure 17. Time-out Timing and Unlock Sequence
RxTx
TOUT
TOFF TOFFD
TOUT
D03IN1409
Reset & Watchdog
RSTO Output is a reset generator for the application circuitry. During the ST7538 startup sequence is
forced low. RSTO becomes high after a TRSTO delay from the end of oscillator startup sequence.
Inside ST7538 is also embedded a watchdog function. The watchdog function is used to detect the occurrence of a software fault of the Host Controller. The watchdog circuitry generates an internal and external
reset (RSTO low for TRSTO time) on expiry of the internal watchdog timer. The watchdog timer reset can
be achieved applying a negative pulse on WD pin Fig 18.
Figure 18. Reset and Watchdog Timing
TRSTO
TWO
RSTO
TRSTO
TWM
TWD
WD
D03IN1410
24/30
ST7538
Zero Crossing Detection
The Mains Voltage Zero Crossing can be detected, through a proper connection of ZCIN to the Mains.
ZCIN comparator has a threshold fixed at SGND. ZCOUT is a TTL Output forced High after a positive
zero-crossing transition, and low after a negative one.
Setting the Bit 11 inside the Control Register to “1” the transmission is automatically synchronized to the
mains positive zero-crossing transition. This function is achieved turning on the PLI when RX/TX is low
and delaying the CLR/T first transition until the first zero-crossing event. The automatic synchronization
procedure can work only if the synchronous interface is programmed. If asynchronous interface is in use
the Zero Crossing synchronization can be achieved managing the ZCOUT line.
Figure 19. Synchronous Zero-Crossing Transmission
ZCIN
t
RxTx
CLR/T
TxD
ZCDEL
ZCOUT
D03IN1423
Output Clock
MCLK is the master clock output. The clock frequency sourced can be programed through the control register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4). The transition between one frequency and another is done only at the end of the ongoing cycle.
Reg OK
REGOK allows to detect an undesired modification of the control register content. REGOK function is disabled during a control register writing session.
Under Voltage Lock Out
The UVLO function turns off the device if the PAVdd voltage falls under 4V. Hysteresis is 340mV typically.
Thermal Shutdown
The ST7538 is provided of a thermal protection which turn off the PLI when the junction temperature exceeds 170°C ±10% . Hysteresis is around 30°C.
When shutdown threshold is overcome, PLI interface is switched OFF.
Thermal Shutdown event is notified to the HOST controller using TIMEOUT line. When TIMEOUT line is
High, ST7538 junction temperature exceed the shutdown threshold (Not Lached).
5V Voltage Regulator and Power Good Function
ST7538 has an embedded 5V linear regulator externally available to supply the application circuitry.
The linear regulator has a very low quiescent current (50µA) and a current capability of 100mA. The regulator is protected against short circuitry events.
When the regulator Voltage is above the power good threshold (VPG), Power Good line is forced high,
while is forced low at startup and when VDC falls below VPG - VPGHYS Voltage.
25/30
ST7538
Figure 20. Power Good Function
VDC
4.5V
250mV
Time
PG
PG OK
D03IN1411
Time
Power-Up Procedure
To ensure ST7538 proper power-Up sequence, PAVcc, AVss and DVss Supply has to fulfil the following
rules:
PAVcc rising slope must not exceed 10V/ms.
When DVdd and AVdd are below 5V: 100mV < PAVcc-AVdd , PAVcc-DVdd < 1.2V.
When AVdd and DVdd supply are connected to VDC the above mentioned relation is guarantied if VDC
load < 100mA and if the filtering capacitor on VDC < 100uF.
Figure 21. Power-UP Sequence
Voltage
5V
PAVcc
DVdd, AVdd
PAVcc-AVdd
PAVcc-DVdd
D03IN1424
Time
PACKAGE INFORMATION
Best thermal performance is acheived when slug is soldered to PCB.
It is recomended to have five solder dots (See fig. 22) without resist to connect the Copper slug to the
ground layer on the soldering side. Moreover it is recomeded to connect the ground layer on the soldering
side to another ground layer on the opposite side with 15 to 20 vias.
It is suggested to not use the PCB surface below the slug area to interconnect any pin except groung pins.
26/30
HOST
CONTROLLER
5V Supply
for Host Controller
Clock & Reset for
Host Controller
12
11
43
8
4
5
3
1
15
9
7
36
42
14
35
30
13
10
28
20
N.C.
DVSS
33 44
N.C.
PAVSS
RSTO
MCLK
5 Lines
Serial Interface
REG/DATA
CLR/T
RX/TX
TxD
RxD
CD/PD
ZCOUT
BU
TOUT
REGOK
PG
WD
TEST1
TEST2
TEST3
DVdd
AVdd
VDC
18
34
N.C.
17
DVSS
2
GND
ST7538
N.C.
39
6
GND
SGND
41
25
26
27
16
31
23
29
19
32
24
21
XOUT
XIN
ZCIN
RxFO
RCL
CL
Vsense
ATOP1
RAI
ATO
ATOP2
C1
C_MINUS
C_PLUS
37
C_OUT
38
PAVCC
40
22
C2
R2
R1
D03IN1412
Voltage
Regulation
&
Current
Protection
LOAD
Zero Crossing
Transmission
Synchronization
No External Components
for POWER LINE DRIVER
SINGLE SUPPY
AC/DC
Converter
AC LINE
ST7538
Figure 22. Application Schematic Example with Coupling Tranformer.
27/30
ST7538
Figure 23. ST7538 Slug Drawing
0.10mm ±0.05
Copper Slug
Solder plated
Lead frame
D03IN1414
Figure 24. Soldering Information
Cu plate
Solder dots
B
L
A
Package Sizes
10x10x1.4mm
A
2.00 mm
B
1.00 mm
L
6.00 mm
L1 (Copper plate)
10.00 mm
L1
L
L1
28/30
D03IN1413
If PCB with ground layer, connect copper plate
with 15 to 20 vias
ST7538
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.60
MAX.
0.063
A1
0.05
0.15
0.002
A2
1.35
1.40
1.45
0.053
0.055
0.057
b
0.30
0.37
0.45
0.012
0.014
0.018
c
0.09
0.20
0.003
D
11.80
12.00
12.20
0.464
D1
9.80
10.00
10.20
0.386
0.006
0.008
0.472
0.480
0.394
0.401
D3
8.00
0.315
e
0.80
0.031
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E3
8.00
0.315
H
5.89
0.232
L
0.45
L1
6.00
S1
6.00
ccc
0.75
0.018
1.00
S
K
0.60
OUTLINE AND
MECHANICAL DATA
0.024
0.030
0.039
0.236
0.236
TQFP44 (10x10x1.40mm)
with Slug Down
0˚ (min.), 3.5˚ (typ.), 7˚(max.)
0.10
0.004
0049510 D
29/30
ST7538
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