TVS Diodes Transient Voltage Suppressor Diodes ESD105-B1-02 Series Low Capacitance & Low Clamping Bi-directional ESD / Transient Protection Diodes ESD105-B1-02ELS ESD105-B1-02EL Data Sheet Revision 1.0, 2013-12-12 Final Power Management & Multimarket ESD105-B1-02 Series Revision History: Rev. 04, 2013-09-24 Page or Item Subjects (major changes since previous revision) Revision 1.0, 2013-12-12 All Status change to Final Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™, CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™, PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™, SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™, XPOSYS™. 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Last Trademarks Update 2010-06-09 Final Data Sheet 2 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Low Capacitance & Low Clamping Bi-directional ESD / Transient Protection 1 Low Capacitance & Low Clamping Bi-directional ESD / Transient Protection Diodes 1.1 Features • • • • • • ESD / Transient protection of signal lines exceeding standard: – IEC61000-4-2 (ESD): ±30 kV air / ±25 kV contact discharge – IEC61000-4-4 (EFT): ±50 A (5/50 ns) – IEC61000-4-5 (Surge): ±5 A (8/20 μs) One-line diode with ultra-small form factor down to 0.62 x 0.32 x 0.31 mm² (0201) package size Bi-directional, symmetrical working voltage up to: VRWM = ±5.5 V Low capacitance CL = 0.3 pF (typical) Very low clamping voltage, low dynamic resistance: RDYN = 0.36 Ω (typ.) Pb-free package (RoHS compliant) and halogen free package 1.2 • • Application Examples USB 3.0. 10/100/1000 Ethernet, Firewire, DVI, HDMI, S-ATA, Display Ports Mobile HDMI Link, MDDI, MIPI, SWP, NFC 1.3 Product Description Pin 1 Pin 2 Pin 1 marking (lasered) Pin 1 TSLP-2 Pin 1 Pin 2 Pin 2 TSSLP-2 a) Pin configuration b) Schematic diagram P G-TS (S)LP -2_Dual_Diode_S erie_P inConf_and_S c hematic Diag. v s d Figure 1 Pin configuration and Schematic diagram Table 1 Ordering Information Type Package Configuration Marking code ESD105-B1-02ELS TSSLP-2-4 1 line, bi-directional N ESD105-B1-02EL TSLP-2-20 1 line, bi-directional N Final Data Sheet 3 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Characteristics 2 Characteristics Table 2 Maximum Ratings at TA = 25 °C, unless otherwise specified 1) Parameter Symbol 2) ESD air discharge contact discharge Unit Min. Typ. Max. – – – – 30 25 – – 5 – – 70 kV VESD Peak pulse current (tp = 8 / 20 μs)3) IPP Peak pulse power tp = 8 / 20 μs Values 3) A W PPK Operating temperature TOP -55 – 125 °C Storage temperature Tstg -65 – 150 °C 1) Device is electrically symmetrical 2) VESD according to IEC61000-4-2 3) IPP according to IEC61000-4-5 Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 2.1 Electrical Characteristics at TA = 25 °C, unless otherwise specified Figure 2 !"# Definitions of electrical characteristics Final Data Sheet 4 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Characteristics Table 3 DC Characteristics at TA = 25 °C, unless otherwise specified 1) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Reverse working voltage VRWM – – 5.5 V Reverse current IR – <1 20 nA Trigger voltage Vt1 6.1 – – V Holding voltage Vh 6.1 8 – V IR = 1 mA Unit Note / Test Condition pF VR = 0 V, f = 1 MHz VR = 5.5 V 1) Device is electrically symmetrical Table 4 AC Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol Line capacitance Table 5 CL Values Min. Typ. Max. – 0.3 0.45 – 0.3 0.45 VR = 0 V, f = 1 GHz ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified 1) Parameter Clamping voltage Symbol 2) VCL Clamping voltage3) Dynamic resistance 2) RDYN Values Unit Note / Test Condition V ITLP = 16 A, tp = 100 ns Min. Typ. Max. – 13 16 – 19 22 ITLP = 30 A, tp = 100 ns – 8.5 11.5 IPP = 2 A, tp = 8/20 µs – 11 14 IPP = 5 A, tp = 8/20 µs – 0.36 0.45 Ω tp = 100 ns 1) Device is electrically symmetrical 2) Please refer to Application Note AN210 [1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristics between ITLP1 = 10 A and ITLP2 = 50 A. 3) IPP according to IEC61000-4-5 (tp = 8/20 µs) Final Data Sheet 5 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Typical Characteristics at TA = 25 °C, unless otherwise specified Typical Characteristics at TA = 25 °C, unless otherwise specified 3 10-7 IR [A] 10-8 -9 10 10-10 -11 10 Figure 3 -6 -5 -4 -3 -2 -1 0 1 VR [V] 60 70 80 TA [°C] 2 3 4 100 110 5 6 Reverse current: IR = f (VR) 10-5 10-6 -7 10 -8 IR [A] 10 -9 10 10-10 -11 10 -12 10 Figure 4 30 40 50 90 120 Reverse current: IR = f(TA), VR = 5.5 V Final Data Sheet 6 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Typical Characteristics at TA = 25 °C, unless otherwise specified 0.45 CL [pF] 0.4 0.35 f = 1 MHz 0.3 f = 1 GHz 0.25 0.2 Figure 5 -6 -5 -4 -3 -2 -1 0 VR [V] 1 2 3 4 5 6 Line capacitance: CL = f (VR), f = 1MHz 700 600 PPK [W] 500 400 300 200 100 0 10-7 Figure 6 10-6 tp [s] 10-5 Peak pulse power: PPK = f (tp) Final Data Sheet 7 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Typical Characteristics at TA = 25 °C, unless otherwise specified 50 25 40 20 30 15 20 ITLP [A] 30 ESD105-B1-02series RDYN 10 RDYN = 0.36 Ω 10 5 0 0 -10 -5 -20 RDYN = 0.36 Ω -10 -30 -15 -40 -20 -50 -25 -60 -30 -25 -20 -15 -10 -5 0 Equivalent VIEC [kV] 60 5 10 15 20 25 -30 30 VTLP [V] Figure 7 Clamping voltage (TLP): ITLP = f(VTLP) according ANSI/ESD STM5.5.1 - Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 Ω, tp = 100 ns, tr = 0.6 ns, ITLP and VTLP averaging window: t1 = ns to t2 = 60 ns, extraction of dynamic resistance using squares fit to TLP characteristics between ITLP1 = 10 A and ITLP2 = 50 A. Please refer to Application Note AN210[1] Final Data Sheet 8 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Typical Characteristics at TA = 25 °C, unless otherwise specified 7 ESD105-B1-02series RDYN 6 5 4 RDYN = 0.9 Ω 3 2 IPP [A] 1 0 -1 -2 RDYN = 0.9 Ω -3 -4 -5 -6 -7 Figure 8 -12 -10 -8 -6 -4 -2 0 2 VCL [V] 4 6 8 10 12 Pulse current (IEC61000-4-5) versus clamping voltage: IPP = f(VCL) Final Data Sheet 9 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Typical Characteristics at TA = 25 °C, unless otherwise specified 150 Scope: 6 GHz, 20 GS/s 125 VCL [V] 100 VCL-max-peak = 135 V 75 VCL-30ns-peak = 10 V 50 25 0 -25 -50 Figure 9 0 50 100 150 200 tp [ns] 250 300 350 400 450 IEC61000-4-2: VCL = f (t), 8 kV positive pulse from pin 1 to pin 2 25 Scope: 6 GHz, 20 GS/s 0 VCL [V] -25 -50 -75 VCL-max-peak = -134 V -100 VCL-30ns-peak = -11 V -125 -150 -50 Figure 10 0 50 100 150 200 tp [ns] 250 300 350 400 450 IEC61000-4-2: VCL = f (t), 8 kV negative pulse from pin 1 to pin 2 Final Data Sheet 10 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Typical Characteristics at TA = 25 °C, unless otherwise specified 200 Scope: 6 GHz, 20 GS/s 175 150 VCL [V] 125 VCL-max-peak = 183 V 100 75 VCL-30ns-peak = 14 V 50 25 0 -25 -50 -50 Figure 11 0 50 100 150 200 tp [ns] 250 300 350 400 450 IEC61000-4-2: VCL = f (t), 15 kV positive pulse from pin 1 to pin 2 50 Scope: 6 GHz, 20 GS/s 25 0 VCL [V] -25 -50 -75 -100 VCL-max-peak = -185 V -125 VCL-30ns-peak = -14 V -150 -175 -200 -50 Figure 12 0 50 100 150 200 tp [ns] 250 300 350 400 450 IEC61000-4-2: VCL = f (t), 15 kV negative pulse from pin 1 to pin 2 Final Data Sheet 11 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Application Information 4 Application Information Insertion Loss in the application Networkanalysor 50 Ohm port1 Line Networkanalysor 50 Ohm port2 Line ESD105-B1-02series ESD105-B1-02series_insertion_loss.vsd Figure 13 Insertion loss measured in 50 Ω environment 0 Insertion Loss [dB] -1 -2 -3 -4 -5 Figure 14 ESD105-B1-TSLP 0V / 3dB @ 14410MHz ESD105-B1-TSSLP 0V / 3dB @ 18142MHz 1 10 100 f [MHz] 1000 10000 Insertion loss vs. frequency of ESD105-B1-02xx in a 50 Ω system Final Data Sheet 12 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Connector Application Information Protected signal line ESD I/O sensitive device 1 2 The protection diode should be placed very close to the location where the ESD or other transients can occur to keep loops and inductances as small as possible . Pin 2 (or pin 1) should be connected directly to a ground plane on the board . A pplic ation_E S D5V3S 1B-02LS .v s d Figure 15 Single line, bi-directional ESD / Transient protection Final Data Sheet 13 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Package Information 5 Package Information 5.1 TSSLP-2-4 Top view Bottom view 0.31 +0.01 -0.02 0.32 ±0.05 0.355 0.62 ±0.05 2 0.05 MAX. Cathode marking 0.26 ±0.035 0.2 ±0.035 1) 1 1) 1) Dimension applies to plated terminals TSSLP-2-3-PO V01 TSSLP-2-4 Package outline 0.19 0.24 Solder mask 0.19 0.57 0.62 Copper 0.19 0.27 0.14 0.32 0.24 Figure 16 Stencil apertures TSSLP-2-3-FP V02 Figure 17 TSSLP-2-4 Footprint 0.35 Tape type Ex Ey Punched Tape 0.43 0.73 Embossed Tape 0.37 0.67 8 Ey 4 Cathode marking Figure 18 Deliveries can be both tape types (no selection possible). Specification allows identical processing (pick & place) by users. Ex TSSLP-2-3-TP V03 TSSLP-2-4 Packing Figure 19 TSSLP-2-4 Marking (example) Final Data Sheet 14 Revision 1.0, 2013-12-12 ESD105-B1-02 Series Package Information 5.2 TSLP-2-20 Top view Bottom view 0.31 +0.01 -0.02 0.6 ±0.05 1±0.05 2 1 0.25 ±0.035 1) 0.65 ±0.05 0.05 MAX. 0.5 ±0.035 1) Cathode marking 1) Dimension applies to plated terminals TSLP-2-19, -20-PO V01 TSLP-2-20 Package outline 0.28 0.35 Solder mask 0.38 0.93 1 Copper 0.28 0.45 0.3 0.6 0.35 Figure 20 Stencil apertures TSLP-2-19, -20-FP V01 Figure 21 TSLP-2-20 Footprint 0.4 1.16 Cathode marking 8 4 0.76 TSLP-2-19, -20-TP V02 Figure 22 TSLP-2-20 Packing Type code 12 Cathode marking TSLP-2-19, -20-MK V01 Figure 23 TSLP-2-20 Marking (example) Final Data Sheet 15 Revision 1.0, 2013-12-12 ESD105-B1-02 Series References References [1] Infineon Technologies AG, “Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology”, Application Note 210, RF and Protection Devices, April 22, 2010, Rev.1.0 [2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages Final Data Sheet 16 Revision 1.0, 2013-12-12 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG