5962-1124201VFA

REVISIONS
LTR
DESCRIPTION
A
DATE (YR-MO-DA)
APPROVED
14-03-21
C.SAFFLE
Add peak-to-peak jitter and random jitter test under Table IA. -jt
REV
SHEET
REV
A
A
SHEET
15
16
REV STATUS
REV
A
A
A
A
A
A
A
A
A
A
A
A
A
A
OF SHEETS
SHEET
1
2
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4
5
6
7
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12
13
14
PMIC N/A
PREPARED BY
JEFFERY TUNSTALL
STANDARD
MICROCIRCUIT
DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
CHECKED BY
RAJESH PITHADIA
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
CHARLES SAFFLE
DRAWING APPROVAL DATE
MICROCIRCUIT, DIGITAL-LINEAR, 2x2 LVDS
CROSSPOINT SWITCH, MONOLITHIC SILICON
12-07-30
REVISION LEVEL
A
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
5962-11242
1 OF 16
5962-E187-14
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When
available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
11242
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
F
A
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type. The device type identify the circuit function as follows:
Device type
Generic number
01
Circuit function
SN55LVCP22-SP
2x2 LVDS crosspoint switch
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline. The case outline are as designated in MIL-STD-1835 and as follows:
Outline letter
F
Descriptive designator
GDFP2-F16
Terminals
Package style
16
Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-11242
A
REVISION LEVEL
A
SHEET
2
1.3 Absolute maximum ratings. 1/
Supply voltage range, VCC …………………………………………………………………. - 0.5 V to 4 V 2/
CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1) ……………………………………. -0.5 V to 4 V
LVDS receiver input voltage (IN+, IN-) ……………………………………………………. -0.7 V to 4.3 V
LVDS driver output voltage (OUT+, OUT-)……………………………………………….. -0.5 V to 4.0 V
LVDS output short circuit current ………………………………………………………….. Continuous
Storage temperature range …………………………………………………………………. -65°C to 125°C
Junction temperature ………………………………………………………………………… +150°C
Power dissipation (PD)……………………………………………………………………….. 313 mW 3/
Thermal resistance, junction-to-ambient (θJA)……………………………………………… 82.5° C/W
Thermal resistance, junction-to-case (θJC) ………………………………………………… 7.5° C/W
Maximum lead temperature (soldering 10 seconds)……………………………………… 300°C
Electrostatic discharge (ESD) classification:
Human body model (HBM) …………………………………………… 5000 V
Charged-device mode (CDM) ………………………………………… 500V
1.4 Recommended operating conditions.
Supply voltage, VCC ………………………………………………………………………….. 3 V to 3.6 V
Receiver input voltage …………………………………………………………………......... 0 V to 4 V
Operating case Temperature, range (TC)…………………………………………………… -55°C to +125°C
Magnitude of differential input voltage│VID│……………………………………………….. 0.1 V to 3V
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil/ or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
________
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ All voltage values, except differential I/O bus voltages, are with respect to network ground terminals.
3/ Test conditions: VCC = 3.6 V, TA=125°C, 1Gbps.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-11242
A
REVISION LEVEL
A
SHEET
3
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein.
3.2.2 Terminal Connections. The terminal connections shall be as specified on figure 1.
3.2.3 Function table. The function table shall be as specified on figure 2.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance
submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall
be provided with each lot of microcircuits delivered to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-11242
A
REVISION LEVEL
A
SHEET
4
TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Unit
Min
Max
CMOS/TTL DC SPECIFICATION (EN0, EN1, SEL0, SEL1)
High-level input voltage
VIH
1, 2, 3
01
2
VCC
V
Low-level input voltage
VIL
1, 2, 3
01
GND
0.8
V
High-level input current
IIH
1, 2, 3
01
±25
µA
1, 2, 3
01
±15
µA
1, 2, 3
01
-1.5
V
RL = 75 Ω, See figure 3
1, 2, 3
01
255
475
RL = 75 Ω, VCC = 3.3 V,
1
01
285
440
VIN = 3.6 V or 2.0 V,
VCC = 3.6 V
Low-level input current
IIL
VIN = 0.0 V or 0.8 V,
VCC = 3.6 V
Input clamp voltage
VCL
ICL = -18mA
LVDS OUTPUT SPECIFICATION (OUT0, OUT1)
Differential output voltage
│VOD│
mV
TA = 25°C, See figure 3
Change in differential output
voltage magnitude between
states
Δ│VOD│
VID = ± 100mV, See figure 3
1, 2, 3
01
-25
25
mV
Steady-state offset voltage
VOS
See Figure 4
1, 2, 3
01
1
1.45
V
Change in steady-state offset
voltage between logic states
ΔVOS
See Figure 4
1, 2, 3
01
-25
25
mV
High-impedance output current
IOZ
VOUT = GND or VCC
1, 2, 3
01
±15
µA
Power-off leakage current
IOFF
VCC = 0 V, 1.5 V;
1, 2, 3
01
±15
µA
VOUT + or VOUT- = 0 V
1, 2, 3
01
-8
mA
VOUT + and VOUT- = 0 V
1, 2, 3
01
8
mA
VOUT = 3.6 V or GND
Output short-circuit current
IOS
Both outputs short-circuit current IOSB
-8
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
A
SHEET
5
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups
type
Limits
Min
Unit
Max
LVDS RECIEVER DC SPECIFICATION (IN0, IN1)
Positive-going differential input
voltage threshold
VTH
See table IB
1, 2, 3
01
Negative-going differential input
voltage threshold
VTL
See table IB
1, 2, 3
01
Differential input voltage
hysteresis
VID
Common-mode voltage range
100
mV
-100
1, 2, 3
mV
150
mV
3.95
V
(HYS)
VCMR
VID = 100mV,
1,2,3
01
1, 2, 3
01
.05
VCC = 3.0 V to 3.6 V
Input current
IIN
VIN = 4 V, VCC = 3.6 V
±18
µA
or 0.0 V
VIN = 0 V, VCC = 3.6 V
1, 2, 3
01
±18
1, 2, 3
01
87
mA
or 0.0 V
SUPPLY CURRENT
Quiescent supply current
ICCQ
RL = 75Ω,
ENO = EN1 = High
Total supply current
ICCD
RL = 75Ω, CL = 5 pF, 500
MHz(1000 Mbps),
EN0 = EN1 = High
1, 2, 3
01
87
mA
Three state supply current
ICCZ
EN0 = EN1 = Low
1, 2, 3
01
35
mA
See 4.4.1b
7,8
01
Functional test
SWITCHING CHARACTERISTICS
Input to SEL setup time
tSET
See figure 5
9, 10, 11
2.2
ns
Input to SEL hold time
tHOLD
See figure 5
9, 10, 11
01
2.2
ns
SEL to switched output
tSWITCH
See figure 5
9, 10, 11
01
2.6
ns
Disable time, high-level-to-highimpedance
tPHZ
See figure 6
9, 10, 11
01
4
ns
Disable time, low-level-to-highimpedance
tPLZ
See figure 6
9, 10, 11
01
4
ns
Enable time, high-impedance-to- tPZH
high-level output
See Figure 6
9, 10, 11
01
4
ns
Enable time, high-impedance-to- tPZL
low-level output
See Figure 6
9, 10, 11
01
8
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
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COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-11242
A
REVISION LEVEL
A
SHEET
6
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Unit
Max
SWITCHING CHARACTERISTICS – Continued.
Differential output signal rise time tLHT
(20%-80%) 1/
CL = 5 pF, see Figure 7
9, 10, 11
01
620
ps
Differential output signal fall time
(20%-80%) 1/
tHLT
CL = 5 pF, See Figure 7
9, 10, 11
01
620
ps
Propagation delay time, low-tohigh level output 1/
tPLHD
9, 10, 11
01
200
2350
ps
Propagation delay time, high-tolow-level output
1/
tPHLD
9, 10, 11
01
200
2350
ps
Pulse skew (│tPLHD-tPHLD│) 2/ 3/
tskew
CL = 5 pF, See Figure 7
9, 10, 11
01
160
ps
Added peak-to-peak jitter
tJIT
VID = 200 mV, 50% duty cycle,
9, 10, 11
01
22.2
ps
9, 10, 11
01
24.5
9, 10, 11
01
35.7
15
9, 10, 11
01
204
15
9, 10, 11
01
282
9, 10, 11
01
1.5
9, 10, 11
01
1.53
9, 10, 11
01
1.79
4, 5, 6
01
VCM = 1.2 V, 50 MHz, CL = 5pF
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 240 MHz, CL = 5pF
VID = 200 mV, 50% duty cycle
VCM = 1.2 V, 500 MHz, CL = 5 pF
VID = 200 mV, PRBS = 2 -1 data
pattern, VCM = 1.2 V, 240 Mbps,
CL = 5 pF
VID = 200 mV, PRBS = 2 -1 data
pattern, VCM = 1.2 V, 1000 Mbps,
CL = 5 pF
Added random jitter (rms)
tJMS
VID = 200 mV, 50% duty cycle,
PSRMS
VCM = 1.2 V, 50 MHz, CL = 5 pF
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 240 MHz, CL = 5 pF
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 500 MHz, CL = 5 pF
Maximum operating frequency 2/
4/
fMAX
1
GHz
1/ Input: VIC = 1.2 V, VID = 200 mV, 50% duty cycle, 1 MHz, tr/tf = 500 ps.
2/ Pulse skew and fMAX parameters are guaranteed by characterization, but not production tested.
3/ tskew is the magnitude of the time difference between the tPLHD and tPHLD of any output of a single device.
4/ Signal generator conditions: 50% duty cycle, tr or tf ≤ 100 ps (10% to 90%), transmitter output criteria:
Duty cycle = 45% to 55% VOD ≥ 300 mV.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-11242
A
REVISION LEVEL
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SHEET
7
Table IB. Reciever Input voltage threshold test.
Applied Voltages
VIA
1.25 V
1.15 V
4.0 V
3.9 V
0.1 V
0.0 V
1.7 V
0.7 V
4.0 V
3.0 V
1.0 V
0.0 V
Resulting differential Input Voltage
Resulting Common-Mode input Voltage
VID
100mA
-100mV
100 mV
-100 mA
100 mV
-100 mA
1000 mV
-1000 mV
1000 mV
-1000 mV
1000 mV
-1000 mV
VIC
1.2 V
1.2 V
3.95 V
3.95 V
0.05 V
0.05
1.2 V
1.2 V
3.5 V
3.5 V
0.5 V
0.5 V
VIB
1.15 V
1.25
3.9 V
4.0 V
0.0 V
0.1 V
0.7 V
1.7 V
3.0 V
4.0 V
0.0 V
1.0 V
Output
1/
H
L
H
L
H
L
H
L
H
L
H
L
1/ H = High level, L = low level.
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MICROCIRCUIT DRAWING
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REVISION LEVEL
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SHEET
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Device type
01
Case outline
F
Terminal number
Terminal symbol
1
SEL1
2
SEL0
3
IN0+
4
IN0-
5
VCC
6
IN1+
7
IN1-
8
NC
9
NC
10
OUT1-
11
OUT1+
12
GND
13
OUT0-
14
OUT0+
15
EN1
16
EN0
NC = No internal connection
FIGURE 1. Terminal connection.
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REVISION LEVEL
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SEL0
SEL1
OUT0
OUT1
Mode
0
0
IN0
IN0
1:2 splitter
0
1
IN0
IN1
Repeater
1
0
IN1
IN0
Switch
1
1
IN1
IN1
1:2 splitter
FIGURE 2. Function table.
Figure 3. Differential output voltage (VOD) test circuit.
Note: All input pulses are supplied by a generator having the following characteristics tr or tf ≤ 1 ns,
Pulse-repetition rate (PRR) = 0.5 Mbps, pulse width = 500 ± 10 ns; RL = 100 Ω; CL includes
instrumentation and fixture capacitance within 0.06 mm of the D.U.T.; the measurement of
VOC(PP) is made on test equipment with a -3 db bandwidth of at least 300 MHz.
Figure 4. Test circuit and definition for the driver common-mode output voltage.
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REVISION LEVEL
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SHEET
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FIGURE 5. Input to select for both rising and falling edge setup and hold times.
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FIGURE 6. Enable and disable test circuit and waveforms.
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DSCC FORM 2234
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REVISION LEVEL
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Figure 7. Timing test circuit and waveforms.
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MICROCIRCUIT DRAWING
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DSCC FORM 2234
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REVISION LEVEL
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection.
4.2.1 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein (see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device classes Q and V, subgroups 7 and 8 shall include verifying the function table.
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MICROCIRCUIT DRAWING
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REVISION LEVEL
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TABLE IIA. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
Device
class Q
class V
1, 7, 9
1, 7, 9
1, 2, 3, 7, 8, 9,
10, 11
1/
1, 2, 3, 7, 8,
9,10, 11 1/ 2/
1, 2, 3, 7, 8,
9, 10, 11
1, 2, 3
1, 2, 3, 7, 8,
9, 10, 11
1, 2, 3 2/
1
1
-
-
1/ PDA applies to subgroup 1.
2/ Delta limits as specified in table IIB shall be required where specified and the delta limits
shall be computed with reference to the zero hour electrical parameters.
Table IIB. Burn-in and operating life test delta parameters. (+25°C) 1/
Parameters 1/
Delta Limits
Total quiescent supply current,
ICCQ
Three state supply current, ICCZ
-/+ 1.5 mA
High-level input current, IIH
-/+ 300 nA
Low-level input current, IIL
-/+ 200 nA
Steady-state offset voltage, VOS
-/+ 50 mV
-/+ 0.5 mA
1/ These parameters shall be recorded before and after the required
burn-in and life test to determine delta limits.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
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REVISION LEVEL
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4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point
electrical parameter limits as defined in table IA at TA = +25°C ±5°C, after exposure, to the subgroups specified in table
IIA herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime -VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime -VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-HDBK103 QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and
Maritime -VA and have agreed to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-11242
A
REVISION LEVEL
A
SHEET
16
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 14-03-21
Approved sources of supply for SMD 5962-11242 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime -VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-1124201VFA
01295
SN55LVCP22W-SP
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
01295
Vendor name
and address
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Ln.
P.O. Box 660199
Dallas, TX 75243
POC U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.