IRF9530S, SiHF9530S Datasheet

IRF9530S, SiHF9530S
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
-100
RDS(on) ()
VGS = -10 V
0.30
Qg max. (nC)
38
Qgs (nC)
6.8
Qgd (nC)
21
Configuration
Single
S
D2PAK
•
•
•
•
•
•
•
•
Surface mount
Available in tape and reel
Dynamic dV/dt rating
Available
Repetitive avalanche rated
P-channel
Available
175 °C operating temperature
Fast switching
Material categorization: for definitions of
compliance please see www.vishay.com/doc?99912
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
(TO-263)
G
DESCRIPTION
G D
S
D
P-Channel MOSFET
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface mount power package
capable of accommodating die sizes up to HEX-4. It
provides the highest power capability and the lowest
possible on-resistance in any existing surface mount
package. The D2PAK (TO-263) is suitable for high current
applications because of its low internal connection
resistance and can dissipate up to 2.0 W in a typical surface
mount application.
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
D2PAK (TO-263)
SiHF9530S-GE3
IRF9530SPbF
SiHF9530S-E3
D2PAK (TO-263)
SiHF9530STRL-GE3 a
IRF9530STRLPbF a
SiHF9530STL-E3 a
D2PAK (TO-263)
SiHF9530STRR-GE3 a
IRF9530STRRPbF a
SiHF9530STR-E3 a
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
VGS at - 10 V
TC = 25 °C
TC = 100 °C
SYMBOL
LIMIT
VDS
VGS
-100
± 20
-12
-8.2
-48
0.59
0.025
400
-12
8.8
88
3.7
- 5.5
-55 to +175
300
ID
Pulsed Drain Current a
IDM
Linear Derating Factor
Linear Derating Factor (PCB mount) e
Single Pulse Avalanche Energy b
EAS
Avalanche Current a
IAR
EAR
Repetitive Avalanche Energy a
Maximum Power Dissipation
TC = 25 °C
PD
Maximum Power Dissipation (PCB mount) e
TA = 25 °C
dV/dt
Peak Diode Recovery dV/dt c
Operating Junction and Storage Temperature Range
TJ, Tstg
Soldering Recommendations (Peak temperature) d
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = -25 V, starting TJ = 25 °C, L = 4.2 mH, Rg = 25 , IAS = -12 A (see fig. 12).
c. ISD  - 12 A, dI/dt  140 A/μs, VDD  VDS, TJ  175 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
S16-0754-Rev. D, 02-May-16
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
Document Number: 91077
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF9530S, SiHF9530S
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
62
Maximum Junction-to-Ambient 
(PCB mount) a
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
1.7
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material). 
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0, ID = -250 μA
-100
-
-
V
VDS/TJ
Reference to 25 °C, ID = -1 mA
-
-0.10
-
V/°C
VGS(th)
VDS = VGS, ID = -250 μA
-2.0
-
-4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = -100 V, VGS = 0 V
-
-
-100
VDS = -80 V, VGS = 0 V, TJ = 150 °C
-
-
-500
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
μA
-
-
0.30

gfs
VDS = -50 V, ID = -7.2 A b
3.7
-
-
S
VGS = 0 V,
VDS = -25 V,
f = 1.0 MHz, see fig. 5
-
860
-
-
340
-
-
93
-
-
-
38
-
-
6.8
RDS(on)
ID = -7.2 A b
VGS = -10 V
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
pF
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
-
21
Turn-On Delay Time
td(on)
-
12
-
tr
-
52
-
-
31
-
-
39
-
-
4.5
-
-
7.5
-
0.4
-
3.3
-
-
-12
-
-
-48
-
-
-6.3
V
-
120
240
ns
-
0.46
0.92
μC
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = -10 V
ID = -12 A, VDS = -80 V,
see fig. 6 and 13 b
VDD = -50 V, ID = -12 A,
RG = 12 , RD = 3.9 , see fig. 10 b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Gate Input Resistance
Rg
Between lead,
6 mm (0.25") from
package and center of
die contact
nC
ns
D
nH
G
S
f = 1 MHz, open drain

Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current a
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the 
integral reverse
p -n junction diode
D
A
G
S
TJ = 25 °C, IS = -12 A, VGS = 0 V b
TJ = 25 °C, IF = -12 A, dI/dt = 100 A/μs b
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
S16-0754-Rev. D, 02-May-16
Document Number: 91077
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF9530S, SiHF9530S
www.vishay.com
Vishay Siliconix
VGS
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom - 4.5 V
- ID, Drain Current (A)
Top
101
- 4.5 V
20 µs Pulse Width
TC = 25 °C
100
10-1
100
101
- VDS, Drain-to-Source Voltage (V)
91077_01
Bottom
2.0
1.5
1.0
0.5
0.0
- 60- 40 - 20 0
TJ, Junction Temperature (°C)
100
Ciss
900
600
Coss
300
Crss
0
101
100
- VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
- ID, Drain Current (A)
175 °C
20 µs Pulse Width
VDS = - 50 V
100
- VGS, Gate-to-Source Voltage (V)
20
25 °C
101
- VDS, Drain-to-Source Voltage (V)
91077_05
Fig. 2 - Typical Output Characteristics, TC = 175 °C
ID = - 12 A
16
VDS = - 80 V
VDS = - 50 V
12
VDS = - 20 V
8
4
For test circuit
see figure 13
0
4
91077_03
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
1200
20 µs Pulse Width
TC = 175 °C
101
20 40 60 80 100 120 140 160 180
1500
- 4.5 V
91077_02
2.5
1800
VGS
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
- 4.5 V
100
10-1
ID = - 12 A
VGS = - 10 V
Fig. 4 - Normalized On-Resistance vs. Temperature
Capacitance (pF)
- ID, Drain Current (A)
101
3.0
91077_04
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Top
RDS(on), Drain-to-Source On Resistance
(Normalized)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
5
6
7
8
9
- VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S16-0754-Rev. D, 02-May-16
10
0
91077_06
10
20
30
40
50
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91077
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF9530S, SiHF9530S
www.vishay.com
Vishay Siliconix
10
- ID, Drain Current (A)
- ISD, Reverse Drain Current (A)
12
175 °C
101
25 °C
100
6
4
2
VGS = 0 V
10-1
0
1.0
2.0
3.0
5.0
4.0
50
25
- VSD, Source-to-Drain Voltage (V)
91076_07
75
100
125
150
175
TC, Case Temperature (°C)
91077_09
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
RD
103
VDS
Operation in this area limited
by RDS(on)
5
2
- ID, Drain Current (A)
8
VGS
102
D.U.T.
Rg
5
10 µs
2
100 µs
+VDD
- 10 V
10
1 ms
5
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
10 ms
2
1
Fig. 10a - Switching Time Test Circuit
5
TC = 25 °C
TJ = 175 °C
Single Pulse
2
0.1
0.1
2
5
1
2
5
10
2
td(on)
5
2
102
5
td(off) tf
tr
VGS
103
10 %
- VDS, Drain-to-Source Voltage (V)
91077_08
Fig. 8 - Maximum Safe Operating Area
90 %
VDS
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
1
D = 0.5
0.2
PDM
0.1
0.1
0.05
t1
Single Pulse
(Thermal Response)
0.02
0.01
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5
91077_11
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S16-0754-Rev. D, 02-May-16
Document Number: 91077
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF9530S, SiHF9530S
www.vishay.com
Vishay Siliconix
L
Vary tp to obtain
required IAS
IAS
VDS
VDS
D.U.T.
Rg
+ V DD
VDD
IAS
tp
- 10 V
0.01 Ω
tp
VDS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
EAS, Single Pulse Energy (mJ)
1200
ID
- 4.9 A
- 8.5 A
Bottom - 12 A
Top
1000
800
600
400
200
0
VDD = - 25 V
25
91077_12c
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
- 10 V
12 V
0.2 µF
0.3 µF
QGS
-
QGD
D.U.T.
VG
+ VDS
VGS
- 3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S16-0754-Rev. D, 02-May-16
Fig. 13b - Gate Charge Test Circuit
Document Number: 91077
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF9530S, SiHF9530S
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
3
+
2
-
-
4
+
1
• dV/dt controlled by Rg
• ISD controlled by duty factor “D”
• D.U.T. - device under test
Rg
+
-
VDD
Compliment N-channel of D.U.T. for driver
1
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = -10 V a
2
D.U.T. ISD waveform
Reverse
recovery
current
3
Body diode forward
current
dI/dt
D.U.T. VSD waveform
Re-applied
voltage
4
Diode recovery
dV/dt
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
Note
a V = -5 V for logic level and -3 V drive devices
GS
Fig. 14 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91077.
S16-0754-Rev. D, 02-May-16
Document Number: 91077
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
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1
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
1
Document Number: 91000