IRF740AS, SiHF740AS, IRF740AL, SiHF740AL Datasheet

IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Halogen-free According to IEC 61249-2-21
Definition
• Low Gate Charge Qg Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully
Characterized
Capacitance
and
Avalanche Voltage and Current
• Effective Coss specified
• Compliant to RoHS Directive 2002/95/EC
400
RDS(on) ()
VGS = 10 V
0.55
Qg (Max.) (nC)
36
Qgs (nC)
9.9
Qgd (nC)
16
Configuration
Single
D
D2PAK (TO-263)
I2PAK (TO-262)
APPLICATIONS
G
G
D
S
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• High speed Power Switching
G
D
S
TYPICAL SMPS TOPOLOGIES
• Single Transistor Flyback Xfmr. Reset
• Single Transistor Forward Xfmr. Reset (Both for US Line
Input Only)
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
D2PAK (TO-263)
D2PAK (TO-263)
D2PAK (TO-263)
I2PAK (TO-262)
SiHF740AS-GE3
SiHF740ASTRL-GE3a
SiHF740ASTRR-GE3a
SiHF740AL-GE3
IRF740ASPbF
IRF740ASTRLPbFa
IRF740ASTRRPbFa
IRF740ALPbF
SiHF740AS-E3
SiHF740ASTL-E3a
SiHF740ASTR-E3a
SiHF740AL-E3
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
VDS
VGS
400
± 30
10
6.3
40
1.0
630
10
12.5
3.1
125
5.9
- 55 to + 150
300d
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Currente
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta, e
Linear Derating Factor
Single Pulse Avalanche Energyb, e
Avalanche Currenta
Repetiitive Avalanche Energya
Maximum Power Dissipation
Peak Diode Recovery dV/dtc, e
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
ID
IDM
EAS
IAR
EAR
TA = 25 °C
TC = 25 °C
PD
dV/dt
TJ, Tstg
for 10 s
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 12.6 mH, Rg = 25 , IAS = 10 A (see fig. 12).
c. ISD  10 A, dI/dt  330 A/μs, VDD  VDS, TJ  150 °C.
d. 1.6 mm from case.
e. Uses IRF740A, SiHF740A data and test conditions.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91052
S11-1048-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient (PCB
Mounted, Steady-State)a
PARAMETER
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
1.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0, ID = 250 μA
400
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mAd
-
0.48
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 400 V, VGS = 0 V
-
-
25
VDS = 320 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 6.0 Ab
VGS = 10 V
VDS = 50 V, ID = 6.0 Ad
μA
-
-
0.55

4.9
-
-
S
-
1030
-
-
170
-
-
7.7
-
-
1490
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Effective Output Capacitance
Coss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5d
VDS = 1.0 V, f = 1.0 MHz
VGS = 0 V
Coss eff.
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 10 V
VDS = 320 V, f = 1.0 MHz
-
52
-
VDS = 0 V to 320 Vc, d
-
61
-
-
-
36
-
-
9.9
ID = 10 A, VDS = 320 V,
see fig. 6 and 13b, d
pF
nC
Gate-Drain Charge
Qgd
-
-
16
Turn-On Delay Time
td(on)
-
10
-
-
35
-
-
24
-
-
22
-
-
-
10
-
-
40
-
-
2.0
-
240
360
ns
-
1.9
2.9
μC
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VDD = 200 V, ID = 10 A,
Rg = 10 , RD = 19.5 , see fig. 10b, d
tf
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 10 A, VGS = 0 Vb
TJ = 25 °C, IF = 10 A, dI/dt = 100 A/μsb, d
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
d. Uses IRF740A, SiHF740A data and test conditions.
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Document Number: 91052
S11-1048-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
102
VGS
Top
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
10
1
4.5 V
0.1
20 µs Pulse Width
TJ = 25 °C
10-2
0.1
1
10
TJ = 150 °C
1
TJ = 25 °C
0.1
4.0
102
10
VDS, Drain-to-Source Voltage (V)
91052_01
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
102
4.5 V
20 µs Pulse Width
TJ = 150 °C
0.1
0.1
91052_02
1
10
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91052
S11-1048-Rev. C, 30-May-11
102
RDS(on), Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
1
6.0
7.0
8.0
9.0
10.0
Fig. 3 - Typical Transfer Characteristics
Top
10
5.0
VGS, Gate-to-Source Voltage (V)
91052_03
Fig. 1 - Typical Output Characteristics
102
20 µs Pulse Width
VDS = 50 V
91052_04
3.0
2.5
ID = 10 A
VGS = 10 V
2.0
1.5
1.0
0.5
0.0
- 60 - 40 - 20 0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
104
Ciss
103
Coss
102
Crss
10
102
ISD, Reverse Drain Current (A)
C, Capacitance (pF)
105
10
TJ = 150 °C
1
1
VGS = 0 V
0.1
102
10
1
103
VDS, Drain-to-Source Voltage (V)
91052_05
0.2
20
102
ID, Drain Current (A)
VDS = 80 V
12
8
For test circuit
see figure 13
0
91052_06
10
20
30
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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1.2
1.4
100 µs
10
1 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
1
10
40
QG, Total Gate Charge (nC)
1.0
10 µs
4
0
0.8
Operation in this area limited
by RDS(on)
VDS = 320 V
VDS = 200 V
0.6
Fig. 7 - Typical Source-Drain Diode Forward Voltage
ID = 10 A
16
0.4
VSD, Source-to-Drain Voltage (V)
91052_07
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
VGS, Gate-to-Source Voltage (V)
TJ = 25 °C
91052_08
10 ms
102
103
VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91052
S11-1048-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
RD
VDS
VGS
10.0
8.0
ID, Drain Current (A)
D.U.T.
Rg
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
6.0
Fig. 10a - Switching Time Test Circuit
4.0
VDS
90 %
2.0
0.0
25
50
75
100
125
150
10 %
VGS
TC, Case Temperature (°C)
91052_09
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
1
D = 0.50
0.20
0.10
0.05
0.02
0.01
0.1
PDM
t1
Single Pulse
(Thermal Response)
10-2
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-3
10-5
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
91052_11
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
D.U.T
Rg
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91052
S11-1048-Rev. C, 30-May-11
Fig. 12b - Unclamped Inductive Waveforms
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IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
1400
ID
Top
4.5 A
6.3 A
Bottom 10 A
1200
1000
800
600
400
200
0
25
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
91052_12c
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
580
VDSav, Avalanche Voltage (V)
EAS, Single Pulse Avalanche Energy (mJ)
Vishay Siliconix
560
540
520
500
480
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0
IAV, Avalanche Current (A)
91052_12d
Fig. 12d - Typlical Drain-to-Source Voltage
vs. Avalanche Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91052
S11-1048-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91052.
Document Number: 91052
S11-1048-Rev. C, 30-May-11
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This document is subject to change without notice.
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Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
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Package Information
Vishay Siliconix
I2PAK (TO-262) (HIGH VOLTAGE)
A
(Datum A)
E
B
c2
A
E
A
L1
Seating
plane
D1
D
C
L2
C
B
B
L
A
c
3 x b2
E1
A1
3xb
Section A - A
Base
metal
2xe
b1, b3
Plating
0.010 M A M B
c1
c
(b, b2)
Lead tip
Section B - B and C - C
Scale: None
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D
8.38
9.65
0.330
0.380
A1
2.03
3.02
0.080
0.119
D1
6.86
-
0.270
-
b
0.51
0.99
0.020
0.039
E
9.65
10.67
0.380
0.420
b1
0.51
0.89
0.020
0.035
E1
6.22
-
0.245
-
b2
1.14
1.78
0.045
0.070
e
b3
1.14
1.73
0.045
0.068
L
13.46
14.10
0.530
0.555
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.065
c1
0.38
0.58
0.015
0.023
L2
3.56
3.71
0.140
0.146
c2
1.14
1.65
0.045
0.065
2.54 BSC
0.100 BSC
ECN: S-82442-Rev. A, 27-Oct-08
DWG: 5977
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost
extremes of the plastic body.
3. Thermal pad contour optional within dimension E, L1, D1, and E1.
4. Dimension b1 and c1 apply to base metal only.
Document Number: 91367
Revision: 27-Oct-08
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12
1
Document Number: 91000