IRL530S, SiHL530S Datasheet

IRL530S, SiHL530S
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• Logic Level Gate Drive
• RDS(on) Specified at VGS = 4 V and 5 V
• 175 °C Operating Temperature
• Compliant to RoHS Directive 2002/95/EC
100
RDS(on) ()
VGS = 5.0 V
0.16
Qg (Max.) (nC)
28
Qgs (nC)
3.8
Qgd (nC)
14
Configuration
Single
D
D2PAK
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface mount power package
capable of accommodating die sizes up to HEX-4. It
provides the highest power capability and the lowest
possible on resistance in any existing surface mount
package. The D2PAK (TO-263) is suitable for high current
applications because of its low internal connection
resistance and can dissipate up to 2.0 W in a typical surface
mount application.
(TO-263)
G
G D
S
S
N-Channel MOSFET
ORDERING INFORMATION
D2PAK (TO-263)
SiHL530STRR-GE3a
IRL530STRRPbFa
SiHL530STR-E3a
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
SYMBOL
VDS
VGS
VGS at 5 V
TC = 25 °C
TC = 100 °C
Currenta
Pulsed Drain
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
ID
IDM
EAS
IAR
EAR
TC = 25 °C
TA = 25 °C
PD
dV/dt
TJ, Tstg
for 10 s
LIMIT
100
± 10
15
11
60
0.59
0.025
290
15
8.8
88
3.7
5.5
- 55 to + 175
300d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 1.9 mH, Rg = 25 , IAS = 15 A (see fig. 12).
c. ISD  15 A, dI/dt  140 A/μs, VDD  VDS, TJ  175 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91342
S11-1055-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL530S, SiHL530S
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
62
Maximum Junction-to Ambient (PCB
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
1.7
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0, ID = 250 μA
100
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.14
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
1.0
-
2.0
V
nA
IGSS
IDSS
RDS(on)
gfs
VGS = ± 10 V
-
-
± 100
VDS = 100 V, VGS = 0 V
-
-
25
VDS = 80 V, VGS = 0 V, TJ = 150 °C
-
-
250
VGS = 5.0 V
ID = 9.0 Ab
-
-
0.16
VGS = 4.0 V
Ab
-
-
0.22
6.4
-
-
-
930
-
ID = 7.5
VDS = 50 V, ID = 9.0 Ab
μA

S
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
250
-
57
-
-
-
28
pF
Gate-Source Charge
Qgs
-
-
3.8
Gate-Drain Charge
Qgd
-
-
14
Turn-On Delay Time
td(on)
-
4.7
-
tr
-
100
-
-
22
-
-
48
-
-
4.5
-
-
7.5
-
-
-
15
S
-
-
60
TJ = 25 °C, IS = 15 A, VGS = 0 Vb
-
-
2.5
-
150
200
ns
-
0.93
1.4
μC
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
td(off)
VGS = 5.0 V
ID = 15 A, VDS = 80 V,
see fig. 6 and 13b
-
VDD = 50 V, ID = 15 A,
Rg = 12 , RD = 32, see fig. 10b
tf
LD
LS
Between lead,
6 mm (0.25") from
package and center
of die contact
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IF = 15 A, dI/dt = 100 A/μsb
V
Forward Turn-On Time
ton
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
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Document Number: 91342
S11-1055-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL530S, SiHL530S
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC = 175 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91342
S11-1055-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL530S, SiHL530S
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91342
S11-1055-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL530S, SiHL530S
Vishay Siliconix
RD
VDS
VGS
D.U.T.
Rg
+
- VDD
5V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 91342
S11-1055-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL530S, SiHL530S
Vishay Siliconix
L
Vary tp to obtain
required IAS
V(BR)DSS
VDS
tp
VDD
D.U.T
Rg
+
-
IAS
V DD
VDS
5V
0.01 W
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
5V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91342
S11-1055-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL530S, SiHL530S
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91342.
Document Number: 91342
S11-1055-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
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AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
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Document Number: 91000