HIP6004E Data Sheet November 10, 2015 Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor Features The HIP6004E provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive two N-Channel MOSFETs in a synchronous-rectified buck topology. The HIP6004E integrates all of the control, output adjustment, monitoring and protection functions into a single package. • Operates from +5V or +12V Input • Drives two N-Channel MOSFETs The output voltage of the converter is easily adjusted and precisely regulated. The HIP6004E includes a 5-input digitalto-analog converter (DAC) that adjusts the output voltage from 1.05VDC to 1.825VDC in 25mV increments steps. The precision reference and voltage-mode regulator hold the selected output voltage to within 1% over temperature and line voltage variations. The HIP6004E provides simple, single feedback loop, voltage-mode control with fast transient response. It includes a 200kHz free-running triangle-wave oscillator that is adjustable from below 50kHz to over 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 6V/s slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%. The HIP6004E monitors the output voltage with a window comparator that tracks the DAC output and issues a Power Good signal when the output is within 10%. The HIP6004E protects against over-current and overvoltage conditions by inhibiting PWM operation. Additional built-in overvoltage protection triggers an external SCR to crowbar the input supply. The HIP6004E monitors the current by using the rDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. Pinout FN4997.3 • Simple single-loop control design - Voltage-mode PWM control • Fast transient response - High-bandwidth error amplifier - Full 0% to 100% Duty Ratio • Excellent output voltage regulation - 1% Over Line Voltage and Temperature • 5-Bit digital-to-analog output Voltage Selection - 25mV binary steps . . . . . . . . . . . 1.05VDC to 1.825VDC • Power good output voltage monitor • Overvoltage and overcurrent fault monitors - Does not require extra current sensing element, Uses MOSFET’s rDS(ON) • Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator Programmable from 50kHz to over 1MHz • Pb-free available Applications • VRM8.5 modules for Pentium III and Other Microprocessors • High-Power DC-DC Regulators • Low-Voltage Distributed Power Supplies Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” HIP6004E TOP VIEW VSEN 1 OCSET 2 19 OVP SS 3 18 VCC VID25mV 4 17 LGATE VID0 5 16 PGND VID1 6 15 BOOT VID2 7 14 UGATE VID3 8 13 PHASE COMP 9 12 PGOOD 20 RT FB 10 11 GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas LLC. Copyright © Intersil Americas LLC 2001, 2004, 2015. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HIP6004E Ordering Information TEMP. RANGE (oC) PART NUMBER PACKAGE PKG. DWG. # HIP6004ECBZ (See Note) 0 to 70 20 Ld SOIC (Pb-free) M20.3 HIP6004ECVZ (See Note) No longer available or supported, recommended replacement HIP6004ECBZ 0 to 70 20 Ld TSSOP (Pb-free) M20.173 *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. Typical Application +12V VCC VIN = +5V OR +12V HIP6004E PGOOD MONITOR AND PROTECTION SS OVP BOOT RT VID25mV VID0 VID1 VID2 VID3 OCSET OSC UGATE PHASE +VOUT D/A + FB - COMP Block Diagram 2 - LGATE + PGND VSEN GND HIP6004E VCC VSEN POWER-ON RESET (POR) 110% + - 90% PGOOD + - 115% + OVERVOLTAGE 10A OVP - SOFTSTART + - OCSET REFERENCE VID25mV VID0 VID1 VID2 VID3 D/A CONVERTER (DAC) 200A OVERCURRENT BOOT 4V UGATE PWM COMPARATOR DACOUT + - + - ERROR AMP FB SS PHASE GATE INHIBIT CONTROL LOGIC PWM LGATE PGND COMP GND OSCILLATOR RT 3 HIP6004E Absolute Maximum Ratings Thermal Information Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V Boot voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . . .+15V Input, output or I/O voltage . . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal resistance (Typical, Note 1) JA (oC/W) SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TSSOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum storage temperature range . . . . . . . . . . . -65oC to 150oC Maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300oC (lead tips only) Operating Conditions Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Ambient temperature range . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Recommended operating conditions, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS UGATE and LGATE open - 5 - mA Rising VCC threshold VOCSET = 4.5V - - 10.4 V Falling VCC threshold VOCSET = 4.5V 8.2 - - V - 1.26 - V VCC SUPPLY CURRENT Nominal supply ICC POWER-ON RESET Rising VOCSET threshold OSCILLATOR Free running frequency RT = open 185 200 215 kHz Total variation 6k < RT to GND < 200k -15 - +15 % - 1.9 - VP-P V VOSC Ramp amplitude RT = open REFERENCE AND DAC DAC (VID0-VID4) input low voltage - - 0.8 DAC (VID0-VID4) input high voltage 2.0 - - V DACOUT voltage accuracy -1.0 - +1.0 % - 88 - dB - 15 - MHz - 6 - V/s 350 500 - mA ERROR AMPLIFIER DC gain Gain-bandwidth product GBWP Slew rate SR COMP = 10pF GATE DRIVERS Upper gate source IUGATE VBOOT - VPHASE = 12V, VUGATE = 6V Upper gate sink RUGATE ILGATE = 0.3A - 5.5 10 300 450 - mA - 3.5 6.5 - 115 120 % VOCSET = 4.5VDC 170 200 230 A VSEN = 5.5V, VOVP = 0V 60 - - mA - 10 - A VSEN rising 106 - 111 % Lower threshold (VSEN/DACOUT) VSEN falling 89 - 94 % Hysteresis (VSEN/DACOUT) Upper and lower threshold - 2 - % IPGOOD = -5mA - 0.3 - V Lower gate source ILGATE VCC = 12V, VLGATE = 6V Lower gate sink RLGATE ILGATE = 0.3A PROTECTION Overvoltage trip (VSEN/DACOUT) OCSET current source IOCSET OVP sourcing current IOVP Soft start current ISS POWER GOOD Upper threshold (VSEN/DACOUT) PGOOD voltage low VPGOOD 4 HIP6004E Typical Performance Curves 80 CGATE = 3300pF 70 60 RT PULLUP TO +12V ICC (mA) RESISTANCE (k) 1000 100 50 CUPPER = CLOWER = CGATE 40 CGATE = 1000pF 30 10 20 RT PULLDOWN TO VSS CGATE = 10pF 10 10 100 1000 0 100 200 300 SWITCHING FREQUENCY (kHz) FIGURE 1. RT RESISTANCE vs FREQUENCY Functional Pin Descriptions 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY reference (DACOUT). The level of DACOUT sets the converter output voltage. It also sets the PGOOD and OVP thresholds. Table 1 specifies DACOUT for the all combinations of DAC inputs. VSEN 1 OCSET 2 19 OVP SS 3 18 VCC COMP (Pin 9) and FB (Pin 10) VID25mV 4 17 LGATE VID0 5 16 PGND VID1 6 15 BOOT VID2 7 14 UGATE VID3 8 13 PHASE COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. COMP 9 12 PGOOD 20 RT FB 10 11 GND VSEN (Pin 1) This pin is connected to the converter’s output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for overvoltage protection. OCSET (Pin 2) Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 200A current source (IOCSET), and the upper MOSFET on-resistance (rDS(ON)) set the converter overcurrent (OC) trip point according to the following equation: I OCSET x R OCSET I PEAK = ----------------------------------------------------r DS ON GND (Pin 11) Signal ground for the IC. All voltage levels are measured with respect to this pin. PGOOD (Pin 12) PGOOD is an open collector output used to indicate the status of the converter output voltage. This pin is pulled low when the converter output is not within 10%of the DACOUT reference voltage. PHASE (Pin 13) Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for overcurrent protection. This pin also provides the return path for the upper gate drive. UGATE (Pin 14) An over-current trip cycles the soft-start function. SS (Pin 3) Connect a capacitor from this pin to ground. This capacitor, along with an internal 10A current source, sets the soft-start interval of the converter. VID25mV-VID3 (Pins 4-8) VID25mV - VID3 are the input pins to the 5-bit DAC. The states of these five pins program the internal voltage 5 Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. BOOT (Pin 15) This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET. HIP6004E PGND (Pin 16) This is the power ground connection. Tie the lower MOSFET source to this pin. LGATE (Pin 17) Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. VCC (Pin 18) Provide a 12V bias supply for the chip to this pin. OVP (Pin 19) The OVP pin can be used to drive an external SCR in the event of an overvoltage condition. Output rising 15% more than the DAC-set voltage triggers a high output on this pin and disables PWM gate drive circuitry. wave. The oscillator’s triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). This interval of increasing pulse width continues to t2 . With sufficient output voltage, the clamp on the reference input controls the output voltage. This is the interval between t2 and t3 in Figure 3. At t3 the SS voltage exceeds the DACOUT voltage and the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The PGOOD signal toggles ‘high’ when the output voltage (VSEN pin) is within 10% of DACOUT. The 2% hysteresis built into the power good comparators prevents PGOOD oscillation due to nominal output voltage ripple. PGOOD (2V/DIV.) RT (Pin 20) This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: 0V SOFT-START (1V/DIV.) 6 5 x 10 Fs 200kHz + --------------------R T k OUTPUT VOLTAGE (1V/DIV.) (RT to GND) Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation: 0V 0V t1 7 (RT to 12V) t3 Functional Description Initialization The HIP6004E automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage at the VCC pin and the input voltage (VIN) on the OCSET pin. The level on OCSET is equal to VIN less a fixed voltage drop (see overcurrent protection). The POR function initiates soft-start operation after both input supply voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold before POR initiates operation. Soft Start The POR function initiates the soft-start sequence. An internal 10A current source charges an external capacitor (CSS) on the SS pin to 4V. Soft start clamps the error amplifier output (COMP pin) and reference input (+ terminal of error amp) to the SS pin voltage. Figure 3 shows the soft-start interval with CSS = 0.1F. Initially the clamp on the error amplifier (COMP pin) controls the converter’s output voltage. At t1 in Figure 3, the SS voltage reaches the valley of the oscillator’s triangle 6 Overcurrent Protection The overcurrent function protects the converter from a shorted output by using the upper MOSFET’s on-resistance, rDS(ON) to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. SOFT-START RT pin has a constant voltage of 1.26V typically. FIGURE 3. SOFT START INTERVAL 4V 2V 0V OUTPUT INDUCTOR 4 x 10 Fs 200kHz – --------------------R T k t2 TIME (5ms/DIV.) 15A 10A 5A 0A TIME (20ms/DIV.) FIGURE 4. OVER-CURRENT OPERATION The overcurrent function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the overcurrent trip level. An internal 200A current HIP6004E sink develops a voltage across ROCSET that is referenced to VIN . When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET, the overcurrent function initiates a soft-start sequence. The softstart function discharges CSS with a 10A current sink and inhibits PWM operation. The soft-start function recharges CSS , and PWM operation resumes with the error amplifier clamped to the SS voltage. Should an overload occur while recharging CSS , the soft-start function inhibits PWM operation while fully charging CSS to 4V to complete its cycle. Figure 4 shows this operation with an overload condition. Note that the inductor current increases to over 15A during the CSS charging interval and causes an overcurrent trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 4 is 2.5W. The overcurrent function will trip at a peak inductor current (IPEAK) determined by: I OCSET x R OCSET I PEAK = ----------------------------------------------------r DS ON where IOCSET is the internal OCSET current source (200A typical). The OC trip point varies mainly due to the MOSFET’s rDS(ON) variations. To avoid overcurrent tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for I PEAK I OUT MAX + I 2 , where I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled “Output Inductor Selection”. A small, ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage. Output Voltage Program The output voltage of a HIP6004E converter is programmed to discreet levels between 1.05VDC and 1.825VDC . The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a TTL-compatible 5-bit digital-toanalog converter (DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the 32 different combinations of connections on the VID pins. The output voltage should not be adjusted while the converter is delivering power. Remove input power before changing the output voltage. Adjusting the output voltage during operation could toggle the PGOOD signal and exercise the overvoltage protection. Application Guidelines Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short-printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding. TABLE 1. OUTPUT VOLTAGE PROGRAM PIN NAME PIN NAME VID25 mV VID0 NOMINAL OUTPUT VOLTAGE DACOUT VID25 mV VID3 VID2 VID1 VID3 VID2 VID1 VID0 NOMINAL OUTPUT VOLTAGE DACOUT 0 0 1 1 0 1 0 0 1.050 0 1 1 0 0 1.450 0 0 1.075 1 1 1 0 0 1.475 0 0 1 0 0 1 1 1.100 0 1 0 1 1 1.500 0 1 1 1.125 1 1 0 1 1 0 1.525 0 0 1 0 1.150 0 1 0 1 0 1.550 1 0 0 1 0 1.175 1 1 0 1 0 1.575 0 0 0 0 1 1.200 0 1 0 0 1 1.600 1 0 0 0 1 1.225 1 1 0 0 1 1.625 0 0 0 0 0 1.250 0 1 0 0 0 1.650 1 0 0 0 0 1.275 1 1 0 0 0 1.675 0 1 1 1 1 1.300 0 0 1 1 1 1.700 1 1 1 1 1 1.325 1 0 1 1 1 1.725 0 1 1 1 0 1.350 0 0 1 1 0 1.750 1 1 1 1 0 1.375 1 0 1 1 0 1.775 0 1 1 0 1 1.400 0 0 1 0 1 1.800 1 1 1 0 1 1.425 1 0 1 0 1 1.825 NOTE: 0 = connected to GND or VSS , 1 = connected to VDD through pull-up resistors or leave the pins floating. Internal pull-ups will force the floating VID pins to HIGH. 7 HIP6004E PWM COMPARATOR HIP6004E Q1 PHASE Q2 LGATE D2 CIN CO ZFB - Figure 6 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS pin and locate the capacitor, CSS close to the SS pin because the internal current source is only 10A. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. Q1 LO VOUT Q2 CO LOAD +12V CVCC CSS GND FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulsewidth modulated (PWM) wave with an amplitude of VIN at the PHASE node. 8 ZFB C2 C1 VOUT ZIN C3 R2 R3 R1 COMP FB + HIP6004E DACOUT FIGURE 7. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR . The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC . Modulator Break Frequency Equations +VIN PHASE VCC REFERENCE DETAILED COMPENSATION COMPONENTS Figure 5 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 5 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the HIP6004E within 3 inches of the MOSFETs, Q1 and Q2 . The circuit traces for the MOSFETs’ gate and source connections from the HIP6004E must be sized to handle up to 1A peak current. CBOOT CO ZIN ERROR AMP RETURN D1 PHASE ESR (PARASITIC) + BOOT VOUT VE/A FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS SS DRIVER + VOUT PGND HIP6004E LO - VOSC LO LOAD UGATE VIN DRIVER OSC VIN 1 F LC = ------------------------------------------2 x L O x C O 1 F ESR = -------------------------------------------2 x ESR x C O The compensation network consists of the error amplifier (internal to the HIP6004E) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180degrees The equations below relate the compensation network’s poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 7. Use these guidelines for locating the poles and zeros of the compensation network: 1. 2. 3. 4. 5. 6. 7. Pick Gain (R2/R1) for desired converter bandwidth. Place 1ST Zero Below Filter’s Double Pole (~75% FLC). Place 2ND Zero at Filter’s Double Pole. Place 1ST Pole at the ESR Zero. Place 2ND Pole at Half the Switching Frequency. Check Gain against Error Amplifier’s Open-Loop Gain. Estimate Phase Margin - Repeat if Necessary. HIP6004E Compensation Break Frequency Equations 1 F Z1 = -----------------------------------2 x R 2 x C 1 1 F P1 = -------------------------------------------------------- C 1 x C 2 2 x R 2 x ---------------------- C1 + C2 1 F Z2 = ------------------------------------------------------2 x R 1 + R 3 x C 3 1 F P2 = -----------------------------------2 x R 3 x C 3 Figure 8 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 8. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 8 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. 100 FZ1 FZ2 FP1 FP2 80 OPEN LOOP ERROR AMP GAIN GAIN (dB) 60 40 20 20LOG (R2/R1) 0 COMPENSATION GAIN -40 -60 CLOSED LOOP GAIN FLC 10 100 1K FESR 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN Component Selection Guidelines Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. 9 High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large-case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: I = 20LOG (VIN/VOSC) MODULATOR GAIN -20 The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. VIN - VOUT Fs x L x VOUT VIN VOUT = I x ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the HIP6004E will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT HIP6004E where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst-case response time can be either at the application or removal of load and dependent upon the DACOUT setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. With a +12V input, and output voltage level equal to DACOUT, tFALL is the longest response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high-frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2 . The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. PUPPER = Io2 x rDS(ON) x D + PLOWER = Io2 x rDS(ON) x (1 - D) Where: D is the duty cycle = VOUT / VIN , tSW is the switch ON time, and FS is the switching frequency. Standard-gate MOSFETs are normally recommended for use with the HIP6004E. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFET’s absolute gate-tosource voltage rating determine whether logic-level MOSFETs are appropriate. Figure 9 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC. The boot capacitor, CBOOT develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle to a voltage of VCC less the boot diode drop (VD) when the lower MOSFET, Q2 turns on. Logic-level MOSFETs can only be used if the MOSFET’s absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC. For a through-hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. +12V VCC In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the upper MOSFET has switching losses, since the Schottky rectifier clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltage current transitions and do not adequately model power loss due the reverse recovery of the lower MOSFET’s body diode. The gate-charge losses are dissipated by the HIP6004E and don't heat the MOSFETs. However, large gate charge increases the switching interval, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are 10 DBOOT +5V OR +12V + VD BOOT CBOOT HIP6004E UGATE MOSFET Selection/Considerations The HIP6004E requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. 1 Io x V x t IN SW x FS 2 Q1 PHASE - + LGATE PGND NOTE: VG-S VCC -VD Q2 D2 NOTE: VG-S VCC GND FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION Figure 10 shows the upper gate drive supplied by a direct connection to VCC . This option should only be used in converter systems where the main input voltage is +5VDC or less. The peak upper gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. A logiclevel MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC . HIP6004E Schottky Selection +12V Rectifier D2 is a clamp that catches the negative inductor swing during the dead time between turning off the lower MOSFET and turning on the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency will drop one or two percent as a result. The diode’s rated reverse breakdown voltage must be greater than the maximum input voltage. +5V OR LESS VCC BOOT HIP6004E Q1 UGATE PHASE - NOTE: VG-S VCC -5V D2 Q2 LGATE + PGND HIP6004E DC-DC Converter Application Circuit NOTE: VG-S VCC GND Figure 11 shows an application circuit of a DC-DC Converter for a microprocessor. Detailed information on the circuit, including a complete bill-of-materials and circuit board description, can be found in AN9916. This application note also contains the application information for ISL6525, an controller IC designed to meet the VTT voltage and powerup sequencing specification given in the Intel VRM8.5. FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION VIN = +5V OR +12V L1 - 1H F1 1F 2N6394 CIN 3x1000F +12V 2K D1 0.1F 1000pF VCC 18 2 OCSET MONITOR AND PROTECTION SS 3 0.1F OVP 19 12 PGOOD 15 BOOT VSEN 1 RT 20 VID25mV VID0 VID1 VID2 VID3 FB 4 5 6 7 8 1.8K 0.1F OSC 14 UGATE Q1 L2 2.4H 13 PHASE HIP6004E D/A - - Q2 16 PGND 9 470pF 17 LGATE + + 10 COMP D2 +VOUT COUT 5x1000F 11 GND 56K 10nF 0.033F 3.32K 27 Component Selection Notes: COUT - Each 1000F 6.3W VDC, Rubycon ZA series or equivalent. CIN - Each 330F 25W VDC, Rubycon ZA series or equivalent. L2 - Core: micrometals T68-52A; winding: 7 turns of 16AWG. L1 - Core: micrometals T50-52; winding: 5 turns of 16AWG. D1 - 1N4148 or equivalent. D2 - 3A, 40V Schottky, Motorola MBR340 or equivalent. Q1 - Intersil MOSFET; HUF76137. Q2 - Intersil MOSFET; HUF76139. FIGURE 11. MICROPROCESSOR DC-DC CONVERTER 11 HIP6004E Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION November 10, 2015 FN4997.3 CHANGE Added Rev History and About Intersil Verbiage Updated Ordering Information on page 2 Updated POD M20.3 to most current version. Rev changes are as follows: Top View: Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion) Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion) Side View: Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion) Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion) Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994" Updated to new POD format by moving dimensions from table onto drawing and adding land pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support All Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 HIP6004E Thin Shrink Small Outline Plastic Packages (TSSOP) M20.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M L A D -C- e A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE A2 c 0.10(0.004) C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 13 MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.252 0.260 6.40 6.60 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX 20 0o 20 7 8o Rev. 1 6/98 HIP6004E Package Outline Drawing M20.3 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 3, 2/11 20 INDEX AREA 7.60 7.40 1 2 10.65 10.00 0.25 (0.10) M B M 3 3 TOP VIEW 13.00 12.60 SEATING PLANE 2 2.65 2.35 5 0.75 1.27 BSC 0.49 0.35 7 0.25 (0.10) M 0.25 0.30 MAX C A M B S 1.27 0.40 x 45° 8° MAX 0.10 (0.004) SIDE VIEW DETAIL "X" 0.32 0.23 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. (0.60) 1.27 BSC 2. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 20 (2.00) 3. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. (9.40mm) 5. Dimension is the length of terminal for soldering to a substrate. 6. Terminal numbers are shown for reference only. 7. The lead width as measured 0.36mm (0.14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 8. Controlling dimension: MILLIMETER. 1 2 3 9. Dimensions in ( ) for reference only. TYPICAL RECOMMENDED LAND PATTERN 14 10. JEDEC reference drawing number: MS-013-AC.