DATASHEET N-Channel 60V Power MOSFET for Soft Switching KGF4N60 Features The KGF4N60 is a 60V, 33mΩ, chip scale, N-channel lateral MOSFET. The device uses technology that uniquely integrates low cost CMOS and WLCSP fabrication processes. The chip scale package offers small area, low vertical profile and is fully compatible with standard SMT assembly processes. The KGF4N60 device offers unprecedented low ON-resistance and total gate charge, outperforming conventional trench MOSFETs and enabling high frequency, low voltage switching. The device offers extremely high power density, reducing the board size of DC/DC converters and other power management systems. • Industry leading figures of merit: rDS(ON) × Qg and rDS(ON) × Qgd • High frequency switching • Known Good FET (KGF) quality assurance process • Low thermal resistance Applications • Point-of-load DC/DC converters • Portable electronics PRODUCT SUMMARY • OR’ing diodes ID TA = +25°C 4A Maximum V(BR)DSS ID = 250µA 60V Minimum rDS(ON) VGS = 5V 33mΩ Typical Qg ID = 12A 2.5nC Typical 0.53nC Typical Qgd • Low profile/small footprint chip scale WLCSP package Related Literature • AN1968, “Unclamped Inductive Switching (UIS) Test and Rating Methodology” D G S FIGURE 1. EQUIVALENT CIRCUIT February 2, 2016 FN8811.0 1 FIGURE 2. N-CHANNEL MOSFET CHIP SCALE WLCSP PACKAGE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. KGF4N60 Ordering Information PART NUMBER TEMP RANGE (°C) PART MARKING KGF4N60 H Pin Configuration 6 Bump WLCSP Pin Descriptions KGF4N60 (6 BUMP WLCSP) LAND GRID ARRAY VIEW 5 S 1 G -55 to +150 PACKAGE (RoHS Compliant) PIN # PIN NAME DESCRIPTION 1 G Gate of MOSFET 2, 3, 4, 5 S Source of MOSFET 6 D Drain of MOSFET 6 4 S D S 2 S 3 Submit Document Feedback 2 FN8811.0 February 2, 2016 KGF4N60 Absolute Maximum Ratings Thermal Information (Note 1) Drain-to-Source Voltage (VDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V Gate-to-Source Voltage (VGS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V Drain Current Continuous (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4A Pulsed (IDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40A Single Pulse Avalanche Current (IAS) L ≤ 300µH, RG ≤ 25Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4A Thermal Resistance (Typical) (Note 2) JA (°C/W) JP (°C/W) WLCSP Package . . . . . . . . . . . . . . . . . . . . . . 50 10 Maximum Power Dissipation (PD) (Note 2) TA = +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W TA = +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6W Junction and Storage Temperature Range (TJ, Tstg). . . . .-55°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. TJ = +25°C unless otherwise noted. 2. When mounted on 1 inch square 2oz copper clad FR-4. Electrical Characteristics SYMBOL V(BR)DSS IDSS TJ = +25°C unless otherwise noted. PARAMETER TEST CONDITIONS MIN (Note 3) TYP (Note 4) MAX (Note 3) UNIT Drain-to-Source Breakdown Voltage VGS = 0V, ID = 250µA Zero Gate Voltage Drain Current VDS = 48V, VGS = 0V, TJ = +25°C 60 1 µA V VDS = 60V, VGS = 0V, TJ = +25°C 25 µA VDS = 60V, VGS = 0V, TJ = +125°C 250 µA 150 nA IGSS Gate-to-Body Leakage VGS = 15V, VDS = 0V VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA 1.8 V rDS(ON) Drain-to-Source On-State Resistance VGS = 5V, ID = 4A 33 mΩ Ciss Input Capacitance VDS = 60V, VGS = 0V, f = 1MHz 215 pF Coss Output Capacitance 205 pF Crss Reverse Transfer Capacitance 2.5 pF Ciss Input Capacitance 245 pF Coss Output Capacitance 640 pF Crss Reverse Transfer Capacitance 35 pF VDS = 0V, VGS = 0V, f = 1MHz rg Gate Resistance VDS = 0V, f = 1MHz 1.0 Ω Qg Total Gate Charge VGS = 5V, ID = 4A, VDS = 48V 2.5 nC Qgs Gate-to-Source Charge 0.99 nC Qgd Gate-to-Drain Charge 0.53 nC 42 ns trr VSD Source-to-Drain Reverse Recovery Time IS = 4A, di/dt = 33A/µs Diode Forward Voltage IS = 4A, VGS = 0V 0.65 1.00 V NOTES: 3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 4. Typical values are for TA = +25°C. Submit Document Feedback 3 FN8811.0 February 2, 2016 KGF4N60 Typical Performance Curves 25 10 VGS = 10V TO 3V VGS = 3V 8 ID - DRAIN CURRENT (A) ID - DRAIN CURRENT (A) 9 7 6 5 VGS = 2.75V 4 3 2 20 15 10 TJ = +1 25°C 5 0 0 0.0 2.0 4.0 6.0 8.0 10.0 0.0 0.5 1.0 1.5 FIGURE 3. OUTPUT CHARACTERISTICS 2 .5 3.0 3.5 4.0 4.5 5.0 FIGURE 4. TRANSFER CHARACTERISTICS 50 1.6 rDS(ON) - ON-STATE RESISTANCE (NORMALIZED) rDS(ON) - ON-STATE RESISTANCE (Ω) 2.0 VGS - GATE-TO -SOURCE (V) VDS - DRAIN-TO-SOURCE VOLTAGE (V) 45 40 VGS = 5V 35 30 25 20 1.5 1.4 1.3 VGS = 5V I D = 4A 1.2 1.1 1.0 0.9 0.8 0.7 0.6 15 0.0 2.0 4.0 6.0 8.0 -60 10.0 -4 0 I D - DR AIN CURRENT (A) 180 160 140 I D = 4A 100 80 60 40 20 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 VGS - GATE-TO-SOURCE VOLTAGE (V) FIGURE 7. DRAIN-TO-SOURCE ON-RESISTANCE vs GATE-TO-SOURCE VOLTAGE Submit Document Feedback 4 0 20 40 60 80 100 120 140 160 FIGURE 6. DRAIN TO SOURCE ON-RESISTANCE vs JUNCTION TEMPERATURE VGS(th) - GATE THRESHOLD VOLTAGE (NORMALIZED) 200 120 -20 TJ - JUNCTION TEMPERATURE (°C) FIGURE 5. DRAIN-TO-SOURCE ON-RESISTANCE vs DRAIN CURRENT rDS(ON) - ON-STATE RESISTANCE (mΩ) TJ = -55°C TJ = +25°C 1 1.5 1.4 1.3 1.2 1.1 I D = 250µA 1.0 0.9 0.8 0.7 0.6 0.5 0.4 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ - JUNCTION TEMPERATURE (°C) FIGURE 8. GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FN8811.0 February 2, 2016 KGF4N60 IS - SOURCE CURRENT (A) 100 .0 10.0 TJ = +125°C TJ = +25°C 1.0 0.1 0.2 0.4 0.6 0.8 1.0 1.2 V(BR)DSS - DRAIN-TO-SOURCE VOLTAGE (NORMALIZED) Typical Performance Curves (Continued) 1.20 1.15 1.10 I D = 250µA 1.05 1.00 0.95 0.90 0.85 0.80 -60 -40 -20 VSD - SOURCE-TO-DRAIN VOLTAGE (V) 0 20 40 60 80 100 120 140 160 TJ - JUNCTION TEMPERATURE (°C) FIGURE 9. SOURCE-TO-DRAIN BREAKDOWN DIODE FOWARD VOLTAGE FIGURE 10. DRAIN-TO-SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE C oss 4.5 VDS = 48V I D = 4A 4.0 C - CAPACITANCE (pF) VGS - GATE-TO-SOURCE VOLTAGE (V) 100 0 5.0 3.5 3.0 2.5 2.0 1.5 C iss 100 C rss 10 1.0 0.5 1 0.0 0 0.0 0.5 1.0 1.5 2.0 2.5 Qg - TOTAL GATE CHARGE (nC) 3.0 10 20 30 40 50 60 VDS - DRAIN-TO-SOURCE VOLTAGE (V) FIGURE 11. GATE CHARGE FIGURE 12. CAPACITANCE 100 .00 ID - DRAIN CURRENT (A) r DS(ON) LIMITED VGS = 5V 10.00 100µs 1ms 1.00 10ms 100ms 0.10 rDS(ON) LIMIT PACKAGE LIMIT THERMAL LIMIT TA = +25o C, SINGLE PULSE 0.01 0.10 1.00 10.00 DC 100 .00 VDS - DRAIN-TO-SOURCE VOLTAG E (V) FIGURE 13. MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA Submit Document Feedback 5 FN8811.0 February 2, 2016 KGF4N60 r(t) - TRANSIENT THERMAL RESISTANCE Typical Performance Curves (Continued) 1.00 0.50 0.20 0.10 0.10 0.05 0.02 SINGLE PULSE 0.01 100 E-6 1E- 3 10E -3 100 E-3 1E+0 10E +0 100 E+0 1E+3 TIME (s) FIGURE 14. TRANSIENT THERMAL RESPONSE, JUNCTION-TO-AMBIENT Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION February 2, 2016 FN8811.0 CHANGE Initial release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. Submit Document Feedback 6 FN8811.0 February 2, 2016 KGF4N60 Dimensional Outline and Pad Layout 0.18 0.465 0.285 R 0.35 0.2 0.645 R 0.05 0.285 0.4 0.464 0.182 0.928 0.4 0.4 0.464 0.646 0.464 0.2 45° 0.271 0.083 0.271 0.934 0.467 0.467 0.052 All Dimensions in mm DIE SIZE = 1.47mm ±0.005mm (SQUARE) PAD THICKNESS = 3µm NiAu DIE THICKNESS = 400µm ±15µm For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 7 FN8811.0