SiHG14N50D www.vishay.com Vishay Siliconix D Series Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • Optimal Design - Low Area Specific On-Resistance - Low Input Capacitance (Ciss) - Reduced Capacitive Switching Losses - High Body Diode Ruggedness - Avalanche Energy Rated (UIS) • Optimal Efficiency and Operation - Low Cost - Simple Gate Drive Circuitry - Low Figure-of-Merit (FOM): Ron x Qg - Fast Switching • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 550 RDS(on) max. at 25 °C () VGS = 10 V 0.4 Qg (Max.) (nC) 58 Qgs (nC) 8 Qgd (nC) 14 Configuration Single D TO-247AC G Note * Lead (Pb)-containing terminations are not RoHS-compliant. Exemptions may apply. S D S G APPLICATIONS N-Channel MOSFET • Consumer Electronics - Displays (LCD or Plasma TV) • Server and Telecom Power Supplies - SMPS • Industrial - Welding, Induction Heating, Motor Drives • Battery Chargers ORDERING INFORMATION Package TO-247AC Lead (Pb)-free SiHG14N50D-E3 Lead (Pb)-free and Halogen-free SiHG14N50D-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage Pulsed Drain LIMIT VDS 500 VGS Gate-Source Voltage AC (f > 1 Hz) Continuous Drain Current (TJ = 150 °C) SYMBOL VGS at 10 V TC = 25 °C TC = 100 °C Currenta ID IDM Linear Derating Factor ± 30 UNIT V 30 14 9 A 38 1.6 W/°C mJ Single Pulse Avalanche Energyb EAS 56 Maximum Power Dissipation PD 208 W TJ, Tstg - 55 to + 150 °C Operating Junction and Storage Temperature Range Drain-Source Voltage Slope TJ = 125 °C Reverse Diode dV/dtd Soldering Recommendations (Peak Temperature) for 10 s dV/dt 24 0.4 300c V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 , IAS = 7 A. c. 1.6 mm from case. d. ISD ID, starting TJ = 25 °C. S12-1229-Rev. A, 21-May-12 Document Number: 91513 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG14N50D www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Maximum Junction-to-Case (Drain) SYMBOL TYP. MAX. UNIT RthJA RthJC - 62 0.6 °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) VDS VGS = 0 V, ID = 250 μA 500 - - V VDS/TJ Reference to 25 °C, ID = 250 μA - 0.58 - V/°C VGS(th) VDS = VGS, ID = 250 μA 3.0 - 5.0 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 500 V, VGS = 0 V - - 1 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 10 Drain-Source On-State Resistance Forward Transconductancea RDS(on) gfs VGS = 10 V ID = 7 A VDS = 50 V, ID = 7 A μA - 0.320 0.40 - 5.2 - S Dynamic Input Capacitance Ciss VGS = 0 V, - 1144 - Output Capacitance Coss VDS = 100 V, - 100 - Reverse Transfer Capacitance Crss f = 1 MHz - 12 - Effective Output Capacitance, Energy relateda Co(er) - 87 - Effective Output Capacitance, Time relatedb Co(tr) - 125 - pF VGS = 0 V, VDS = 0 V to 400 V Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 7 A, VDS = 400 V - 29 58 - 8 - - 14 - - 16 32 nC VDD = 400 V, ID = 7 A Rg = 9.1 , VGS = 10 V - 27 54 - 29 58 - 26 52 f = 1 MHz, open drain - 1.7 - - - 14 - - 56 - - 1.2 V - 319 - ns - 3.0 - μC - 18 - A ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 7 A, VGS = 0 V TJ = 25 °C, IF = IS = 7 A, dI/dt = 100 A/μs, VR = 20 V S Note a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S12-1229-Rev. A, 21-May-12 Document Number: 91513 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG14N50D www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V 30 3 TJ = 25 °C ID = 7 A RDS(on), Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 40 20 10 2.5 2 1.5 0.5 5.0 V 0 0 5 10 15 20 25 VGS = 10 V 1 0 - 60 - 40 - 20 0 30 Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics 30 10 000 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTYTOM 5.0 V 18 TJ = 150 °C C iss Capacitance (pF) ID, Drain-to-Source Current (A) TOP 24 12 1000 VGS = 0 V, f = 1 MHz C iss = C gs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 100 Coss 10 6 Crss 5.0 V 1 0 0 5 10 15 20 25 30 0 VDS, Drain-to-Source Voltage (V) 100 200 24 VGS, Gate-to-Source Voltage (V) 30 20 TJ = 150 °C 400 500 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 40 10 300 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics ID, Drain-to-Source Current (A) 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) VDS, Drain-to-Source Voltage (V) TJ = 25 °C VDS = 400 V VDS = 250 V VDS = 100 V 20 16 12 8 4 0 0 0 5 10 15 20 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S12-1229-Rev. A, 21-May-12 25 0 10 20 30 40 50 Qg, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91513 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG14N50D www.vishay.com Vishay Siliconix 100 10 ID, Drain Current (A) ISD, Reverse Drain Current (A) 16 TJ = 150 °C 1 TJ = 25 °C 12 8 4 VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 VSD, Source-Drain Voltage (V) 25 50 75 100 125 150 TJ, Case Temperature (°C) Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature 1000 625 ID, Drain Current (A) 600 VDS, Drain-to-Source Brakdown Voltage (V) Operation in this Area Limited by RDS(on) 100 IDM = Limited 10 100 μs Limited by RDS(on)* 1 ms 1 TC = 25 °C TJ = 150 °C Single Pulse 0.1 1 10 ms 550 525 500 BVDSS Limited 10 100 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is s Fig. 8 - Maximum Safe Operating Area Normalized Effective Transient Thermal Impedance 575 475 - 60 - 40 - 20 0 1000 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 10 - Typical Drain-to-Source Voltage vs. Temperature 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case S12-1229-Rev. A, 21-May-12 Document Number: 91513 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG14N50D www.vishay.com V DS RD V DS V GS Vishay Siliconix tp V DD D.U.T. RG + - V DD V DS 10 V Pulse width ≤ 1 μs Duty factor ≤ 0.1 % IAS Fig. 12 - Switching Time Test Circuit Fig. 15 - Unclamped Inductive Waveforms V DS 90 % QG 10 V QGS 10 % V GS QGD VG td(on) td(off) tr tf Charge Fig. 13 - Switching Time Waveforms Fig. 16 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. L Vary t p to obtain required IAS VDS 50 kΩ D.U.T. RG + - I AS 12 V 0.2 μF 0.3 μF V DD + D.U.T. - VDS 10 V tp 0.01 Ω VGS 3 mA Fig. 14 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 17 - Gate Charge Test Circuit S12-1229-Rev. A, 21-May-12 Document Number: 91513 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG14N50D www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 18 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91513. S12-1229-Rev. A, 21-May-12 Document Number: 91513 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-247AC (High Voltage) A A 4 E B 3 R/2 E/2 7 ØP Ø k M DBM A2 S (Datum B) ØP1 A D2 Q 4 4 2xR (2) D1 D 1 2 4 D 3 Thermal pad 5 L1 C L A See view B 2 x b2 3xb 0.10 M C A M 4 E1 0.01 M D B M View A - A C 2x e A1 b4 Planting Lead Assignments 1. Gate 2. Drain 3. Source 4. Drain D DE (b1, b3, b5) Base metal E C (c) C c1 (b, b2, b4) (4) Section C - C, D - D, E - E View B MILLIMETERS DIM. MIN. MAX. A 4.58 5.31 A1 2.21 2.59 A2 1.17 2.49 b 0.99 1.40 b1 0.99 1.35 b2 1.53 2.39 b3 1.65 2.37 b4 2.42 3.43 b5 2.59 3.38 c 0.38 0.86 c1 0.38 0.76 D 19.71 20.82 D1 13.08 ECN: X13-0103-Rev. D, 01-Jul-13 DWG: 5971 INCHES MIN. MAX. 0.180 0.209 0.087 0.102 0.046 0.098 0.039 0.055 0.039 0.053 0.060 0.094 0.065 0.093 0.095 0.135 0.102 0.133 0.015 0.034 0.015 0.030 0.776 0.820 0.515 - DIM. D2 E E1 e Øk L L1 N ØP Ø P1 Q R S MILLIMETERS MIN. MAX. 0.51 1.30 15.29 15.87 13.72 5.46 BSC 0.254 14.20 16.25 3.71 4.29 7.62 BSC 3.51 3.66 7.39 5.31 5.69 4.52 5.49 5.51 BSC INCHES MIN. MAX. 0.020 0.051 0.602 0.625 0.540 0.215 BSC 0.010 0.559 0.640 0.146 0.169 0.300 BSC 0.138 0.144 0.291 0.209 0.224 0.178 0.216 0.217 BSC Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Contour of slot optional. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions D1 and E1. 5. Lead finish uncontrolled in L1. 6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154"). 7. Outline conforms to JEDEC outline TO-247 with exception of dimension c. 8. Xian and Mingxin actually photo. Revision: 01-Jul-13 Document Number: 91360 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000