SiHS36N50D www.vishay.com Vishay Siliconix D Series Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • Optimal Design - Low Area specific On-Resistance - Low Input Capacitance (Ciss) - Reduced Capacitive Switching Losses - High Body Diode Ruggedness - Avalanche Energy Rated (UIS) • Optimal Efficiency and Operation - Low Cost - Simple Gate Drive Circuitry - Low Figure-Of-Merit (FOM): Ron x Qg - Fast Switching • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 550 RDS(on) max. at 25 °C () VGS = 10 V 0.130 Qg max. (nC) 125 Qgs (nC) 23 Qgd (nC) 37 Configuration Single D Super-247 S D G G APPLICATIONS • Consumer Electronics - Displays (LCD or Plasma TV • Server and Telecom Power Supplies - SMPS • Industrial - Welding, Induction Heating, Motor Drives • Battery Chargers S N-Channel MOSFET ORDERING INFORMATION Package Super-247 Lead (Pb)-free SiHS36N50D-E3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage LIMIT VDS 500 VGS Gate-Source Voltage AC (f > 1 Hz) Continuous Drain Current (TJ = 150 °C) SYMBOL VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID Maximum Power Dissipation Operating Junction and Storage Temperature Range Drain-Source Voltage Slope TJ = 125 °C Reverse Diode dV/dtd Soldering Recommendations (Peak Temperature) for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 , IAS = 17 A. c. 1.6 mm from case. d. ISD ID, starting TJ = 25 °C. S12-1457-Rev. A, 18-Jun-12 V 30 36 23 A IDM 112 3.6 W/°C EAS 332 mJ Linear Derating Factor Single Pulse Avalanche Energyb ± 30 UNIT PD 446 W TJ, Tstg - 55 to + 150 °C dV/dt 24 0.1 300c V/ns °C Document Number: 91514 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHS36N50D www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 0.28 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate Threshold Voltage (N) Gate-Source Leakage Zero Gate Voltage Drain Current VDS VGS = 0 V, ID = 250 μA 500 - - V VDS/TJ Reference to 25 °C, ID = 250 μA - 0.52 - V/°C VGS(th) VDS = VGS, ID = 250 μA 3.0 - 5.0 V nA VGS = ± 30 V - - ± 100 VDS = 500 V, VGS = 0 V - - 1 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 10 IGSS IDSS μA - 0.105 0.130 gfs VDS = 50 V, ID = 18 A - 12.8 - S Input Capacitance Ciss 3233 - Coss - 285 - Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 100 V, f = 1 MHz - Output Capacitance - 25 - Effective Output Capacitance, Energy Relateda Co(er) - 240 - Effective Output Capacitance, Time Relatedb Co(tr) - 352 - Qg - 83 125 - 23 - - 37 - Drain-Source On-State Resistance Forward Transconductancea RDS(on) VGS = 10 V ID = 18 A Dynamic Total Gate Charge pF VGS = 0 V, VDS = 0 V to 400 V VGS = 10 V Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) - 33 66 tr - 89 134 - 79 119 Rise Time Turn-Off Delay Time td(off) Fall Time tf Gate Input Resistance Rg ID = 18 A, VDS = 400 V VDD = 400 V, ID = 18 A, VGS = 10 V, Rg = 9.1 f = 1 MHz, open drain nC ns - 68 102 - 1.8 - - - 36 - - 144 - - 1.2 - 490 - ns - 8.2 - μC - 31 - A Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 18 A, VGS = 0 V TJ = 25 °C, IF = IS = 18 A, dI/dt = 100 A/μs, VR = 20 V V Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S12-1457-Rev. A, 18-Jun-12 Document Number: 91514 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHS36N50D www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 90 3 TJ = 25 °C ID = 18 A RDS(on), Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 120 60 30 2.5 2 1.5 1 0.5 0 - 60 - 40 - 20 0 0 0 5 10 15 20 25 30 TJ, Junction Temperature (°C) Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 10 000 TJ = 150 °C Ciss Capacitance (pF) ID, Drain-to-Source Current (A) TOP 40 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 1000 Coss 100 20 Crss 10 1 0 0 5 10 15 20 25 30 0 VDS, Drain-to-Source Voltage (V) 100 200 400 500 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 24 VGS, Gate-to-Source Voltage (V) 120 TJ = 25 °C 90 60 300 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics ID, Drain-to-Source Current (A) 20 40 60 80 100 120 140 160 VDS, Drain-to-Source Voltage (V) 80 60 VGS = 10 V TJ = 150 °C 30 VDSS = 400 V VDS = 250 V VDSS = 100 V 20 16 12 8 4 0 0 0 5 10 15 20 25 0 30 60 90 120 150 VGS, Gate-to-Source Voltage (V) Qg, Total Gate Charge (nC) Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage S12-1457-Rev. A, 18-Jun-12 Document Number: 91514 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHS36N50D www.vishay.com Vishay Siliconix 40 ID, Drain Current (A) ISD, Reverse Drain Current (A) 1000 ġ 100 ġ TJ = 150 °C ġ 10 TJ = 25 °Cġġ ġ 1 30 20 10 VGS = 0 Vġ ġ 0.1 ġ 0.2 0 0.4 0.6 0.8 1 1.2 1.4 1.6 25 VSD, Source-Drain Voltage (V) 100 125 150 Fig. 9 - Maximum Drain Current vs. Case Temperature 1000 625 IDM = Limited Operation in this Area Limited by RDS(on) VDS, Drain-to-Source Brakdown Voltage (V) 600 100 ID, Drain Current (A) 75 TJ, Case Temperature (°C) Fig. 7 - Typical Source-Drain Diode Forward Voltage Limited by RDS(on)* 10 100 μs 1 ms 1 TC = 25 °C TJ = 150 °C Single Pulse 10 ms BVDSS Limited 10 100 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is s 550 525 475 1000 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 8 - Maximum Safe Operating Area Normalized Effective Transient Thermal Impedance 575 500 0.1 1 50 Fig. 10 - Temperature vs. Drain-to-Source Voltage 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 Single Pulse 0.02 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case S12-1457-Rev. A, 18-Jun-12 Document Number: 91514 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHS36N50D www.vishay.com Vishay Siliconix RD V DS QG 10 V V GS D.U.T. RG QGS + - V DD QGD VG 10 V Pulse width ≤ 1 μs Duty factor ≤ 0.1 % Charge Fig. 16 - Basic Gate Charge Waveform Fig. 12 - Switching Time Test Circuit Current regulator Same type as D.U.T. V DS 90 % 50 kΩ 12 V 0.2 μF 0.3 μF + 10 % V GS D.U.T. td(on) td(off) tr tf - VDS VGS 3 mA Fig. 13 - Switching Time Waveforms IG ID Current sampling resistors Fig. 17 - Gate Charge Test Circuit L Vary t p to obtain required IAS VDS D.U.T. RG + - I AS V DD 10 V 0.01 Ω tp Fig. 14 - Unclamped Inductive Test Circuit V DS tp V DD V DS IAS Fig. 15 - Unclamped Inductive Waveforms S12-1457-Rev. A, 18-Jun-12 Document Number: 91514 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHS36N50D www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 18 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91514. S12-1457-Rev. A, 18-Jun-12 Document Number: 91514 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-274AA (HIGH VOLTAGE) B A E E4 A D2 E1 A1 R D1 D L1 L Detail “A” C b e A2 0.10 (0.25) M B A M 10° b4 b2 Lead Tip 5° Detail “A” Scale: 2:1 MILLIMETERS DIM. MIN. MAX. INCHES MIN. MAX. MILLIMETERS DIM. MIN. MAX. INCHES MIN. MAX. A 4.70 5.30 0.185 0.209 D1 15.50 16.10 0.610 0.634 A1 1.50 2.50 0.059 0.098 D2 0.70 1.30 0.028 0.051 A2 2.25 2.65 0.089 0.104 E 15.10 16.10 0.594 0.634 b 1.30 1.60 0.051 0.063 E1 13.30 13.90 0.524 0.547 b2 1.80 2.20 0.071 0.087 e b4 3.00 3.25 0.118 0.128 L 13.70 14.70 0.539 0.579 c 0.80 1.20 0.031 0.047 L1 1.00 1.60 0.039 0.063 D 19.80 20.80 0.780 0.819 R 2.00 3.00 0.079 0.118 5.45 BSC 0.215 BSC ECN: S-82247-Rev. A, 06-Oct-08 DWG: 5975 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outer extremes of the plastic body. 3. Outline conforms to JEDEC outline to TO-274AA. Document Number: 91365 Revision: 06-Oct-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000