DATASHEET

Flexible Double-Ended Voltage-Mode PWM Controller
with Voltage Feed Forward
ISL6740A
Features
The ISL6740A is an enhanced ISL6740 PWM controller
featuring built-in voltage feed forward functionality. It is pin
and feature compatible with the ISL6740 double-ended pulse
width modulating (PWM) voltage-mode controller, allowing
easy drop-in replacement on existing designs.
• Input Voltage Feed Forward Compensation
Voltage feed forward compensates for input voltage variation
without intervention of the feedback control loop. It is
particularly useful in unregulated bus converters and DC
transformers where wide input voltage variation would
otherwise result in large output voltage swings.
• Adjustable Oscillator Frequency Up to 2MHz
In addition to voltage feed forward compensation, the
ISL6740A features an extremely flexible oscillator that allows
precise control of frequency, duty cycle, and deadtime.
Deadtimes of under 40ns are easily achievable.
This advanced BiCMOS design features low operating current,
adjustable switching frequency up to 1MHz, adjustable
soft-start, internal and external over-temperature protection,
fault annunciation, and a bidirectional SYNC signal that allows
the oscillator to be locked to paralleled units or to an external
clock for noise sensitive applications.
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
ISL6740AIVZA
• Precision Duty Cycle and Deadtime Control
• Adjustable Delayed Overcurrent Shutdown and Re-Start
• Adjustable Short Circuit Shutdown and Re-Start
• Bidirectional Synchronization
• Adjustable Input Undervoltage Lockout/Inhibit
• Tight Tolerance Voltage Reference Over Line, Load, and
Temperature
• Adjustable Soft-Start
• Fault Signal
• 95µA Startup Current
• Internal Over-Temperature Protection
• System Over-Temperature Protection Using a Thermistor or
Sensor
• Pb-free and ELV, WEEE, RoHS Compliant
Applications
• Telecom and Datacom Power
• Wireless Base Station Power
PART
MARKING
6740 AIVZ
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
-40 to +105 16 Ld TSSOP M16.173
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL6740A. For more information on MSL please see
techbrief TB363.
• File Server Power
• Industrial Power Systems
• DC Transformers and Bus Converters
Pin Configuration
ISL6740A
(16 LD TSSOP)
TOP VIEW
OUTA 1
16 OUTB
GND 2
15 VREF
SCSET 3
CT 4
13 RTD
SYNC 5
12 RTC
CS 6
11 OTS
VERROR 7
UV/FF 8
February 9, 2012
FN9195.3
1
14 VDD
10 FAULT
9 SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2005, 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
VREF
VDD
SYNC
FL
VREF
5.00 V
1%
100
OUTA
Q
ENABLE
+
-
T
Q
BG +-
OUTB
PWM TOGGLE
4.5 k
2
GND
SC S/D
Internal
OT Shutdown
130 - 150 C
Bi-Directional
Synchronization
UV/FF
VREF
S
Q
R
Q
70μA
SYNC IN
SS LOW
INHIBIT/VIN UV
1.00 V
OC S/D
N_SYNC OUT
ON
SC LATCH
+
-
INHIBI
T
EXT. SYNC
SS
SS DONE
RTC
15μA
OC LATCH
-
Oscillator
S
Q
R
Q
+
300k
4.5 V
IRTD
RTD
SS CLAMP
CLK
SCSET
Short Circuit
Detection
SS HI
CT
+
-
Q
SS DONE
4.25 V
Q
50µs
RETRIGGERABLE
ONE SHOT
SS LOW
INHIBIT
CS
0.6 V
+
-
S
0.4
+
-
PWM
COMPARATOR
Q
Q
PWM LATCH
RESET
DOMINANT
0.27 V
+
-
FAULT LATCH
SET DOMINANT
OC DETECT
R
S
Q
R
Q
FAULT
VREF
SS
0.4
VREF UV 4.65 V
0.5
VREF/2
+
FL
SC S/D
OC S/D
VERROR
OTS
ISL6740A
IRTC
+
BG +-
FN9195.3
February 9, 2012
Typical Application - 48V Input Bus Converter, 9V @ 10A Output
VIN+
+9V
Q1
QR1
T1
C2
C11
L1
RTN
3
C1
T2
QR2
Q2
R2
36-75V
CR1
CR2
ISL6740A
C3
R1
U1
R12
LO 8
1 VDD
3 HO
4 HS
HIP2101
2 HB
R13
VSS 7
LI 6
HI 5
SYNC
C5
U3
C4
VINR3
1 OUTA
OUTB 16
2 GND
VREF 15
VDD 14
3 SCSET
5 SYNC
R4
6 CS
ISL6740A
4 CT
7 VERROR
R5
Q3
R11
RTD 13
RTC 12
OTS 11
FAULT 10
8 UV/FF
FAULT
SS 9
R8
RT1
FN9195.3
February 9, 2012
VR1
R6
R7
C6
C7
C8
C9
C10
R9
R10
Typical Application - 36 to 75 V Input, Regulated 12V @ 8A Output
VIN+
+12V
CR3
Q1
T1
C2
R22
QR1
C11
L1
RTN
4
C1
CR4
T2
QR2
R21
Q2
R2
R23
R19
R17
R20
36-75V
CR2
CR1
C12
C13
R18
ISL6740A
C3
R1
R14
U1
3 HO
4 HS
HIP2101
2 HB
R16
LO 8
1 VDD
C14
R13
U3
2801-1
VSS 7
LI 6
HI 5
VR2
U4
TL431
C5
R15
U2
C4
VINR3
1 OUTA
OUTB 16
2 GND
VREF 15
VDD 14
3 SCSET
5 SYNC
SYNC
R4
6 CS
ISL6740A
4 CT
7 VERROR
R5
Q3
8 UV/FF
R12
RTD 13
RTC 12
SYNC
FAULT 10
FAULT
SS 9
R8
RT1
FN9195.3
February 9, 2012
R7
VR1
R6
R9
C6
C7
SYNC I/O
OTS 11
C8
C9
C10
R10
R11
ISL6740A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
OUTA, OUTB, Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . 1500V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93). . . . . . . . 1000V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
16 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . .
98
30
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . -55°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . . . -65°C to 150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
ISL6740AIVx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . . . 9VDC - 16 VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
6. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on
page 2 and Typical Application Schematics on page 3 and page 4. 9V < VDD < 20 V, RTD = 51.1kΩ, RTC = 10kΩ, CT = 470pF, TA = -40°C to 105°C,
Typical values are at TA = 25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C.
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
SUPPLY VOLTAGE
Start-Up Current, IDD
VDD < START Threshold
-
95
140
µA
Operating Current, IDD
RLOAD, COUTA,B = 0
-
5.0
8.0
mA
-
7.0
12.0
mA
UVLO START Threshold
COUTA,B = 1nF
6.50
7.25
8.00
V
UVLO STOP Threshold
6.00
6.75
7.50
V
Hysteresis
0.35
0.50
0.75
V
4.900
5.000
5.050
V
-
3
-
mV
Fault Voltage
4.10
4.55
4.75
V
VREF Good Voltage
4.25
4.75
VREF
-0.05
V
Hysteresis
75
165
250
mV
Operational Current (Source)
-20
-
-
mA
5
-
-
mA
-25
-
-100
mA
REFERENCE VOLTAGE
Overall Accuracy
IVREF = 0, -20mA
Long Term Stability
TA = 125°C, 1000 hours
Operational Current (Sink)
Current Limit
CURRENT SENSE
0.55
0.6
0.65
V
CS to OUT Delay
Current Limit Threshold
VERROR = VREF
-
35
50
ns
CS Sink Current
-
10
-
mA
-1.00
-
1.00
µA
1
-
-
MΩ
Input Bias Current
SCSET Input Impedance
5
FN9195.3
February 9, 2012
ISL6740A
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on
page 2 and Typical Application Schematics on page 3 and page 4. 9V < VDD < 20 V, RTD = 51.1kΩ, RTC = 10kΩ, CT = 470pF, TA = -40°C to 105°C,
Typical values are at TA = 25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
TEST CONDITIONS
SC Setpoint Accuracy
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
-
10
-
%
400
-
-
kΩ
PULSE WIDTH MODULATOR
VERROR Input Impedance
Minimum Duty Cycle
VERROR < CT Valley Voltage
-
-
0
%
Maximum Duty Cycle
VERROR > 4.75V, VUV/FF = 2.5V (Note 9)
RTD = 5.11kΩ, RTC = 25.5kΩ, CT = 220pF
-
83
-
%
-
99
-
%
VERROR to PWM Comparator Input Gain
-
0.4
-
V/V
CT to PWM Comparator Input Gain
-
0.4
-
V/V
SS to PWM Comparator Input Gain
-
0.5
-
V/V
333
351
369
kHz
0.1
0.4
%
OSCILLATOR
Frequency Accuracy
TA = +25°C (Note 10)
Frequency Variation with VDD
TA = +105°C, |(F20V - F9V)/F9V|, UV/FF = 2.00V
-
TA = +25°C, |(F20V - F9V)/F9V|, UV/FF = 2.00V
-
0.1
0.3
TA = -40°C, |(F20V - F9V)/F9V|, UV/FF = 2.00V
-
0.2
0.7
TA = +25°C, |(F4.25V - F2.00V)/F2.00V|
Frequency Variation with VUV/FF
%
VDD = 9V
-
1.2
3
%
VDD = 20V
-
1.2
3
%
VUV/FF = 2.0V, VDD = 9V
-
0.5
1.5
%
1.88
2.0
2.12
µA/µA
45
55
65
µA/µA
0.75
0.80
0.85
V
VUV/FF = 2.00V
2.30
2.40
2.50
V
VUV/FF = 4.25V
4.10
4.20
4.30
V
VUV/FF = 2.00V
-
1.60
-
V
VUV/FF = 4.25V
-
3.40
-
V
Input High Threshold (VIH), Minimum
4.0
-
-
V
Input Low Threshold (VIL), Maximum
-
-
0.8
V
Input Impedance
-
4.5
-
kΩ
Free Running
-
1.67 x
Free Running
Hz
100
-
-
ns
Temperature Stability
Charge Current Gain
Discharge Current Gain
CT Valley Voltage
Static operation
CT Peak Voltage
Static operation
RTD, RTC Voltage
RLOAD = 0Ω
SYNCHRONIZATION
Input Frequency Range
Input Pulse Width
High Level Output Voltage (VOH)
ILOAD = -1mA
-
4.5
-
V
Low Level Output Voltage (VOL)
ILOAD = 10µA
-
-
100
mV
SYNC Output Current
VOH > 2.0V
-10
-
-
mA
250
-
532
ns
-
5
-
ns
SYNC Output Pulse Duration (Minimum)
SYNC Advance
SYNC rising edge to GATE falling edge,
COUTA/B = CSYNC = 100pF
6
FN9195.3
February 9, 2012
ISL6740A
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on
page 2 and Typical Application Schematics on page 3 and page 4. 9V < VDD < 20 V, RTD = 51.1kΩ, RTC = 10kΩ, CT = 470pF, TA = -40°C to 105°C,
Typical values are at TA = 25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
-45
-55
-75
µA
4.35
4.5
4.65
V
0.20
0.25
0.30
V
SOFT-START
Charging Current
SS = 2V
SS Clamp Voltage
Sustained Overcurrent Threshold Voltage
Charged Threshold minus:
Overcurrent/Short Circuit Discharge Current
SS = 2V
13
18
23
µA
Fault SS Discharge Current
SS = 2V
-
10.0
-
mA
0.25
0.27
0.33
V
Reset Threshold Voltage
FAULT
Fault High Level Output Voltage (VOH)
ILOAD = -10mA
2.85
3.5
-
V
Fault Low Level Output Voltage (VOL)
ILOAD = 10mA
-
0.4
0.9
V
Fault Rise Time
CLOAD = 100pF
-
15
-
ns
Fault Fall Time
CLOAD = 100pF
-
15
-
ns
High Level Output Voltage (VOH)
VREF - OUTA or OUTB,
IOUT = -50mA, 1µS duration, CVREF = 1.0µF
-
0.5
1.0
V
Low Level Output Voltage (VOL)
OUTA or OUTB - GND, IOUT = 50mA,
1μs duration, CVREF = 1.0µF
-
0.5
1.0
V
Rise Time
CGATE = 1nF, VDD = 15V
-
50
100
ns
Fall Time
CGATE = 1nF, VDD = 15V
-
40
80
ns
Thermal Shutdown
135
145
155
°C
Thermal Shutdown Clear
120
130
140
°C
-
15
-
°C
2.375
2.50
2.625
V
18
25
30
µA
0.97
1.00
1.03
V
7
10
15
µA
4.8
-
-
V
1
-
-
MΩ
0.78
0.8
0.82
V/V
4.20
-
VREF
V
OUTPUT
THERMAL PROTECTION
Hysteresis, Internal Protection
OTS
Threshold
Hysteresis, Switched Current Amplitude
UV/FF Undervoltage Inhibit/Feed Forward
Input Voltage Low/Inhibit Threshold
Hysteresis, Switched Current Amplitude
Input High Clamp Voltage
Input Impedance
FF Gain
VRTD/VFF, VRTC/VFF
Maximum Control Voltage
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. SYNC pulse width is the greater of this value or the CT discharge time.
9. This is the maximum duty cycle achievable using the specified values of RTC, RTD, and CT. Larger or smaller maximum duty cycles may be obtained
using other values for these components. See Equations 2-4.
10. The oscillator frequency is affected by the tolerance of the timing components used. In particular, parasitic capacitance at the CT pin introduced by
layout, leads, and probes, etc. will lower the frequency.
7
FN9195.3
February 9, 2012
ISL6740A
Typical Performance Curves
65
CT DISCHARGE CURRENT GAIN
NORMALIZED VREF
1.001
1
0.999
0.998
0.997
-40
-25 -10
5
20
35
50
65
80
60
55
50
45
40
95 110
0
50
100 150 200 250 300 350 400 450
TEMPERATURE (°C)
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. OSCILLATOR CT DISCHARGE CURRENT GAIN
1•106
CT (pF) =
1000
680
470
1•103 330
220
100
FREQUENCY (Hz)
DEADTIME - TD (ns)
1•104
100
10
10
20
500
RTD CURRENT (µA)
30
40
50
60
70
80
90
100
RTD (kΩ)
1•105
RTD = 10k
CT (pF) =
100
220
330
470
1•104
10
20
30
680
1000
40
50
60
70
80
90
100
RTC (kΩ)
FIGURE 3. DEADTIME (DT) vs CAPACITANCE
FIGURE 4. CAPACITANCE vs FREQUENCY
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize noise
immunity, bypass VDD to GND with a ceramic capacitor as
close to the VDD and GND pins as possible.
The total supply current, IDD, will be dependent on the load
applied to outputs OUTA and OUTB. Total IDD current is the
sum of the quiescent current and the average output current.
Knowing the operating frequency, Fsw, and the output loading
capacitance charge, Q, per output, the average output current
can be calculated from:
I OUT = 2 • Q • F SW
A
(EQ. 1)
SYNC - A bidirectional synchronization signal used to
coordinate the switching frequency of multiple units.
Synchronization may be achieved by connecting the SYNC
signal of each unit together or by using an external master
clock signal. The oscillator timing capacitor, CT, is always
required regardless of the synchronization method used. The
paralleled unit with the highest oscillator frequency assumes
control. Self-synchronization is not recommended for oscillator
frequencies above 900kHz. For higher switching frequencies,
8
an external clock with a pulse width less than one-half of the
oscillator period must be used.
RTC - This is the oscillator timing capacitor charge current
control pin. A resistor is connected between this pin and GND.
The current flowing through the resistor determines the
magnitude of the charge current. The charge current is
nominally twice this current. The PWM maximum ON time is
determined by the timing capacitor charge duration. The
voltage appearing on this pin is nominally 80% of the voltage
applied to the UV/FF pin.
RTD - This is the oscillator timing capacitor discharge current
control pin. A resistor is connected between this pin and GND.
The current flowing through the resistor determines the
magnitude of the discharge current. The discharge current is
nominally 50x this current. The PWM deadtime is determined
by the timing capacitor discharge duration. The voltage
appearing on this pin is nominally 80% of the voltage applied
to the UV/FF pin.
CT - The oscillator timing capacitor is connected between this
pin and GND.
FN9195.3
February 9, 2012
ISL6740A
VERROR - The inverting input of the PWM comparator. The error
voltage is applied to this pin to control the duty cycle.
Increasing the signal level increases the duty cycle. The node
may be driven with an external error amplifier or opto-coupler.
The ISL6740A features a built-in soft-start capability. Soft-start
is implemented as a clamp on the error voltage input.
OTS - The non-inverting input to the over temperature
shutdown comparator. The signal input at this pin is compared
to an internal threshold of VREF/2. If the voltage at this pin
exceeds the threshold, the Fault signal is asserted and the
outputs are disabled until the condition clears. There is a
nominal 25µA switched current source used for hysteresis. The
amount of hysteresis is adjustable by varying the source
impedance of the signal into this pin.
OTS may be used to monitor parameters other than
temperature, such as voltage. Any signal for which a high
out-of-bounds monitor is desired may utilize the OTS
comparator.
FAULT - The Fault signal is asserted high whenever the outputs,
OUTA and OUTB, are disabled. This occurs during an over
temperature fault, an input UV fault, a VREF UV fault, or during
an overcurrent or short circuit shutdown fault. Fault can be
used to disable synchronous rectifiers whenever the outputs
are disabled.
Fault is a three-state output and is high impedance during the
soft-start cycle. Adding a pull-up resistor to VREF or a pull-down
resistor to ground determines the state of Fault during
soft-start. This feature allows the designer to use the Fault
signal to enable or disable output synchronous rectifiers during
soft-start.
UV/FF - Undervoltage monitor and voltage feed forward input
pin. A resistor divider between the input source voltage and
GND sets the undervoltage lock-out threshold and provides
voltage sensing for the feed forward compensation circuit.
The signal is compared to an internal 1.00V reference to
detect an undervoltage or inhibit condition. For voltages in
excess of the UV threshold, the signal provides voltage
information to the voltage feed forward function.
CS - This is the input to the current sense comparator. The
overcurrent comparator threshold is set at 0.600V nominal.
The CS pin is shorted to GND at the termination of each output
pulse. Depending on the current sensing source impedance, a
series input resistor may be required due to the delay between
the internal clock and the external power switch. This delay
may allow an overlap such that the CS signal may be
discharged while the current signal is still active. If the current
sense source is low impedance it will cause increased power
dissipation.
Exceeding the overcurrent threshold will start a delayed
shutdown sequence. Once an overcurrent condition is
detected, the soft-start charge current source is disabled. The
soft-start capacitor begins discharging through a 25µA current
source, and if it discharges to less than 4.25V (Sustained
Overcurrent Threshold), a shutdown condition occurs and the
OUTA and OUTB outputs are forced low. When the soft-start
9
voltage reaches 0.27V (Reset Threshold) a soft-start cycle
begins.
An overcurrent condition must be absent for 50μs before the
delayed shutdown control resets. If the overcurrent condition
ceases, and an additional 50μs period elapses before the
shutdown threshold is reached, no shutdown occurs. The SS
charging current is re-enabled and the soft-start voltage is
allowed to recover.
GND - Reference and power ground for all functions on this
device. Due to high peak currents and high frequency
operation, a low impedance layout is necessary. Ground planes
and short traces are highly recommended.
OUTA and OUTB - Alternate half cycle output stages. Each
output is capable of 0.5A peak currents for driving logic level
power MOSFETs or MOSFET drivers. Each output provides very
low impedance to overshoot and undershoot.
VREF - The 5.00V reference voltage output. +1/-2% tolerance
over line, load and operating temperature. Bypass to GND with
a 0.047µF to 2.2µF ceramic capacitor. Capacitors outside of
this range may cause oscillation.
SS - Connect the soft-start timing capacitor between this pin
and GND to control the duration of soft-start. The value of the
capacitor determines the rate of increase of the duty cycle
during start up, controls the overcurrent shutdown delay, and
the overcurrent and short circuit hiccup restart period.
SCSET - Sets the duty cycle threshold that corresponds to a
short circuit condition. A resistive divider between RTC and
GND, VREF to GND, RTD and GND, or a voltage between 0 and
2V may be used to adjust the SCSET threshold. If using a
resistor divider from either RTC or RTD, the impedance to GND
affects the oscillator timing and should be considered when
determining the oscillator timing components. Connecting
SCSET to GND disables short circuit shutdown and hiccup.
Functional Description
Features
The ISL6740A PWM is an excellent choice for low cost feed
forward voltage mode bridge topologies for applications
requiring accurate duty cycle and deadtime control. With its
many protection and control features, a highly flexible design
with minimal external components is possible. Among its
many features are voltage feed forward compensation,
adjustable soft-start, overcurrent protection, thermal
protection, bidirectional synchronization, fault indication, and
adjustable frequency.
Oscillator
The ISL6740A has an oscillator with a programmable
frequency range to 2MHz, and can be programmed with two
resistors and a capacitor. The use of three timing elements,
RTC, RTD, and CT allows great flexibility and precision when
setting the oscillator frequency.
The switching period is the sum of the timing capacitor charge
and discharge durations. The charge duration is determined by
FN9195.3
February 9, 2012
ISL6740A
RTC and CT. The discharge duration is determined by RTD and
CT.
t C ≈ 0.5 • R TC • C T
t D ≈ 0.02 • R TD • C T
1
t SW = t C + t D = ----------F SW
(EQ. 2)
S
(EQ. 3)
S
(EQ. 4)
S
where tC and tD are the charge and discharge times,
respectively, tSW is the oscillator free running period, and f is
the oscillator frequency. One output switching cycle requires
two oscillator cycles. The actual times will be slightly longer
than calculated due to internal propagation delays of
approximately 10ns/transition. This delay ads directly to the
switching duration, but also causes overshoot of the timing
capacitor peak and valley voltage thresholds, effectively
increasing the peak-to-peak voltage on the timing capacitor.
Additionally, if very low charge and discharge currents are
used, there will be increased error due to the input impedance
at the CT pin.
The maximum duty cycle, D, and percent deadtime, DT, can be
calculated from:
tC
D = ---------t SW
(EQ. 5)
DT = 1 – D
(EQ. 6)
Figures 3 and 4 graphically portray the deadtime and oscillator
frequency as function of the timing components.
Implementing Synchronization
The oscillator can be synchronized to an external clock applied
to the SYNC pin or by connecting the SYNC pins of multiple ICs
together. If an external master clock signal is used, the free
running frequency of the oscillator should be ~10% slower
than the desired synchronous frequency. The external master
clock signal should have a pulse width greater than 20ns. The
SYNC circuitry will not respond to an external signal during the
first 60% of the oscillator switching cycle. Self-synchronization
is not recommended for oscillator frequencies above 900kHz.
For higher switching frequencies, an external clock with a
pulse width less than one-half of the oscillator period must be
used.
The SYNC input is edge triggered and its duration does not
affect oscillator operation. However, the deadtime is affected
by the SYNC frequency. A higher frequency signal applied to
the SYNC input will shorten the deadtime. The shortened
deadtime is the result of the timing capacitor charge cycle
being prematurely terminated by the external SYNC pulse.
Consequently, the timing capacitor is not fully charged when
the discharge cycle begins. This effect is only a concern when
an external master clock is used, or if units with different
operating frequencies are paralleled.
10
Soft-Start Operation
Soft-start is controlled using an external capacitor in
conjunction with an internal current source. Soft-start reduces
stresses and surge currents during start up.
Upon start up, the soft-start circuitry clamps the error voltage
input (VERROR pin) indirectly to a value equal to the soft-start
voltage. The soft-start clamp does not actually clamp the error
voltage input as is done in many implementations. Rather the
PWM comparator has two inverting inputs such that the lower
voltage is in control.
The output pulse width increases as the soft-start capacitor
voltage increases. This has the effect of increasing the duty
cycle from zero to the regulation pulse width during the softstart period. When the soft-start voltage exceeds the error
voltage at the PWM comparator inputs, soft-start is completed.
Soft-start occurs during start-up, after recovery from a Fault
condition or overcurrent/short circuit shutdown. The soft-start
voltage is clamped to 4.5V.
The Fault signal output is high impedance during the soft-start
cycle unless an active fault (see “Fault Conditions” on page 13)
is present. A pull-up resistor to VREF or a pull-down resistor to
ground should be added to achieve the desired state of Fault
during soft-start.
Gate Drive
The outputs are capable of sourcing and sinking 0.5A peak
current, but are primarily intended to be used in conjunction
with a MOSFET driver due to the 5V drive level. To limit the
peak current through the IC, an external resistor may be placed
between the totem-pole output of the IC (OUTA or OUTB pin)
and the gate of the MOSFET. This small series resistor also
damps any oscillations caused by the resonant tank formed by
the parasitic inductances in the traces of the board and the
device’s input capacitance.
Undervoltage Monitor, Inhibit, and
Feed-Forward
The UV/FF input is used for input source undervoltage lockout
and inhibit functions as well as sensing the input voltage for
feed forward compensation.
If the node voltage falls below 1.00V, a UV shutdown fault
occurs. This may be caused by low source voltage or by
intentional grounding of the pin to disable the outputs. There is
a nominal 10μA switched current source used to create
hysteresis. The current source is active only during a UV/Inhibit
fault; otherwise, it is inactive and does not affect the node
voltage. The magnitude of the hysteresis is a function of the
external resistor divider impedance. If the resistor divider
impedance results in too little hysteresis, a series resistor
between the UV pin and the divider may be used to increase
the hysteresis. A soft-start cycle begins when the UV/Inhibit
fault clears.
The voltage hysteresis created by the switched current source
and the external impedance is generally small due to the large
resistor divider ratio required to scale the input voltage down
to the UV threshold level. A small capacitor placed between the
UV input and ground may be required to filter noise out.
FN9195.3
February 9, 2012
ISL6740A
The voltage amplitude of CT ranges from 1.6V to 4.2V as the
voltage on UV increases. The UV threshold defines the
minimum amplitude of CT and corresponds to maximum duty
cycle operation.
VIN
R1
1.00V
For unregulated bus converters and DC transformers, feed
forward can compensate for input voltage variations without a
closed loop feedback network. A resistive voltage divider from
VREF to VERROR sets the feed forward control voltage. For
example, if the desired duty cycle at the minimum operating
voltage is 90%, then:
+
-
R3
10μA
R2
ON
V ERROR = D max ( V UV ⁄ FF • 0.8 ) + 0.8
= 0.9 ( 1.0 • 0.8 ) + 0.8 = 1.52
FIGURE 5. UV HYSTERESIS
V
–5
R1 + R2
• 〈 R1 + R3 • ⎛ ----------------------⎞ 〉
⎝ R2 ⎠
V
There are two overcurrent protection mechanisms in the
ISL6740A, one for light overcurrent and one for heavy over
load. They are referred to, respectively, as overcurrent
protection and short circuit protection.
(EQ. 8)
OVERCURRENT OPERATION
Setting R3 equal to zero results in the minimum hysteresis,
and yields:
ΔV = 10
–5
• R1
V
(EQ. 9)
As VIN increases from a UV condition, the threshold level is:
V IN ( UP ) = V IN ( DOWN ) + ΔV
V
V
(EQ. 7)
The hysteresis voltage, ΔV, is:
ΔV = 10
(EQ. 11)
Overcurrent Protection
As VIN decreases to a UV condition, the threshold level is:
R1 + R2
V IN ( DOWN ) = ---------------------R2
V
(EQ. 10)
Output voltage variation caused by changes in the supply
voltage may be virtually removed through a technique known
as feed forward compensation. Using feed forward, the duty
cycle is directly modulated based on changes in the input
voltage only. No closed loop feedback system is required. The
feed forward circuit uses the voltage applied to the UV/FF pin
to modulate the oscillator ramp amplitude with minimal effect
on the switching frequency and deadtime of the oscillator. The
voltage feed forward operates over a 3:1 input voltage range.
Overcurrent delayed shutdown is enabled once the soft-start
cycle is complete. If an overcurrent condition is detected, the
soft-start charging current source is disabled and the soft-start
capacitor is allowed to discharge through a 15µA source. At
the same time a 50µs re-triggerable one-shot timer is
activated. It remains active for 50µs after the overcurrent
condition ceases. If the soft-start capacitor discharges by more
then 0.25V to 4.25V, the output is disabled and the Fault signal
asserted. This state continues until the soft-start voltage
reaches 270mV, at which time a new soft-start cycle is
initiated. If the overcurrent condition stops at least 50µs prior
to the soft-start voltage decreasing to 4.25V, the soft-start
charging currents revert to normal operation and the soft-start
voltage is allowed to recover.
4.5 V
SS
0.6 V OC
VUV/FF
CS
OUTA
VERROR
OUTB
CT
FIGURE 7. PULSE-BY-PULSE OC BEHAVIOR DURING SS
OUTA
OUTB
FIGURE 6. FEED FORWARD BEHAVIOR
The voltage applied to the UV/FF pin is multiplied by 0.8 and
output on the RTC and RTD pins. This voltage is also summed
with the CT valley threshold voltage (0.8 V) to create the CT
peak threshold voltage. As the voltage applied to UV/FF varies,
the CT peak voltage and the CT charge and discharge currents
vary, all in direct proportion to each other. The result is an
amplitude modulated sawtooth waveform on CT that is
frequency invariant.
11
Figure 7 shows the overcurrent behavior during SS. Although
an overcurrent condition exists, a shutdown is not allowed prior
to completion of the SS cycle. Only peak current limit operates
during the soft-start cycle. If the overcurrent condition were to
continue beyond the soft-start cycle, a delayed overcurrent
shutdown would occur as shown in Figure 8.
FN9195.3
February 9, 2012
ISL6740A
4.5 V
SS
1
16
4.25 V
2
VREF 15
0.27 V
3
14
4
0.6 V OC
5
CS
OUTA
13
ISL6740A
12
6
11
7
10
8
SS 9
R
OUTB
CSS
FIGURE 8. OC SHUTDOWN BEHAVIOR
Figure 8 portrays the typical delayed overcurrent shutdown
behavior. Once SS has discharged to 4.25V, the outputs are
disabled and remain that way until SS has discharged to
0.27V, and then a new SS cycle begins.
4.5 V
SS
50 μS
OC
4.25 V
0.6 V OC
FIGURE 10. MODIFYING OC SHUTDOWN TIMING
Short Circuit Operation
If the output current increases beyond the overcurrent
threshold, peak current limit will reduce the duty cycle. As the
load current continues to increase, the duty cycle continues to
decrease. A short circuit event is defined as the simultaneous
occurrence of current limit and a reduced duty cycle.
The degree of reduced duty cycle that defines a short circuit
condition is user adjustable using the SCSET input. A resistor
divider between RTD, RTC, or VREF and GND to RCSET sets a
threshold that is compared to the voltage on the timing capacitor,
CT. The resistor divider voltage divided by 2 corresponds to the
duty cycle below which a short circuit can exist.
CS
OUTA
OUTB
FIGURE 9. OC RECOVERY PRIOR TO SHUTDOWN
If the overcurrent condition is removed prior to a shutdown, a
recovery can occur as indicated in Figure 9. When the load
decreases below the overcurrent threshold and an additional
50μs elapses without the SS dropping below 4.25V, the
overcurrent circuitry resets and the soft-start voltage recovers.
The duration of the OC shutdown period can be increased by
adding a resistor between VREF and SS. The value of the
resistor must be large enough so that the minimum specified
SS discharge current is not exceeded. Using a 422kΩ resistor,
for example, will result in a small current being injected into
SS, effectively reducing the discharge current. This will nearly
double the OFF time. The external pull-up resistor will also
decrease the SS duration, so its effect should be considered
when selecting the value of the SS capacitor.
Latching OC shutdown is also possible by using a lower valued
resistor between VREF and SS. If the SS node is not allowed to
discharge below the SS reset threshold, the IC will not recover
from an overcurrent fault. The value of the resistor must be low
enough so that the maximum specified discharge current is
not sufficient to pull SS below 0.33V. A 200kΩ resistor, for
example, prevents SS from discharging below ~0.4V. Again,
the external pull-up resistor will decrease the SS duration, so
its effect should be considered when selecting the value of the
SS capacitor.
12
V SCSET
D SC = ------------------- ⋅ D max
2
(EQ. 12)
where DSC is the maximum short circuit duty cycle, VSCSET is
the voltage applied to SCSET, and Dmax is the maximum duty
cycle. If the timing capacitor voltage fails to exceed the
threshold before an overcurrent pulse is detected, a short
circuit condition exists. A shutdown will occur if 8 short circuit
events occur within 32 oscillator cycles. Once shutdown
occurs, SS will discharge through a 15µA current source. A
new soft-start cycle will begin when SS reaches 0.27V.
Latching shutdown may be implemented in the same manner
as described in the overcurrent section. Short circuit shutdown
is enabled once the soft-start cycle is complete. Connecting
SCSET to GND inhibits short circuit shutdown.
If either RTC ar RTD are used as the voltage source for the
divider, the effect of the SCSET divider must be included in the
timing calculations since the current sourced from RTC and
RTD determine the charge and discharge currents for the
timing capacitor. Typically the resistor between either RTC or
RTD and GND is formed by two series resistors with the center
node connected to SCSET.
Alternatively, SCSET may be set using a voltage between 0V
and 2V. This voltage divided by 2 determines the percentage of
the maximum duty cycle that corresponds to a short circuit
when current limit is active. For example, if the maximum duty
cycle is 95% and 1V is applied to SCSET, then the short circuit
duty cycle is 50% of 95% or 47.5%.
FN9195.3
February 9, 2012
ISL6740A
Fault Conditions
A fault condition occurs if any of the following conditions
occur:
• VREF falls below 4.65V
• UV falls below 1.00V
• the internal thermal protection triggers
• OTS faults
When any of the above faults are detected, OUTA and OUTB
outputs are disabled, Fault is asserted, and the soft-start
capacitor is quickly discharged. When the fault condition
clears and the soft-start voltage is below the reset threshold, a
soft-start cycle begins. Fault is high impedance during the
soft-start cycle unless an active fault is present.
A shutdown resulting from an overcurrent or short circuit
condition also causes assertion of Fault, but the soft-start
capacitor is not quickly discharged. The initiation of a new
soft-start cycle is delayed while the soft-start capacitor is
discharged at a 15µA rate. This reduces the repetition rate of
the hiccup behavior and keeps the average output current to a
minimum.
Thermal Protection
Two methods of over temperature protection are provided. The
first method is an on board temperature sensor that protects
the device should the junction temperature exceed 145°C.
There is approximately 15°C of hysteresis.
The second method uses an internal comparator with a 2.5V
reference (VREF/2). The non-inverting input to the comparator
is accessible through the OTS pin. A thermistor or thermal
sensor located at or near the area of interest may be
connected to this input. There is a nominal 25μA switched
current source used to create hysteresis. The current source is
active only during an OT fault; otherwise, it is inactive and does
not affect the node voltage. The magnitude of the hysteresis is
a function of the external resistor divider impedance. Either a
positive temperature coefficient (PTC) or a negative
temperature coefficient (NTC) thermistor may be used. If a NTC
thermistor is desired, position R1 may be substituted. If a PTC
is desired, then position R2 may be substituted. The threshold
with increasing temperature is set by making the fixed
resistance equal in value to the thermistor resistance at the
desired trip temperature.
V TH↑ = 2.5V and R1 = R2 (HOT)
To determine the value of the hysteresis resistor, R3, select the
value of thermistor resistance that corresponds to the desired
reset temperature.
5
10 • ( R1 – R2 ) – R1 • R2
R3 = ---------------------------------------------------------------------R1 + R2
Ω
(EQ. 13)
If the hysteresis resistor, R3, is not desired, the value of the
thermistor resistance at the reset temperature can be
determined from:
2.5 • R2
R1 = ----------------------------------------–5
2.5 – 10 • R2
Ω
( NTC )
(EQ. 14)
2.5 • R1
R2 = ----------------------------------------–5
2.5 + 10 • R1
Ω
( PTC )
(EQ. 15)
VREF
VREF
ON
R1
OTHER USES FOR OTS
25μA
VREF/2
R3
+
-
R2
The OTS comparator may also be used to monitor signals other
than as suggested above. It may also be used to monitor any
voltage signal for which an excess requires a response as
described above. Input and output voltage monitoring are
examples of this.
Ground Plane Requirements
FIGURE 11. OTS HYSTERESIS
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. VDD and VREF
should be bypassed directly to GND with good high frequency
capacitance.
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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13
FN9195.3
February 9, 2012
ISL6740A
Package Outline Drawing
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.65
0.09-0.20
END VIEW
TOP VIEW
1.00 REF
- 0.05
H
C
1.20 MAX
SEATING
PLANE
0.90 +0.15/-0.10
GAUGE
PLANE
0.25 +0.05/-0.06 5
0.10 M C B A
0.10 C
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
14
FN9195.3
February 9, 2012