SiHJ6N65E Datasheet

SiHJ6N65E
www.vishay.com
Vishay Siliconix
E Series Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) typ. () at 25 °C
• Low figure-of-merit (FOM) Ron x Qg
700
VGS = 10 V
• Low input capacitance (Ciss)
0.755
Qg max. (nC)
32
• Reduced switching and conduction losses
Qgs (nC)
5
• Ultra low gate charge (Qg)
Qgd (nC)
7
• Avalanche energy rated (UIS)
Configuration
Single
PowerPAK® SO-8L
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
D
• Switch mode power supplies (SMPS)
• Power factor correction power supplies (PFC)
• Lighting
G
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Consumer
S
- Adaptors
N-Channel MOSFET
ORDERING INFORMATION
Package
PowerPAK SO-8L
Lead (Pb)-free and Halogen-free
SiHJ6N65E-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
650
Gate-Source Voltage
VGS
± 30
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
UNIT
V
5.6
ID
A
3.6
IDM
12
Linear Derating Factor
0.76
W/°C
Single Pulse Avalanche Energy b
EAS
36
mJ
Maximum Power Dissipation
PD
74
W
TJ, Tstg
-55 to +150
°C
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
TJ = 125 °C
Reverse Diode dV/dt c
70
dV/dt
V/ns
9.4
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 120 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 1.6 A.
c. ISD  ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
52
65
Maximum Junction-to-Case (Drain)
RthJC
1.2
1.7
S16-0840-Rev. B, 09-May-16
UNIT
°C/W
Document Number: 91589
1
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SiHJ6N65E
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SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = 250 μA
650
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.8
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
VGS = ± 20 V
-
-
± 100
nA
μA
IGSS
IDSS
RDS(on)
VGS = ± 30 V
-
-
±1
VDS = 650 V, VGS = 0 V
-
-
1
VDS = 520 V, VGS = 0 V, TJ = 125 °C
-
-
10
-
0.755
0.868

-
S
VGS = 10 V
ID = 3 A
gfs
VDS = 30 V, ID = 3 A
-
1.8
Input Capacitance
Ciss
596
-
Coss
-
35
-
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output Capacitance
-
4
-
Effective Output Capacitance, Energy
Related a
Co(er)
-
26
-
Effective Output Capacitance, Time
Related b
Co(tr)
-
90
-
-
16
32
-
5
-
-
7
-
μA
Dynamic
pF
VDS = 0 V to 520 V, VGS = 0 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
-
14
28
tr
VDD = 520 V, ID = 3 A,
VGS = 10 V, Rg = 9.1 
-
14
28
-
25
50
-
17
34
f = 1 MHz
0.4
0.8
1.6
-
-
5.6
-
-
12
Rise Time
Turn-Off Delay Time
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
ID = 3 A, VDS = 520 V
nC
ns

Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the 
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 3 A, VGS = 0 V
TJ = 25 °C, IF = IS = 3 A,
dI/dt = 100 A/μs, VR = 25 V
S
-
0.9
1.2
V
-
278
556
ns
-
2.1
4.2
μC
-
12
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
S16-0840-Rev. B, 09-May-16
Document Number: 91589
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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SiHJ6N65E
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3.0
15
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
12
9
ID = 3 A
TJ = 25 °C
RDS(on), Drain-to-Source On-Resistance
(Normalized)
6
3
0
2.0
1.5
1.0
VGS = 10 V
0.5
0
0
5
10
15
VDS, Drain-to-Source Voltage (V)
-60 -40 -20
20
8
10 000
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
TJ = 150 °C
1000
C, Capacitance (pF)
6
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
ID, Drain-to-Source Current (A)
2.5
4
Ciss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
100
Coss
10
2
Crss
1
0
0
5
10
15
VDS, Drain-to-Source Voltage (V)
0
20
100
200
300
400
500
VDS, Drain-to-Source Voltage (V)
600
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
15
10 000
5
4.5
4
3.5
1000
9
3
Coss (pF)
ID, Drain-to-Source Current (A)
TJ = 25 °C
12
TJ = 150 °C
6
Coss
Eoss
2.5
2
100
Eoss (μJ)
ID, Drain-to-Source Current (A)
TOP
1.5
3
1
0.5
VDS = 31 V
0
0
5
10
15
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S16-0840-Rev. B, 09-May-16
0
10
20
0
100
200
300
VDS
400
500
600
Fig. 6 - Coss and Eoss vs. VDS
Document Number: 91589
3
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SiHJ6N65E
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Vishay Siliconix
6
VDS = 520 V
VDS = 325 V
VDS = 130 V
20
16
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
12
8
4
2
4
0
0
6
12
18
24
0
30
25
50
Qg, Total Gate Charge (nC)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
75
100
125
TC, Case Temperature (°C)
150
Fig. 10 - Maximum Drain Current vs. Case Temperature
VDS, Drain-to-Source Breakdown Voltage (V)
875
ISD, Reverse Drain Current (A)
10
TJ = 150 °C
TJ = 25 °C
1
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
VSD, Source-Drain Voltage (V)
1.2
Fig. 8 - Typical Source-Drain Diode Forward Voltage
850
825
800
775
750
725
700
675
ID = 250 μA
650
-60 -40 -20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 11 - Temperature vs. Drain-to-Source Voltage
100
Operation in this area
limited by RDS(on)
IDM limited
ID, Drain Current (A)
10
100 μs
1
Limited by RDS(on)*
1 ms
0.1
10 ms
TC = 25 °C
TJ = 150 °C
Single pulse
0.01
1
BVDSS limited
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S16-0840-Rev. B, 09-May-16
Document Number: 91589
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHJ6N65E
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Vishay Siliconix
1
Normalized Effective Transient
Thermal Impedance
Duty cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single pulse
0.01
0.000001
0.00001
0.0001
0.001
Pulse Time (s)
0.01
0.1
1
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
1
Duty cycle = 0.5
Normalized Effective Transient
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
0.01
0.001
Single pulse
0.0001
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Time (s)
Fig. 13 - Normalized Thermal Transient Impedance, Junction-to-Ambient
VDS
VGS
RG
RD
VDS
90 %
D.U.T.
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 14 - Switching Time Test Circuit
S16-0840-Rev. B, 09-May-16
10 %
VGS
td(on)
tr
td(off) tf
Fig. 15 - Switching Time Waveforms
Document Number: 91589
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SiHJ6N65E
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Vishay Siliconix
L
Vary tp to obtain
required IAS
VDS
QG
10 V
D.U.T
RG
+
-
IAS
QGS
QGD
V DD
VG
10 V
0.01 Ω
tp
Charge
Fig. 16 - Unclamped Inductive Test Circuit
Fig. 18 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
tp
50 kΩ
VDD
12 V
0.2 µF
0.3 µF
+
VDS
D.U.T.
-
VDS
VGS
IAS
Fig. 17 - Unclamped Inductive Waveforms
3 mA
IG
ID
Current sampling resistors
Fig. 19 - Gate Charge Test Circuit
S16-0840-Rev. B, 09-May-16
Document Number: 91589
6
For technical questions, contact: [email protected]
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SiHJ6N65E
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 20 - For N-Channel










Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91589.
S16-0840-Rev. B, 09-May-16
Document Number: 91589
7
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
PowerPAK® SO-8L Case Outline
for Non-Al Parts
W
E1
E
E2
W2
W3
W1
b2
D2
b
b1
L
L1
L1
A1
e
θ
D1
D
b3
b4
0.25 gauge line
Topside view
Backside view (single)
E2
W2
C
A
W3
W1
F
K
D3
D3
D2
b3
b4
Backside view (dual)
Revision: 16-May-16
Document Number: 69003
1
For technical questions, contact: [email protected]
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Package Information
www.vishay.com
DIM.
Vishay Siliconix
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
1.00
1.07
1.14
0.039
0.042
0.045
A1
0.00
-
0.127
0.00
-
0.005
b
0.33
0.41
0.48
0.013
0.016
0.019
b1
0.44
0.51
0.58
0.017
0.020
0.023
b2
4.80
4.90
5.00
0.189
0.193
0.197
b3
0.094
b4
0.004
0.47
0.019
c
0.20
0.25
0.30
0.008
0.010
0.012
D
5.00
5.13
5.25
0.197
0.202
0.207
D1
4.80
4.90
5.00
0.189
0.193
0.197
D2
3.86
3.96
4.06
0.152
0.156
0.160
D3
1.63
1.73
1.83
0.064
0.068
0.072
e
1.27 BSC
0.050 BSC
E
6.05
6.15
6.25
0.238
0.242
0.246
E1
4.27
4.37
4.47
0.168
0.172
0.176
E2
3.18
3.28
3.38
0.125
0.129
0.133
F
-
-
0.15
-
-
0.006
L
0.62
0.72
0.82
0.024
0.028
0.032
L1
0.92
1.07
1.22
0.036
0.042
0.048
K
0.51
0.020
W
0.23
0.009
W1
0.41
0.016
W2
2.82
0.111
W3
2.96
0.117

0°
-
10°
0°
-
10°
ECN: T16-0221-Rev. D, 16-May-16
DWG: 5976
Note
• Millimeters will gover
Revision: 16-May-16
Document Number: 69003
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PAD Pattern
www.vishay.com
Vishay Siliconix
RECOMMENDED MINIMUM PAD FOR PowerPAK® SO-8L SINGLE
5.000
(0.197)
0.510
(0.020)
2.310
(0.091)
4.061
(0.160)
0.595
(0.023)
6.250
(0.246)
8.250
(0.325)
3.630
(0.143)
0.610
(0.024)
0.410
(0.016)
2.715
(0.107)
0.860
(0.034)
1.291
(0.051)
0.710
(0.028)
0.820
(0.032)
1.905
(0.075)
1.270
(0.050)
7.250
(0.285)
Recommended Minimum Pads
Dimensions in mm (inches)
Revision: 07-Feb-12
1
Document Number: 63818
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 02-Oct-12
1
Document Number: 91000