DATASHEET

X4C105
®
4k, NOVRAM/EEPROM
Data Sheet
July 3, 2008
CPU Supervisor with NOVRAM and Output
Ports
The low voltage X4C105 combines several functions into
one device. The first is a 2-wire, 4k-bit serial EEPROM
memory with write protection. A Write Protect (WP) pin
provides hardware protection for the upper half of this
memory against inadvertent writes.
A one nibble NOVRAM is provided and occupies a single
location. This allows access of 4-bits in a single 150ns cycle.
This is useful for tracking system operation or process
status. The NOVRAM memory is completely isolated from
the serial memory section.
A low voltage detect circuit activates a RESET pin when VCC
drops below 3V. This signal also blocks new read or write
operations and initiates a NOVRAM AUTOSTORE. The
AUTOSTORE operation is powered by an external capacitor
to ensure that the value in the NOVRAM is always
maintained in the event of a power failure.
The four NOVRAM bits also appear on four separate output
pins to allow continuous control of external circuitry, such as
ASICs.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Inherent data retention is
greater than 100 years.
FN8124.2
Features
• 4k-bit serial EEPROM
- 400kHz serial interface speed
- 16-byte page write mode
• One nibble NOVRAM
- 120ns NOVRAM access speed
- AUTOSTORE
- Direct/bus access of NOVRAM bits
• Four output ports
• Operates at 3.3V ± 10%
• Low voltage reset when VCC < 3V
- 3% accurate thresholds available
- Output signal shows low voltage condition
- Activates NOVRAM AUTOSTORE
- Internal block on EEPROM operation
• Max EEPROM/NOVRAM nonvolatile write cycle: 5ms
• High reliability
- 1,000,000 endurance cycles
- Guaranteed data retention: 100 years
- 20 Ld TSSOP package
Ordering Information
PART
NUMBER
PART
MARKING
X4C105V20
X4C105V
X4C105V20I
X4C105V I
1
VCC LIMITS
(V)
VTRIP
(V)
TEMP RANGE
(°C)
3.3V ±10%
2.8 to 2.95
0 to +70
20 Ld TSSOP
-40 to +85
20 Ld TSSOP
PACKAGE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X4C105
Block Diagram
WP
WRITE CONTROL LOGIC
SCL
SDA
S1
S2
X DECODER
HV GENERATION
TIMING AND CONTROL
COMMAND
DECODE
AND
CONTROL
LOGIC
EEPROM
MEMORY
STATIC RAM
MEMORY
4k-BITS
EEPROM
ARRAY
O0
O1
O2
O3
I/O
BUFFERS
D0
D1
D2
D3
CONTROL
LOGIC AND
TIMING
Y DECODER
DATA REGISTER
LOW VOLTAGE DETECT
POWER-ON RESET
Pinout
OUTPUT
BUFFERS
AND
LATCHES
VOLTAGE
MONITOR
SUPPLY
CE
OE
WE
CAP
VCC
VSS
RESET
Device Description
X4C105
(20 LD TSSOP)
TOP VIEW
CAP
1
S1
2
19 WP
S2
3
18 SCL
CE
4
17 SDA
WE
5
16 D0
OE
6
15 D1
RESET
7
14 D2
O3
8
13 D3
O2
9
12 O0
VSS 10
11 O1
20 VCC
Pin Descriptions
Serial Memory Section
The device contains a 4k-bit EEPROM memory array with an
internal address counter that allows it to be read
sequentially, through its entire address space after receiving
only 1 full address. The serial interface includes a current
address read that requires no input address, but allows
reading of the entire array starting from the address plus one
of the last read or write. The address counter is also used for
the write operation where the user may enter up to a page of
data (16 bytes) after supplying only 1 full address.
A WP pin provides hardware write protection. The WP pin
active (HIGH) prevents writes to the top half of the memory.
This section is a 4k-bit version of an industry standard
24C04 device.
NOVRAM Section
PIN
DESCRIPTION
VSS
Ground
SDA
Serial Data
VCC
Power
SCL
Serial Clock
WP
Write Protect
S1, S2
CAP
D0, D1, D2, D3
RESET
Device Select Inputs
External AUTOSTORE Capacitor
NOVRAM I/Os
Low Voltage Detect Output
CE
NOVRAM Chip Enable
OE
NOVRAM Read Signal
WE
NOVRAM Write signal
O0, O1, O2, O3
NOVRAM Outputs
2
The X4C105 also contains a single nibble of NOVRAM, with
parallel access. This memory is completely isolated from the
serial memory section. The NOVRAM is intended to connect
to the system memory bus and uses standard CE, OE, and
WE pins to control access.
A NOVRAM (or nonvolatile RAM) consists of an SRAM part
and an EEPROM part. The SRAM is saved to EEPROM only
when power fails and the EEPROM is recalled to SRAM only
on power-up.
Output Ports
The X4C105 has four output only ports. These are active
whenever power is applied to the device. The state of the
output pin reflects the value in the respective SRAM bit. As
such, these port pins provide a nonvolatile state. The conditions
on the pins are restored when power is re-applied to the device.
This can be valuable as a DIP switch replacement for
controlling the conditions of an ASIC or other system logic.
FN8124.2
July 3, 2008
X4C105
Low Voltage Detection
Serial Interface
When the internal low voltage detect circuitry senses that
VCC is low, several things happen:
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the devices in this family operate as slaves in all
applications.
• The RESET pin goes active.
• The contents of the SRAM are automatically saved to the
“shadow” EEPROM.
• Internal circuitry switches to provide power for the
AUTOSTORE operation from the CAP pin so the store
operation can complete even in the event of a catastrophic
power failure. To insure this, it is recommended that a
47µF capacitor be used on the CAP pin. The capacitor is
continuously charged during normal operation to provide
the necessary charge to complete the store operation.
Other internal circuits are turned off to minimize current
consumption during the store operations.
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 2.
• Communication to the device is interrupted and any
command is aborted. If a serial nonvolatile store is in
progress when power fails, the operation is completed and
is followed by a NOVRAM AUTOSTORE cycle.
Serial Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 3.
Capacitor Backup Circuit
The diagram in Figure 1 shows a representation of the
capacitor backup circuit.
TO INTERNAL
VOLTAGE SUPPLY
VCC
VTRIP
HIGH WHEN
VCC > VTRIP
LOW WHEN
VCC < VTRIP - 0.2V
START
NOVRAM
AUTOSTORE
CAP
FIGURE 1. CAPACITOR BACK-UP CIRCUIT
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 2. VALID DATA CHANGES ON THE SDA BUS
3
FN8124.2
July 3, 2008
X4C105
Serial Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus. See Figure 2.
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data. Refer to Figure 4.
The device will respond with an acknowledge after
recognition of a start condition and if the correct device
identifier and select bits are contained in the slave address
byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
eight bit word. The device will acknowledge all incoming data
and address bytes, except for the slave address byte when
the device identifier and/or select bits are incorrect or when
the device is busy, such as during a nonvolatile write.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
standby mode and place the device into a known state.
Serial Write Operations
Byte Write
For a write operation, the device requires the slave address
byte and a word address byte. This gives the master access to
any one of the words in the array. After receipt of the word
address byte, the device responds with an acknowledge, and
awaits the next eight bits of data. After receiving the 8 bits of the
data byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating a stop
condition, at which time the device begins the internal write
cycle to the nonvolatile memory. During this internal write cycle,
the device inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 5.
An attempted write to a protected block of memory will
suppress the acknowledge bit and the operation will
terminate.
SCL
SDA
START
STOP
FIGURE 3. VALID START AND STOP CONDITIONS
SCL
FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVE
4
FN8124.2
July 3, 2008
X4C105
Page Write
The master terminates the data byte loading by issuing a
stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. Refer to Figure 7 for the address, acknowledge, and
data transfer sequence.
The device is capable of a page write operation. It is initiated
in the same manner as the byte write operation; but instead
of terminating the write cycle after the first data byte is
transferred, the master can transmit an unlimited number of
8-bit bytes. After the receipt of each byte, the device will
respond with an acknowledge, and the address is internally
incremented by one. The page address remains constant.
When the counter reaches the end of the page, it “rolls over”
and goes back to ‘0’ on the same page. This means that the
master can write 16 bytes to the page starting at any location
on that page. If the master begins writing at location 10, and
loads 12 bytes, then the first 5 bytes are written to locations
10 through 15, and the last 7 bytes are written to locations 0
through 6. Afterwards, the address counter would point to
location 7 of the page that was just written. See Figure 6. If the
master supplies more than 16 bytes of data, then new data
over-writes the previous data, one byte at a time.
S
T
A
R
T
SIGNALS
FROM THE
MASTER
Stops and Write Modes
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte plus the
subsequent ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte plus its associated ACK
is sent, then the device will reset itself without performing the
write. The contents of the array will not be affected.
BYTE
ADDRESS
SLAVE
ADDRESS
SDA BUS
S
T
O
P
DATA
0
A
C
K
SIGNALS
FROM THE
SLAVE
A
C
K
A
C
K
FIGURE 5. BYTE WRITE SEQUENCE
.
7 BYTES
5 BYTES
ADDRESS POINTER
ADDRESS = 6
ADDRESS
ADDRESS
10
n-1
ENDS HERE
ADDR = 7
FIGURE 6. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10
(1 < n < 16)
S
T
A
R
T
SIGNALS
FROM THE
MASTER
SDA BUS
BYTE
ADDRESS
SLAVE
ADDRESS
S
T
O
P
DATA
(n)
DATA
(1)
0
A
C
K
SIGNALS
FROM THE
SLAVE
A
C
K
A
C
K
A
C
K
FIGURE 7. PAGE WRITE OPERATION
5
FN8124.2
July 3, 2008
X4C105
Serial Read Operations
BYTE LOAD
COMPLETED BY
ISSUING STOP
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the slave
address byte is set to one. There are three basic read
operations: current address read, random read, and
sequential read.
ISSUE START
Current Address Read
ISSUE SLAVE
ADDRESS BYTE
ISSUE STOP
Internally the device contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power-up, the address of the address counter is undefined,
requiring a read or write operation for initialization.
NO
ACK
RETURNED?
YES
Upon receipt of the slave address byte with the R/W bit set to
one, the device issues an acknowledge and then transmits
the eight bits of the data byte. The master terminates the read
operation when it does not respond with an acknowledge
during the ninth clock and then issues a stop condition. Refer
to Figure 9 for the address, acknowledge, and data transfer
sequence.
NO
HIGH VOLTAGE
CYCLE COMPLETE.
CONTINUE
COMMAND
ISSUE STOP
YES
CONTINUE NORMAL
READ OR WRITE
COMMAND
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
PROCEED
Random Read
FIGURE 8. ACKNOWLEDGE POLLING SEQUENCE
Acknowledge Polling
The disabling of the inputs during high voltage cycles can be
used to take advantage of the typical 5ms write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the device initiates the internal
non volatile write cycle. Acknowledge polling can be initiated
immediately. To do this, the master issues a start condition
followed by the slave address byte for a write or read
operation. If the device is still busy with the high voltage
cycle then no ACK will be returned. If the device has
completed the write operation, an ACK will be returned and
the host can then proceed with the read or write operation.
Refer to the flow chart in Figure 8.
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
S
T
A
R
T
A random read operation allows the master to access any
memory location in the array. Prior to issuing the slave
address byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the start condition and the slave address byte, receives an
acknowledge, then issues the word address byte. After
acknowledging receipts of the word address byte, the master
immediately issues another start condition and the slave
address byte with the R/W bit set to one. This is followed by
an acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a stop
condition. Refer to Figure 10 for the address, acknowledge
and data transfer sequence.
S
T
O
P
SLAVE
ADDRESS
1
A
C
K
DATA
FIGURE 9. CURRENT ADDRESS READ SEQUENCE
6
FN8124.2
July 3, 2008
X4C105
• a device type identifier that is always ‘1010’.
The device offers a similar operation, called “Set Current
Address,” where the device ends the transmission and issues
a stop instead of the second start, shown in Figure 10. The
device goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This operation
loads the new address into the address counter. The next
current address read operation will then read from the newly
loaded address. This operation could be useful if the master
knows the next address it needs to read, but is not ready for
the data.
• two bits that provide the device select bits.
• one bit that becomes the MSB of the address.
• one bit of the slave command byte is a R/W bit. The R/W
bit of the slave address byte defines the operation to be
performed. When the R/W bit is a one, then a read
operation is selected. A zero selects a write operation.
Refer to Figure 11.
After loading the entire slave address byte from the SDA
bus, the device compares the device select bits with the
status of the device select pins. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Sequential Read
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is
transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it requires
additional data. The device continues to output data for each
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
Slave Byte
1
0
1
0
S2
S1
A8
R/W
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter is
undefined on a power-up condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address counter
for read operations increments through all page and column
addresses, allowing the entire memory contents to be serially
read during one operation. At the end of the address space
the counter “rolls over” to address 0000H and the device
continues to output data for each acknowledge received.
Refer to Figure 11 for the acknowledge and data transfer
sequence.
Write Protect Operations
The WP pin provides write protection. The WP pin protects
the upper half of the array.
TABLE 1. WRITE PROTECTED AREAS
WP PIN
Serial Device Addressing
SERIAL MEMORY WRITE PROTECTION
LOW
Writes possible to all locations
HIGH
No writes to 100H-1FFH, writes possible to 000H to 0FFH
Slave Address Byte
Following a start condition, the master must output a slave
address byte. This byte consists of several parts:
S
T
A
R
T
SIGNALS
FROM THE
MASTER
SDA BUS
S
T
A
R
T
BYTE
ADDRESS
SLAVE
ADDRESS
1
0
A
C
K
SIGNALS
FROM THE
SLAVE
S
T
O
P
SLAVE
ADDRESS
A
C
K
A
C
K
DATA
FIGURE 10. RANDOM ADDRESS READ SEQUENCE
SIGNALS
FROM THE
MASTER
SLAVE
ADDRESS
SDA BUS
1
A
C
K
A
C
K
SIGNALS
FROM THE
SLAVE
DATA
(1)
A
C
K
DATA
(2)
S
T
O
P
A
C
K
DATA
(n - 1)
DATA
(n)
(“n” IS ANY INTEGER GREATER THAN 1)
FIGURE 11. SEQUENTIAL READ SEQUENCE
7
FN8124.2
July 3, 2008
X4C105
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to GND . . . . . . . . . . -1.0V to 7.0V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
20 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
SYMBOL
VCC = 3.0V to 3.6V at -40°C to +85°C, unless otherwise specified. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
ICC1 (Note 2) Active Supply Current Serial
Read or Serial Write (Does Not
Include the Nonvolatile Store
Operation)
VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400kHz, SDA = Read/Write
Operation, CE, OE, WE, D0 - D3 = VIH; O0 - O3, RESET = Open
CAP is tied to VCC; VCC > VTRIP
2.0
mA
ICC2 (Note 2) Average Active Supply Current
During Serial Nonvolatile Store
Operation
VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 = VIL,
CE, OE, WE, D0 - D3 = VIH; O0 - O3, RESET = Open CAP is tied to
VCC. Test during the N.V. write cycle.
3.0
mA
ICC3 (Note 2) Active Supply Current Volatile
NOVRAM Read
VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 = VIL,
WE = VIH; CE, OE = VIL, D0 - D3, O0 - O3, RESET = Open CAP is
tied to VCC; VCC > VTRIP
3.0
mA
ICC4 (Note 2) Active Supply Current Volatile
NOVRAM Write
VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 =VIL,
OE = VIH; CE, WE = VIL, D0-D3 = VIL or VIH, O0 - O3, RESET = Open
CAP is tied to VCC; VCC > VTRIP
3.0
mA
ICC5 (Note 2) Average Active Supply Current
Over NOVRAM Store or Active
Current During Recall
VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA, VIH; WP, S1, S2 = VIL,
WE, CE, OE = VIH; D0 - D3, O0 - O3, RESET = Open CAP is tied
to VCC, VCC < VTRIP for Store; VCC > VTRIP for Recall
3.0
mA
ISB1 (Note 2) Standby Current
VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA, CE, WE, OE, D0 - D3,
= VIH, WP = VIL, O0 - O3,RESET = Open; CAP is tied to VCC
50
µA
ILI
Input Leakage Current
VIN = GND to VCC
10
µA
ILO
Output Leakage Current
VSDA = GND to VCC; Device is in Standby (Note 3)
10
µA
VIL (Note 4) Input LOW voltage
-0.5
VCC x 0.3
V
VIH (Note 4) Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VHYS
Schmitt Trigger Input Hysteresis
VOL
Output LOW Voltage
IOL = 2.0mA, VCC = 3.3V
VOH
Output HIGH Voltage
IOH = -1mA, VCC = 3.3V
0.05 x VCC
V
0.4
V
VCC - 0.4
V
NOTES:
2. The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte
are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
3. The device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage
cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte.
4. VIL min and VIH max are for reference only and are not tested.
Capacitance
TA = +25°C, f = 1.0 MHz, VCC = 3.0V to 3.6V.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
UNIT
CI/O
Input/Output Capacitance (SDA, D0 - D3, O0 - O3)
VI/O = 0V
8
pF
CIN
Input Capacitance (SCL, WP, CE, WE, OE, S1, S2)
VIN = 0V
6
pF
8
FN8124.2
July 3, 2008
X4C105
Serial Nonvolatile Write Cycle Timing
SYMBOL
tWC (Note 5)
PARAMETER
MIN
Write Cycle Time
TYP
(Note 5)
MAX
UNIT
3
5
ms
NOTE:
5. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used.
Serial Memory AC Characteristics
Serial AC Test Conditions
Equivalent AC Output Load Circuit for VCC = 3.0V
to 3.6V
3.3V
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
1533Ω
FOR VOL = 0.4V
AND IOL = 2mA
Input and output timing levels
VCC x 0.5
Output load
Standard output load
SDA
100pF
Electrical Specifications
TA = -40°C to +85°C, VCC = +3.0V to +3.6V, unless otherwise specified. Parameters with MIN and/or MAX limits
are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and
are not production tested.
400kHz OPTION
SYMBOL
MIN
MAX
UNIT
SCL Clock Frequency
0
400
kHz
tIN
Pulse Width of Spikes to be Suppressed by the Input Filter
0
50
ns
tAA
SCL Low to SDA Data Out Valid
0.1
0.9
µs
tBUF
Time the Bus Must be Free Before a New Transmission Can Start
1.3
µs
tLOW
Clock Low Time
1.3
µs
tHIGH
Clock High Time
0.6
µs
tSU:STA
Start Condition Set-up Time
0.6
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tSU:DAT
Data In Set-up Time
100
ns
tHD:DAT
Data In Hold Time
0
µs
tSU:STO
Stop Condition Set-up Time
0.6
µs
tDH
Data Output Hold Time
50
ns
tR
SDA and SCL Rise Time
20 + 0.1Cb (Note 6)
300
ns
tF
SDA And SCL Fall Time
20 + 0.1Cb (Note 6)
300
ns
fSCL
PARAMETER
tSU: S1, S2,WP
S1, S2 and WP Set-up Time
0.4
ms
tHD: S1, S2,WP
S1, S2 and WP Hold Time
0.4
ms
Cb
Capacitive Load for Each Bus Line
400
pF
NOTES:
6. Cb = total capacitance of one bus line in pF.
9
FN8124.2
July 3, 2008
X4C105
Serial Timing Diagrams
Bus Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA IN
tAA
tDH
tBUF
SDA OUT
S1, S2 and WP Pin Timing
START
SCL
CLK 1
CLK 9
SLAVE ADDRESS BYTE
SDA IN
tHD: S1, S2, WP
tSU: S1, S2, WP
S1, S2 AND WP
Write Cycle Timing
SCL
SDA
8TH BIT OF LAST BYTE
ACK
tWC
STOP
CONDITION
NOVRAM AC Characteristics
START
CONDITION
NOVRAM Equivalent AC Load Circuits
NOVRAM AC Conditions of Test
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing levels
VCC x 0.5
3.3V
1596Ω
3093Ω
10
30pF
FN8124.2
July 3, 2008
X4C105
NOVRAM Read Cycle Specifications
tRC
tCE
CE
tOE
OE
tWES
tWEH
WE
tOHZ
tOLZ
tOH
tLZ
tHZ
D0 - D3
Electrical Specifications
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested.
VCC = 3.0V TO 3.6V
-40°C TO +85°C
SYMBOL
PARAMETER
MIN
MAX
UNIT
tRC
Read Cycle Time
120
ns
tCE
Chip Enable Access Time
50
ns
tOE
Output Enable Access Time
50
ns
tOH
Output Hold From CE or OE High
0
ns
tWES
Write Enable High Set-ups Time
25
ns
tWEH
Write Enable High Hold Time
25
ns
tLZ (Note 7)
0
ns
tOLZ (Note 7) Output Enable to Output in Low Z
Chip Enable to Output in Low Z
0
ns
tHZ (Note 7)
0
50
0
50
Chip Disable to Output in High Z
tOHZ (Note 7) Output Disable to Output in High Z
ns
ns
tSOE (Note 7) OE Setup Prior to Operation in 2-wire Mode
100
ms
tHOE (Note 7) OE Hold Following Operation in 2-wire Mode
100
ms
NOTE:
7. tLZ and tOLZ min.; tSOE and tHOE min; and tHZ and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured,
with CL = 5pF, from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven.
Electrical Specifications
VCC = 3.0V to 3.6V, TA = -40°C to +85°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested.
SYMBOL
PARAMETER
MIN
MAX
UNIT
tWC
Write Cycle Time
120
ns
tWC1
Write Cycle Time
170
ns
tOES
Output Enable HIGH Set-up Time
50
ns
tOEH
Output Enable HIGH Hold Time
50
ns
11
FN8124.2
July 3, 2008
X4C105
Electrical Specifications
VCC = 3.0V to 3.6V, TA = -40°C to +85°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tCW
Chip Enable to End of Write Input
50
ns
tCE
Write Set-up time
0
ns
tCH
Write Hold Time
0
ns
tWP
Write Pulse Width
50
ns
tWP1
Write Pulse Width
100
ns
tWPH
Write Pulse HIGH Recovery Time
50
ns
tDS
Data Set-up to End of Write
40
ns
tDH
Data Hold Time
0
ns
tNDO
New Data Output
50
ns
tSOE (Note 8) OE Set-up Prior to Operation In 2-wire Mode
100
ms
tHOE (Note 8) OE Hold Following Operation in 2-wire Mode
100
ms
tWZ
Write Enable to Output in HIGH-Z
tOW
Output Active From End of Write
0
tCHZ (Note 8) Chip Disable to Output in High Z
0
50
ns
tOHZ (Note 8) Output Disable to Output in High Z
0
50
ns
50
ns
ns
NOTE:
8. tLZ and tOLZ min.; tSOE and tHOE min; and tHZ and tOHZ are periodically sampled and not 100% tested. tHZ max and tOHZ max are measured, with
CL = 5pF, from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven.
NOVRAM WE Controlled Write Cycle
OE
tOES
tCH
tCW
CE
tCE
tOEH
tWP
WE
tWPH
tWC
tDS
D0-D3
(DATA I/O)
tDH
DATA VALID
tNDO
O0-O3
(DATA OUT)
PREVIOUS VALID DATA
12
NEW VALID DATA
FN8124.2
July 3, 2008
X4C105
NOVRAM CE Controlled Write Cycle
OE
tOES
tCW
tOEH
CE
tCE
tCH
tWP
tWPH
WE
tWC
tDS
D0-D3
(DATA IN)
tDH
DATA VALID
tNDO
O0-O3
(DATA OUT)
NEW VALID DATA
PREVIOUS VALID DATA
Low Voltage Detect/Power Cycle Parameters Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production
tested.
SYMBOLS
PARAMETERS
VTRIP
Reset Trip Voltage-blank
tRPD
VCC Detect to Reset Active
tPURST
MIN
TYP
MAX
UNIT
2.80
2.875
2.95
V
500
ns
400
ms
Power-up Reset Time-Out Delay (tPURST Option 1)-Default
100
tF
VCC Fall Time From VCC = 3V to VCC = 2.5V
100
µs
tR
VCC Rise Time From VCC = 2.5V to VCC = 3V
100
µs
tOVT
200
Output Pins Valid after VCC Exceeds VTRIP
200
Reset valid VCC
VRVALID
1
ns
V
Low Voltage Detect and Output Pin Recall
VTRIP
VCC
tPURST
tRPD
tPURST
tF
tR
VRVALID
RST
tOVT
DATA VALID
O0-O3
13
tOVT
DATA VALID
VCC(min)
FN8124.2
July 3, 2008
X4C105
Packaging Information
20-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
.019 (.50)
.029 (.75)
Seating Plane
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN8124.2
July 3, 2008