IRFL9014, SiHFL9014 www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • -60 RDS(on) () VGS = -10 V Qg (Max.) (nC) 0.50 12 Qgs (nC) 3.8 Qgd (nC) 5.1 Configuration Single S SOT-223 DESCRIPTION G D G D Surface mount Available in tape and reel Dynamic dV/dt rating Repetitive avalanche rated Available P-channel Fast switching Ease of paralleling Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SOT-223 package is designed for surface-mounting using vapor phase, infrared, or wave soldering techniques. Its unique package design allows for easy automatic pick-and-place as with other SOT or SOIC packages but has the added advantage of improved thermal performance due to an enlarged tab for heatsinking. Power dissipation of greater than 1.25 W is possible in a typical surface mount application. S D Marking code: FE P-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free SOT-223 SiHFL9014-GE3 IRFL9014PbF SiHFL9014-E3 Lead (Pb)-free SOT-223 SiHFL9014TR-GE3 IRFL9014TRPbF a SiHFL9014T-E3 a Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS -60 Gate-Source Voltage VGS ± 20 VGS at - 10 V Continuous Drain Current TC = 25 °C TC = 100 °C Pulsed Drain Current a ID IDM UNIT V -1.8 -1.1 A -14 Linear Derating Factor 0.025 Linear Derating Factor (PCB Mount) e 0.017 W/°C Single Pulse Avalanche Energy b EAS 140 Repetitive Avalanche Current a IAR -1.8 A Repetitive Avalanche Energy a EAR 0.31 mJ Maximum Power Dissipation Maximum Power Dissipation (PCB TC = 25 °C Mount) e TA = 25 °C Peak Diode Recovery dV/dt c Operating Junction and Storage Temperature Range for 10 s Soldering Recommendations (Peak Temperature) d Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = - 25 V, starting TJ = 25 °C, L = 50 mH, Rg = 25 , IAS = - 1.8 A (see fig. 12). c. ISD - 6.7 A, dI/dt 90 A/μs, VDD VDS, TJ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). S14-1686-Rev. F, 18-Aug-14 PD 3.1 2.0 dV/dt -4.5 TJ, Tstg -55 to +150 300 mJ W V/ns °C Document Number: 91195 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL9014, SiHFL9014 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL TYP. MAX. Maximum Junction-to-Ambient (PCB Mount) a PARAMETER RthJA - 60 Maximum Junction-to-Case (Drain) RthJC - 40 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS VGS = 0 V, ID = 250 μA -60 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - -0.059 - V/°C VGS(th) VDS = VGS, ID = 250 μA -2.0 - -4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs VDS = -60 V, VGS = 0 V - - - 100 VDS = -48 V, VGS = 0 V, TJ = 125 °C - - -500 - - 0.50 1.3 - - S - 270 - - 170 - - 31 - - - 12 ID = 1.1 A b VGS = -10 V VDS = - 25 V, ID = 1.1 A b μA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs - - 3.8 Gate-Drain Charge Qgd - - 5.1 Turn-On Delay Time td(on) - 11 - tr - 63 - - 9.6 - - 31 - - 4.0 - - 6.0 - - - - 1.8 - - - 14 - - - 5.5 Rise Time Turn-Off Delay Time Fall Time td(off) VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VGS = - 10 V ID = - 6.7 A, VDS = - 48 V, see fig. 6 and 13 b VDD = - 30 V, ID = - 6.7 A, Rg = 24 , RD = 4.0 , see fig. 10 b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact pF nC ns D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current a ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = - 1.8 A, VGS = 0 V b TJ = 25 °C, IF = - 6.7 A, dI/dt = 100 A/μs b V - 80 160 ns - 0.096 0.19 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. S14-1686-Rev. F, 18-Aug-14 Document Number: 91195 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL9014, SiHFL9014 www.vishay.com Vishay Siliconix Top -10 V -8.0 V -7.0 V -6.0 V -5.5 V -5.0 V Bottom -4.5 V 101 - ID, Drain Current (A) VGS -15 V 100 4.5 V 10-1 20 µs Pulse Width TC = 25 °C 101 100 10-1 - VDS, Drain-to-Source Voltage (V) 91195_01 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2.5 ID = - 6.7 A VGS = 10 V 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 TJ, Junction Temperature (°C) 91195_04 Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 4 - Normalized On-Resistance vs. Temperature 600 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 101 4.5 V 10-1 Coss 200 Crss 100 - VDS, Drain-to-Source Voltage (V) 25 °C 150 °C 100 10-1 20 µs Pulse Width VDS = - 25 V 4 5 6 7 8 9 - VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S14-1686-Rev. F, 18-Aug-14 101 - VDS, Drain-to-Source Voltage (V) 91195_05 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 20 101 - ID, Drain Current (A) Ciss 300 0 101 Fig. 2 - Typical Output Characteristics, TC = 150 °C 91195_03 400 100 20 µs Pulse Width TC = 150 °C 100 91195_02 Capacitance (pF) VGS -15 V -10 V -8.0 V -7.0 V -6.0 V -5.5 V -5.0 V Bottom -4.5 V Top - VGS, Gate-to-Source Voltage (V) - ID, Drain Current (A) 500 100 20 40 60 80 100 120 140 160 ID = -6.7 A VDS = -48 V 16 VDS = -30 V 12 8 4 For test circuit see figure 13 0 10 0 91195_06 4 8 12 16 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91195 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL9014, SiHFL9014 www.vishay.com Vishay Siliconix 101 150 °C - ID, Drain Current (A) - ISD, Reverse Drain Current (A) 2.0 25 °C 100 1.0 0.5 VGS = 0 V 10-1 1.0 0.0 2.0 3.0 5.0 4.0 6.0 25 - VSD, Source-to-Drain Voltage (V) 91195_07 102 50 125 150 RD VDS VGS 2 10 100 Fig. 9 - Maximum Drain Current vs. Case Temperature Operation in this area limited by RDS(on) 5 75 TC, Case Temperature (°C) 91195_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage - ID, Drain Current (A) 1.5 D.U.T. Rg 100 µs +VDD 5 - 10 V 1 ms 2 1 Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 10 ms 5 0.1 0.1 Fig. 10a - Switching Time Test Circuit TC = 25 °C TJ = 150 °C Single Pulse 2 2 5 1 2 5 10 2 5 102 2 5 td(on) 103 - VDS, Drain-to-Source Voltage (V) 91195_08 td(off) tf tr VGS 10 % Fig. 8 - Maximum Safe Operating Area 90 % VDS Fig. 10b - Switching Time Waveforms Thermal Response (ZτηJC) 102 0 − 0.5 10 0.2 0.1 0.05 1 0.02 PDM 0.01 Single Pulse (Thermal Response) t1 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 0.1 10-2 10-5 91195_11 10-4 10-3 10-2 0.1 1 10 102 103 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S14-1686-Rev. F, 18-Aug-14 Document Number: 91195 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL9014, SiHFL9014 www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS IAS VDS VDS D.U.T Rg + V DD VDD IAS tp - 10 V 0.01 Ω tp VDS Fig. 12b - Unclamped Inductive Waveforms Fig. 12a - Unclamped Inductive Test Circuit EAS, Single Pulse Energy (mJ) 400 ID - 0.80 A - 1.1 A Bottom - 1.8 A Top 300 200 100 0 VDD = - 25 V 25 91195_12c 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG - 10 V 12 V 0.2 µF 0.3 µF QGS - QGD D.U.T. VG + VDS VGS - 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform S14-1686-Rev. F, 18-Aug-14 Fig. 13b - Gate Charge Test Circuit Document Number: 91195 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL9014, SiHFL9014 www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • dV/dt controlled by Rg • ISD controlled by duty factor “D” • D.U.T. - device under test + - VDD Note • Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = - 5 V for logic level and - 3 V drive devices Fig. 14 - For P-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91195. S14-1686-Rev. F, 18-Aug-14 Document Number: 91195 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SOT-223 (HIGH VOLTAGE) B D A 3 0.08 (0.003) B1 C 0.10 (0.004) M C B M A 4 3 H E 0.20 (0.008) M C A M L1 1 2 3 4xL 3xB e θ 0.10 (0.004) M C B M e1 4xC MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. A 1.55 1.80 0.061 0.071 0.033 B 0.65 0.85 0.026 B1 2.95 3.15 0.116 0.124 C 0.25 0.35 0.010 0.014 D 6.30 6.70 0.248 0.264 E 3.30 3.70 0.130 e 2.30 BSC e1 4.60 BSC 0.181 BSC H 6.71 7.29 0.264 L 0.91 - 0.036 L1 θ 0.061 BSC - 0.146 0.0905 BSC 0.287 0.0024 BSC 10' - 10' ECN: S-82109-Rev. A, 15-Sep-08 DWG: 5969 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension do not include mold flash. 4. Outline conforms to JEDEC outline TO-261AA. Document Number: 91363 Revision: 15-Sep-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000