IRFPS38N60L, SiHFPS38N60L Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Superfast Body Diode Eliminates the Need for External Diodes in ZVS Applications 600 RDS(on) () VGS = 10 V Qg (Max.) (nC) 0.12 • Lower Gate Charge Results in Simple Drive Requirements 320 Qgs (nC) 85 Qgd (nC) 160 Configuration Available RoHS* COMPLIANT • Enhanced dV/dt Capabilities Offer Improved Ruggedness • Higher Gate Voltage Threshold Offers Improved Noise Immunity Single D • Compliant to RoHS Directive 2002/95/EC APPLICATIONS Super-247 • Zero Voltage Switching SMPS G • Telecom and Server Power Supplies • Uniterruptible Power Supplies S D G • Motor Control applications S N-Channel MOSFET ORDERING INFORMATION Package Super-247 IRFPS38N60LPbF Lead (Pb)-free SiHFPS38N60L-E3 IRFPS38N60L SnPb SiHFPS38N60L ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current VGS at 10 V TC = 25 °C ID TC = 100 °C Pulsed Drain Currenta UNIT V 38 24 A IDM 150 4.3 W/°C EAS 680 mJ Currenta IAR 38 A Repetitive Avalanche Energya EAR 54 mJ Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque PD 540 W dV/dt 19 V/ns TJ, Tstg - 55 to + 150 for 10 s 6-32 or M3 screw 300d °C 10 lbf · in 1.1 N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 12). b. Starting TJ = 25 °C, L = 0.91 mH, Rg = 25 , IAS = 38 A, dV/dt = 13 V/ns (see fig. 14a). c. ISD 38 A, dI/dt 630 A/μs, VDD VDS, TJ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91259 S11-0111-Rev. B, 07-Feb-11 www.vishay.com 1 IRFPS38N60L, SiHFPS38N60L Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SYMBOL TYP. MAX. UNIT RthJA RthCS RthJC 0.24 - 40 0.22 °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0 V, ID = 250 μA 600 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 410 - mV/°C VGS(th) VDS = VGS, ID = 250 μA 3.0 - 5.0 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS Drain-Source On-State Resistance RDS(on) Forward Transconductance gfs VDS = 600 V, VGS = 0 V - - 50 μA VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 2.0 mA - 0.12 0.15 VDS = 50 V, ID = 23 Ab 20 - - S ID = 23 Ab VGS = 10 V Dynamic Input Capacitance Ciss VGS = 0 V, - 7990 - Output Capacitance Coss VDS = 25 V, - 740 - f = 1.0 MHz, see fig. 5 - 72 - - 350 - - 260 - - - 320 - - 85 - - 160 - 1.2 - - 44 - - 130 - - 92 - - 69 - - - 38 - - 150 TJ = 25 °C, IS = 38 A, VGS = 0 Vb - - 1.5 Reverse Transfer Capacitance Crss Effective Output Capacitance Coss eff. Effective Output Capacitance (Energy Related) Coss eff. (ER) Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time VGS = 0 V VDS = 0 V to 480 Vc RG td(on) tr VGS = 10 V ID = 38 A, VDS = 480 V see fig. 7 and 15b f = 1 MHz, open drain VDD = 300 V, ID = 38 A, td(off) RG = 4.3 , VGS = 10 V, tf see fig. 11a and 11bb pF nC ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Time IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IF = 38 A - 170 250 TJ = 125 °C, dI/dt = 100 A/μsb - 420 630 TJ = 25 °C, IF = 38 A, VGS = 0 Vb - 830 1240 - 2600 3900 - 9.1 14 TJ = 125 °C, dI/dt = 100 TJ = 25 °C A/μsb V ns nC A Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 12). b. Pulse width 300 μs; duty cycle 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising form 0 % to 80 % VDS. Coss eff. (ER) is a fixed capacitance that stores the same energy as Coss while VDS is rising from 0 % to 80 % VDS. www.vishay.com 2 Document Number: 91259 S11-0111-Rev. B, 07-Feb-11 IRFPS38N60L, SiHFPS38N60L Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1000 1000 10 BOTTOM ID, Drain-to-Source Current (Α ) ID, Drain-to-Source Current (A) TOP 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 1 0.1 4.5V 0.01 100 T J = 150°C 10 1 T J = 25°C 0.1 20µs PULSE WIDTH Tj = 25°C 0.001 0.01 0.1 1 10 100 4 VDS, Drain-to-Source Voltage (V) 8 10 12 14 16 VGS , Gate-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics 3.0 100 BOTTOM 10 4.5V 1 20µs PULSE WIDTH Tj = 150°C ID = 38A 2.5 VGS = 10V 2.0 (Normalized) TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V RDS(on) , Drain-to-Source On Resistance 1000 ID, Drain-to-Source Current (A) 6 1.5 1.0 0.5 0.0 0.1 0.1 1 10 100 -60 -40 -20 0 20 40 60 80 100 120 140 160 VDS, Drain-to-Source Voltage (V) T J , Junction Temperature (°C) Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91259 S11-0111-Rev. B, 07-Feb-11 www.vishay.com 3 IRFPS38N60L, SiHFPS38N60L Vishay Siliconix 100000 C, Capacitance(pF) 10000 = 0V, f = 1 MHZ = Cgs + Cgd , Cds SHORTED = Cgd = Cds + Cgd Ciss 1000 Coss 100 Crss 12.0 ID= 38A VGS , Gate-to-Source Voltage (V) VGS Ciss Crss Coss 10.0 VDS= 480V VDS= 300V VDS= 120V 8.0 6.0 4.0 2.0 0.0 10 1 10 100 0 1000 VDS , Drain-to-Source Voltage (V) 50 100 150 200 250 Q G Total Gate Charge (nC) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 50 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 1000.00 ISD, Reverse Drain Current (A) 45 40 100.00 Energy (µJ) 35 30 25 20 15 10 T J = 150°C 10.00 1.00 5 T J = 25°C VGS = 0V 0 0.10 0 100 200 300 400 500 600 700 VDS, Drain-to-Source Voltage (V) Fig. 6 - Typical Output Capacitance Stored Energy vs. VDS www.vishay.com 4 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VSD, Source-to-Drain Voltage (V) Fig. 8 - Typical Source-Drain Diode Forward Voltage Document Number: 91259 S11-0111-Rev. B, 07-Feb-11 IRFPS38N60L, SiHFPS38N60L Vishay Siliconix 1000 RD ID, Drain-to-Source Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) VDS VGS 100 D.U.T. RG 10 V 100µsec 10 + - VDD Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 1msec Fig. 11a - Switching Time Test Circuit 1 Tc = 25°C Tj = 150°C Single Pulse 10msec VDS 90 % 0.1 1 10 100 1000 10000 VDS, Drain-to-Source Voltage (V) Fig. 9 - Maximum Safe Operating Area 10 % VGS 40 td(on) td(off) tf tr Fig. 11b - Switching Time Waveforms 35 ID, Drain Current (A) 30 25 20 15 10 5 0 25 50 75 100 125 150 T C , Case Temperature (°C) Fig. 10 - Maximum Drain Current vs. Case Temperature Thermal Response ( Z thJC ) 1 0.1 D = 0.50 0.20 0.10 0.01 0.05 0.02 0.01 P DM t1 0.001 t2 SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty factor D = 2. Peak T t1/ t 2 J = P DM x Z thJC +T C 0.0001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 91259 S11-0111-Rev. B, 07-Feb-11 www.vishay.com 5 IRFPS38N60L, SiHFPS38N60L Vishay Siliconix VGS(th) Gate threshold Voltage (V) 5.0 VDS 4.5 tp 4.0 3.5 3.0 ID = 250µA 2.5 IAS 2.0 1.5 Fig. 14c - Unclamped Inductive Waveforms 1.0 Current regulator Same type as D.U.T. 0.5 0.0 -75 -50 -25 0 25 50 75 100 125 150 175 50 kΩ 12 V T J , Temperature ( °C ) 0.2 µF 0.3 µF + Fig. 13 - Threshold Voltage vs. Temperature D.U.T. - VDS EAS , Single Pulse Avalanche Energy (mJ) 1400 VGS ID TOP 17A 24A BOTTOM 38A 1200 1000 3 mA IG ID Current sampling resistors Fig. 15a - Basic Gate Charge Waveform 800 600 400 200 QG VGS 0 QGS 25 50 75 100 125 QGD 150 Starting T J , Junction Temperature (°C) Fig. 14a - Maximum Avalanche Energy vs. Drain Current VG Charge Fig. 15b - Gate Charge Test Circuit 15 V L VDS D.U.T RG IAS 20 V tp Driver + - VDD A 0.01Ω Fig. 14b - Unclamped Inductive Test Circuit www.vishay.com 6 Document Number: 91259 S11-0111-Rev. B, 07-Feb-11 IRFPS38N60L, SiHFPS38N60L Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 16 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91259. Document Number: 91259 S11-0111-Rev. B, 07-Feb-11 www.vishay.com 7 Package Information Vishay Siliconix TO-274AA (HIGH VOLTAGE) B A E E4 A D2 E1 A1 R D1 D L1 L Detail “A” C b e A2 0.10 (0.25) M B A M 10° b4 b2 Lead Tip 5° Detail “A” Scale: 2:1 MILLIMETERS DIM. MIN. MAX. INCHES MIN. MAX. MILLIMETERS DIM. MIN. MAX. INCHES MIN. MAX. A 4.70 5.30 0.185 0.209 D1 15.50 16.10 0.610 0.634 A1 1.50 2.50 0.059 0.098 D2 0.70 1.30 0.028 0.051 A2 2.25 2.65 0.089 0.104 E 15.10 16.10 0.594 0.634 b 1.30 1.60 0.051 0.063 E1 13.30 13.90 0.524 0.547 b2 1.80 2.20 0.071 0.087 e b4 3.00 3.25 0.118 0.128 L 13.70 14.70 0.539 0.579 c 0.80 1.20 0.031 0.047 L1 1.00 1.60 0.039 0.063 D 19.80 20.80 0.780 0.819 R 2.00 3.00 0.079 0.118 5.45 BSC 0.215 BSC ECN: S-82247-Rev. A, 06-Oct-08 DWG: 5975 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outer extremes of the plastic body. 3. Outline conforms to JEDEC outline to TO-274AA. Document Number: 91365 Revision: 06-Oct-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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