IRFPS40N50L, SiHFPS40N50L Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Superfast Body Diode Eliminates the Need for External Diodes in ZVS Applications 500 RDS(on) () VGS = 10 V 0.087 Available RoHS* Qg (Max.) (nC) 380 Qgs (nC) 80 • Lower Gate Charge Results in Simpler Drive Requirements 190 • Enhanced dV/dt Capabilities Offer Improved Ruggedness Qgd (nC) Configuration Single COMPLIANT • Higher Gate Voltage Threshold Offers Improved Noise Immunity D • Compliant to RoHS Directive 2002/95/EC Super-247 APPLICATIONS G • Zero Voltage Switching SMPS S • Telecom and Server Power Supplies D G • Uninterruptible Power Supplies S • Motor Control Applications N-Channel MOSFET ORDERING INFORMATION Package Super-247 IRFPS40N50LPbF SiHFPS40N50L-E3 IRFPS40N50L SiHFPS40N50L Lead (Pb)-free SnPb ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 500 Gate-Source Voltage VGS ± 30 Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID UNIT V 46 29 A IDM 180 4.3 W/°C EAS 920 mJ Currenta IAR 46 A Repetitive Avalanche Energya EAR 54 mJ Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) for 10 s PD 540 W dV/dt 34 V/ns TJ, Tstg - 55 to + 150 300d °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 0.86 mH, Rg = 25 , IAS = 46 A (see fig. 12). c. ISD 46 A, dI/dt 550 A/μs, VDD VDS, TJ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91260 S11-0111-Rev. C, 07-Feb-11 www.vishay.com 1 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambienta RthJA - 40 Case-to-Sink, Flat, Greased Surface RthCS 0.24 - Maximum Junction-to-Case (Drain)a RthJC - 0.23 UNIT °C/W Note a. Rth is measured at TJ approximately 90 °C. SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 500 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.60 - VGS(th) VDS = VGS, ID = 250 μA 3.0 - 5.0 V/°C V Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VGS = ± 30 V - - ± 100 VDS = 500 V, VGS = 0 V - - 50 nA μA VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 2.0 mA - 0.087 0.100 S IGSS IDSS RDS(on) ID = 28 Ab VGS = 10 V gfs VDS = 50 V, ID = 46 A 21 - - VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 8110 - - 960 - - 130 - VDS = 1.0 V , f = 1.0 MHz - 11200 - VDS = 400 V , f = 1.0 MHz - 240 - - 440 - - 310 - - - 380 - - 80 nC Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Output Capacitance Coss Effective Output Capacitance Effective Output Capacitance (Energy Related) Total Gate Charge Coss eff. Qg Qgs Gate-Drain Charge Internal Gate Resistance Qgd RG Turn-On Delay Time td(on) Turn-Off Delay Time Fall Time VDS = 0 V to 400 Vc Coss eff. (ER) Gate-Source Charge Rise Time VGS = 0 V tr td(off) VGS = 10 V ID = 46 A, VDS = 400 V, see fig. 7 and 15b f = 1 MHz, open drain VDD = 250 V, ID = 46 A, RG = 0.85 , VGS = 10 V, see fig. 14a and 14bb tf - - - 0.90 190 - - 27 - - 170 - - 50 - - 69 - - - 46 - - 180 pF ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 46 A, VGS = 0 Vb - - 1.5 TJ = 25 °C, IF = 46 A - 170 250 TJ = 125 °C, dI/dt = 100 A/μsb - 220 330 TJ = 25 °C, IS = 46 A, VGS = 0 Vb - 705 1060 TJ = 125 °C, dI/dt = 100 A/μsb - 1.3 2.0 TJ = 25 °C - 9.0 - V ns nC A Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 400 μs; duty cycle 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS. Coss eff. (ER) is a fixed capacitance that stores the same energy as Coss while VDS is rising from 0 % to 80 % VDS. www.vishay.com 2 Document Number: 91260 S11-0111-Rev. C, 07-Feb-11 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1000 1000 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 100 I D , Drain-to-Source Current (A) I D , Drain-to-Source Current (A) TOP 100 10 1 4.5V 0.1 20μs PULSE WIDTH TJ = 25 °C 0.01 0.1 1 10 10 TJ = 25 ° C 1 0.1 100 VDS , Drain-to-Source Voltage (V) RDS(on) , Drain-to-Source On Resistance (Normalized) VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V I D , Drain-to-Source Current (A) 10 4.5V 1 0.1 0.1 20µs PULSE WIDTH TJ = 150 °C 1 10 4 5 6 7 8 9 10 11 Fig. 3 - Typical Transfer Characteristics TOP 100 V DS= 50V 20µs PULSE WIDTH VGS , Gate-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics 1000 TJ = 150° C 100 3.0 ID = 47A 2.5 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 VDS , Drain-to-Source Voltage (V) TJ , Junction Temperature ( ° C) Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91260 S11-0111-Rev. C, 07-Feb-11 www.vishay.com 3 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd C, Capacitance(pF) 100000 Coss = Cds + Cgd 10000 Ciss 1000 Coss 100 Crss VGS , Gate-to-Source Voltage (V) 20 1000000 ID = 47A V DS= 400V V DS= 250V V DS= 100V 15 10 5 10 1 10 100 0 1000 0 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 40 200 300 400 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 1000 ISD , Reverse Drain Current (A) 35 30 Energy (µJ) 100 QG , Total Gate Charge (nC) 100 25 20 15 10 5 TJ = 150° C 10 TJ = 25 ° C 1 0 0 100 200 300 400 500 600 0.1 0.2 V GS = 0 V 0.7 1.2 1.7 2.2 VDS, Drain-to-Source Voltage (V) VSD ,Source-to-Drain Voltage (V) Fig. 6 - Typical Output Capacitance Stored Energy vs. VDS Fig. 8 - Typical Source Drain Diode Forward Voltage www.vishay.com 4 Document Number: 91260 S11-0111-Rev. C, 07-Feb-11 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix RD VDS 50 VGS 40 ID , Drain Current (A) D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 30 Fig. 10a - Switching Time Test Circuit 20 VDS 90 % 10 0 25 50 75 100 125 150 10 % VGS TC , Case Temperature ( °C) td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response(Z thJC ) 1 0.1 D = 0.50 0.01 0.20 0.10 0.05 0.02 0.01 0.001 0.00001 PDM t1 SINGLE PULSE (THERMAL RESPONSE) t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 91260 S11-0111-Rev. C, 07-Feb-11 www.vishay.com 5 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix EAS , Single Pulse Avalanche Energy (mJ) 2000 15 V TOP BOTTOM ID 21A 30A 46A 1500 Driver L VDS D.U.T. RG IAS 20 V tp 1000 + A - VDD 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit VDS 500 0 25 50 75 100 125 150 Starting TJ , Junction Temperature( °C) tp Fig. 12d - Maximum Safe Operating Area Current regulator Same type as D.U.T. IAS 50 kΩ 12 V Fig. 12b - Unclamped Inductive Waveforms 0.2 µF 0.3 µF + D.U.T. 1000 OPERATION IN THIS AREA LIMITED BY RDS(on) - VDS VGS ID , Drain Current (A) 3 mA 100 10us IG ID Current sampling resistors 100us 10 1 Fig. 13a - Gate Charge Test Circuit 1ms TC = 25 °C TJ = 150 °C Single Pulse 10 10ms QG VGS 100 100 QGS VDS , Drain-to-Source Voltage (V) Fig. 12c - Maximum Avalanche Energy vs. Drain Current QGD VG Charge Fig. 13b - Basic Gate Charge Waveform www.vishay.com 6 Document Number: 91260 S11-0111-Rev. C, 07-Feb-11 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91260. Document Number: 91260 S11-0111-Rev. C, 07-Feb-11 www.vishay.com 7 Package Information Vishay Siliconix TO-274AA (HIGH VOLTAGE) B A E E4 A D2 E1 A1 R D1 D L1 L Detail “A” C b e A2 0.10 (0.25) M B A M 10° b4 b2 Lead Tip 5° Detail “A” Scale: 2:1 MILLIMETERS DIM. MIN. MAX. INCHES MIN. MAX. MILLIMETERS DIM. MIN. MAX. INCHES MIN. MAX. A 4.70 5.30 0.185 0.209 D1 15.50 16.10 0.610 0.634 A1 1.50 2.50 0.059 0.098 D2 0.70 1.30 0.028 0.051 A2 2.25 2.65 0.089 0.104 E 15.10 16.10 0.594 0.634 b 1.30 1.60 0.051 0.063 E1 13.30 13.90 0.524 0.547 b2 1.80 2.20 0.071 0.087 e b4 3.00 3.25 0.118 0.128 L 13.70 14.70 0.539 0.579 c 0.80 1.20 0.031 0.047 L1 1.00 1.60 0.039 0.063 D 19.80 20.80 0.780 0.819 R 2.00 3.00 0.079 0.118 5.45 BSC 0.215 BSC ECN: S-82247-Rev. A, 06-Oct-08 DWG: 5975 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outer extremes of the plastic body. 3. Outline conforms to JEDEC outline to TO-274AA. Document Number: 91365 Revision: 06-Oct-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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